musb_core.c 75 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MUSB OTG driver core code
  4. *
  5. * Copyright 2005 Mentor Graphics Corporation
  6. * Copyright (C) 2005-2006 by Texas Instruments
  7. * Copyright (C) 2006-2007 Nokia Corporation
  8. */
  9. /*
  10. * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
  11. *
  12. * This consists of a Host Controller Driver (HCD) and a peripheral
  13. * controller driver implementing the "Gadget" API; OTG support is
  14. * in the works. These are normal Linux-USB controller drivers which
  15. * use IRQs and have no dedicated thread.
  16. *
  17. * This version of the driver has only been used with products from
  18. * Texas Instruments. Those products integrate the Inventra logic
  19. * with other DMA, IRQ, and bus modules, as well as other logic that
  20. * needs to be reflected in this driver.
  21. *
  22. *
  23. * NOTE: the original Mentor code here was pretty much a collection
  24. * of mechanisms that don't seem to have been fully integrated/working
  25. * for *any* Linux kernel version. This version aims at Linux 2.6.now,
  26. * Key open issues include:
  27. *
  28. * - Lack of host-side transaction scheduling, for all transfer types.
  29. * The hardware doesn't do it; instead, software must.
  30. *
  31. * This is not an issue for OTG devices that don't support external
  32. * hubs, but for more "normal" USB hosts it's a user issue that the
  33. * "multipoint" support doesn't scale in the expected ways. That
  34. * includes DaVinci EVM in a common non-OTG mode.
  35. *
  36. * * Control and bulk use dedicated endpoints, and there's as
  37. * yet no mechanism to either (a) reclaim the hardware when
  38. * peripherals are NAKing, which gets complicated with bulk
  39. * endpoints, or (b) use more than a single bulk endpoint in
  40. * each direction.
  41. *
  42. * RESULT: one device may be perceived as blocking another one.
  43. *
  44. * * Interrupt and isochronous will dynamically allocate endpoint
  45. * hardware, but (a) there's no record keeping for bandwidth;
  46. * (b) in the common case that few endpoints are available, there
  47. * is no mechanism to reuse endpoints to talk to multiple devices.
  48. *
  49. * RESULT: At one extreme, bandwidth can be overcommitted in
  50. * some hardware configurations, no faults will be reported.
  51. * At the other extreme, the bandwidth capabilities which do
  52. * exist tend to be severely undercommitted. You can't yet hook
  53. * up both a keyboard and a mouse to an external USB hub.
  54. */
  55. /*
  56. * This gets many kinds of configuration information:
  57. * - Kconfig for everything user-configurable
  58. * - platform_device for addressing, irq, and platform_data
  59. * - platform_data is mostly for board-specific information
  60. * (plus recentrly, SOC or family details)
  61. *
  62. * Most of the conditional compilation will (someday) vanish.
  63. */
  64. #include <linux/module.h>
  65. #include <linux/kernel.h>
  66. #include <linux/sched.h>
  67. #include <linux/slab.h>
  68. #include <linux/list.h>
  69. #include <linux/kobject.h>
  70. #include <linux/prefetch.h>
  71. #include <linux/platform_device.h>
  72. #include <linux/io.h>
  73. #include <linux/dma-mapping.h>
  74. #include <linux/usb.h>
  75. #include <linux/usb/of.h>
  76. #include "musb_core.h"
  77. #include "musb_trace.h"
  78. #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
  79. #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
  80. #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
  81. #define MUSB_VERSION "6.0"
  82. #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
  83. #define MUSB_DRIVER_NAME "musb-hdrc"
  84. const char musb_driver_name[] = MUSB_DRIVER_NAME;
  85. MODULE_DESCRIPTION(DRIVER_INFO);
  86. MODULE_AUTHOR(DRIVER_AUTHOR);
  87. MODULE_LICENSE("GPL");
  88. MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
  89. /*-------------------------------------------------------------------------*/
  90. static inline struct musb *dev_to_musb(struct device *dev)
  91. {
  92. return dev_get_drvdata(dev);
  93. }
  94. enum musb_mode musb_get_mode(struct device *dev)
  95. {
  96. enum usb_dr_mode mode;
  97. mode = usb_get_dr_mode(dev);
  98. switch (mode) {
  99. case USB_DR_MODE_HOST:
  100. return MUSB_HOST;
  101. case USB_DR_MODE_PERIPHERAL:
  102. return MUSB_PERIPHERAL;
  103. case USB_DR_MODE_OTG:
  104. case USB_DR_MODE_UNKNOWN:
  105. default:
  106. return MUSB_OTG;
  107. }
  108. }
  109. EXPORT_SYMBOL_GPL(musb_get_mode);
  110. /*-------------------------------------------------------------------------*/
  111. static int musb_ulpi_read(struct usb_phy *phy, u32 reg)
  112. {
  113. void __iomem *addr = phy->io_priv;
  114. int i = 0;
  115. u8 r;
  116. u8 power;
  117. int ret;
  118. pm_runtime_get_sync(phy->io_dev);
  119. /* Make sure the transceiver is not in low power mode */
  120. power = musb_readb(addr, MUSB_POWER);
  121. power &= ~MUSB_POWER_SUSPENDM;
  122. musb_writeb(addr, MUSB_POWER, power);
  123. /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
  124. * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
  125. */
  126. musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
  127. musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
  128. MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
  129. while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
  130. & MUSB_ULPI_REG_CMPLT)) {
  131. i++;
  132. if (i == 10000) {
  133. ret = -ETIMEDOUT;
  134. goto out;
  135. }
  136. }
  137. r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
  138. r &= ~MUSB_ULPI_REG_CMPLT;
  139. musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
  140. ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
  141. out:
  142. pm_runtime_put(phy->io_dev);
  143. return ret;
  144. }
  145. static int musb_ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
  146. {
  147. void __iomem *addr = phy->io_priv;
  148. int i = 0;
  149. u8 r = 0;
  150. u8 power;
  151. int ret = 0;
  152. pm_runtime_get_sync(phy->io_dev);
  153. /* Make sure the transceiver is not in low power mode */
  154. power = musb_readb(addr, MUSB_POWER);
  155. power &= ~MUSB_POWER_SUSPENDM;
  156. musb_writeb(addr, MUSB_POWER, power);
  157. musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
  158. musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)val);
  159. musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
  160. while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
  161. & MUSB_ULPI_REG_CMPLT)) {
  162. i++;
  163. if (i == 10000) {
  164. ret = -ETIMEDOUT;
  165. goto out;
  166. }
  167. }
  168. r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
  169. r &= ~MUSB_ULPI_REG_CMPLT;
  170. musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
  171. out:
  172. pm_runtime_put(phy->io_dev);
  173. return ret;
  174. }
  175. static struct usb_phy_io_ops musb_ulpi_access = {
  176. .read = musb_ulpi_read,
  177. .write = musb_ulpi_write,
  178. };
  179. /*-------------------------------------------------------------------------*/
  180. static u32 musb_default_fifo_offset(u8 epnum)
  181. {
  182. return 0x20 + (epnum * 4);
  183. }
  184. /* "flat" mapping: each endpoint has its own i/o address */
  185. static void musb_flat_ep_select(void __iomem *mbase, u8 epnum)
  186. {
  187. }
  188. static u32 musb_flat_ep_offset(u8 epnum, u16 offset)
  189. {
  190. return 0x100 + (0x10 * epnum) + offset;
  191. }
  192. /* "indexed" mapping: INDEX register controls register bank select */
  193. static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum)
  194. {
  195. musb_writeb(mbase, MUSB_INDEX, epnum);
  196. }
  197. static u32 musb_indexed_ep_offset(u8 epnum, u16 offset)
  198. {
  199. return 0x10 + offset;
  200. }
  201. static u32 musb_default_busctl_offset(u8 epnum, u16 offset)
  202. {
  203. return 0x80 + (0x08 * epnum) + offset;
  204. }
  205. static u8 musb_default_readb(const void __iomem *addr, unsigned offset)
  206. {
  207. u8 data = __raw_readb(addr + offset);
  208. trace_musb_readb(__builtin_return_address(0), addr, offset, data);
  209. return data;
  210. }
  211. static void musb_default_writeb(void __iomem *addr, unsigned offset, u8 data)
  212. {
  213. trace_musb_writeb(__builtin_return_address(0), addr, offset, data);
  214. __raw_writeb(data, addr + offset);
  215. }
  216. static u16 musb_default_readw(const void __iomem *addr, unsigned offset)
  217. {
  218. u16 data = __raw_readw(addr + offset);
  219. trace_musb_readw(__builtin_return_address(0), addr, offset, data);
  220. return data;
  221. }
  222. static void musb_default_writew(void __iomem *addr, unsigned offset, u16 data)
  223. {
  224. trace_musb_writew(__builtin_return_address(0), addr, offset, data);
  225. __raw_writew(data, addr + offset);
  226. }
  227. /*
  228. * Load an endpoint's FIFO
  229. */
  230. static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
  231. const u8 *src)
  232. {
  233. struct musb *musb = hw_ep->musb;
  234. void __iomem *fifo = hw_ep->fifo;
  235. if (unlikely(len == 0))
  236. return;
  237. prefetch((u8 *)src);
  238. dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
  239. 'T', hw_ep->epnum, fifo, len, src);
  240. /* we can't assume unaligned reads work */
  241. if (likely((0x01 & (unsigned long) src) == 0)) {
  242. u16 index = 0;
  243. /* best case is 32bit-aligned source address */
  244. if ((0x02 & (unsigned long) src) == 0) {
  245. if (len >= 4) {
  246. iowrite32_rep(fifo, src + index, len >> 2);
  247. index += len & ~0x03;
  248. }
  249. if (len & 0x02) {
  250. __raw_writew(*(u16 *)&src[index], fifo);
  251. index += 2;
  252. }
  253. } else {
  254. if (len >= 2) {
  255. iowrite16_rep(fifo, src + index, len >> 1);
  256. index += len & ~0x01;
  257. }
  258. }
  259. if (len & 0x01)
  260. __raw_writeb(src[index], fifo);
  261. } else {
  262. /* byte aligned */
  263. iowrite8_rep(fifo, src, len);
  264. }
  265. }
  266. /*
  267. * Unload an endpoint's FIFO
  268. */
  269. static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
  270. {
  271. struct musb *musb = hw_ep->musb;
  272. void __iomem *fifo = hw_ep->fifo;
  273. if (unlikely(len == 0))
  274. return;
  275. dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
  276. 'R', hw_ep->epnum, fifo, len, dst);
  277. /* we can't assume unaligned writes work */
  278. if (likely((0x01 & (unsigned long) dst) == 0)) {
  279. u16 index = 0;
  280. /* best case is 32bit-aligned destination address */
  281. if ((0x02 & (unsigned long) dst) == 0) {
  282. if (len >= 4) {
  283. ioread32_rep(fifo, dst, len >> 2);
  284. index = len & ~0x03;
  285. }
  286. if (len & 0x02) {
  287. *(u16 *)&dst[index] = __raw_readw(fifo);
  288. index += 2;
  289. }
  290. } else {
  291. if (len >= 2) {
  292. ioread16_rep(fifo, dst, len >> 1);
  293. index = len & ~0x01;
  294. }
  295. }
  296. if (len & 0x01)
  297. dst[index] = __raw_readb(fifo);
  298. } else {
  299. /* byte aligned */
  300. ioread8_rep(fifo, dst, len);
  301. }
  302. }
  303. /*
  304. * Old style IO functions
  305. */
  306. u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
  307. EXPORT_SYMBOL_GPL(musb_readb);
  308. void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
  309. EXPORT_SYMBOL_GPL(musb_writeb);
  310. u16 (*musb_readw)(const void __iomem *addr, unsigned offset);
  311. EXPORT_SYMBOL_GPL(musb_readw);
  312. void (*musb_writew)(void __iomem *addr, unsigned offset, u16 data);
  313. EXPORT_SYMBOL_GPL(musb_writew);
  314. u32 musb_readl(const void __iomem *addr, unsigned offset)
  315. {
  316. u32 data = __raw_readl(addr + offset);
  317. trace_musb_readl(__builtin_return_address(0), addr, offset, data);
  318. return data;
  319. }
  320. EXPORT_SYMBOL_GPL(musb_readl);
  321. void musb_writel(void __iomem *addr, unsigned offset, u32 data)
  322. {
  323. trace_musb_writel(__builtin_return_address(0), addr, offset, data);
  324. __raw_writel(data, addr + offset);
  325. }
  326. EXPORT_SYMBOL_GPL(musb_writel);
  327. #ifndef CONFIG_MUSB_PIO_ONLY
  328. struct dma_controller *
  329. (*musb_dma_controller_create)(struct musb *musb, void __iomem *base);
  330. EXPORT_SYMBOL(musb_dma_controller_create);
  331. void (*musb_dma_controller_destroy)(struct dma_controller *c);
  332. EXPORT_SYMBOL(musb_dma_controller_destroy);
  333. #endif
  334. /*
  335. * New style IO functions
  336. */
  337. void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
  338. {
  339. return hw_ep->musb->io.read_fifo(hw_ep, len, dst);
  340. }
  341. void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
  342. {
  343. return hw_ep->musb->io.write_fifo(hw_ep, len, src);
  344. }
  345. /*-------------------------------------------------------------------------*/
  346. /* for high speed test mode; see USB 2.0 spec 7.1.20 */
  347. static const u8 musb_test_packet[53] = {
  348. /* implicit SYNC then DATA0 to start */
  349. /* JKJKJKJK x9 */
  350. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  351. /* JJKKJJKK x8 */
  352. 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
  353. /* JJJJKKKK x8 */
  354. 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
  355. /* JJJJJJJKKKKKKK x8 */
  356. 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  357. /* JJJJJJJK x8 */
  358. 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
  359. /* JKKKKKKK x10, JK */
  360. 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
  361. /* implicit CRC16 then EOP to end */
  362. };
  363. void musb_load_testpacket(struct musb *musb)
  364. {
  365. void __iomem *regs = musb->endpoints[0].regs;
  366. musb_ep_select(musb->mregs, 0);
  367. musb_write_fifo(musb->control_ep,
  368. sizeof(musb_test_packet), musb_test_packet);
  369. musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
  370. }
  371. /*-------------------------------------------------------------------------*/
  372. /*
  373. * Handles OTG hnp timeouts, such as b_ase0_brst
  374. */
  375. static void musb_otg_timer_func(struct timer_list *t)
  376. {
  377. struct musb *musb = from_timer(musb, t, otg_timer);
  378. unsigned long flags;
  379. spin_lock_irqsave(&musb->lock, flags);
  380. switch (musb->xceiv->otg->state) {
  381. case OTG_STATE_B_WAIT_ACON:
  382. musb_dbg(musb,
  383. "HNP: b_wait_acon timeout; back to b_peripheral");
  384. musb_g_disconnect(musb);
  385. musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
  386. musb->is_active = 0;
  387. break;
  388. case OTG_STATE_A_SUSPEND:
  389. case OTG_STATE_A_WAIT_BCON:
  390. musb_dbg(musb, "HNP: %s timeout",
  391. usb_otg_state_string(musb->xceiv->otg->state));
  392. musb_platform_set_vbus(musb, 0);
  393. musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
  394. break;
  395. default:
  396. musb_dbg(musb, "HNP: Unhandled mode %s",
  397. usb_otg_state_string(musb->xceiv->otg->state));
  398. }
  399. spin_unlock_irqrestore(&musb->lock, flags);
  400. }
  401. /*
  402. * Stops the HNP transition. Caller must take care of locking.
  403. */
  404. void musb_hnp_stop(struct musb *musb)
  405. {
  406. struct usb_hcd *hcd = musb->hcd;
  407. void __iomem *mbase = musb->mregs;
  408. u8 reg;
  409. musb_dbg(musb, "HNP: stop from %s",
  410. usb_otg_state_string(musb->xceiv->otg->state));
  411. switch (musb->xceiv->otg->state) {
  412. case OTG_STATE_A_PERIPHERAL:
  413. musb_g_disconnect(musb);
  414. musb_dbg(musb, "HNP: back to %s",
  415. usb_otg_state_string(musb->xceiv->otg->state));
  416. break;
  417. case OTG_STATE_B_HOST:
  418. musb_dbg(musb, "HNP: Disabling HR");
  419. if (hcd)
  420. hcd->self.is_b_host = 0;
  421. musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
  422. MUSB_DEV_MODE(musb);
  423. reg = musb_readb(mbase, MUSB_POWER);
  424. reg |= MUSB_POWER_SUSPENDM;
  425. musb_writeb(mbase, MUSB_POWER, reg);
  426. /* REVISIT: Start SESSION_REQUEST here? */
  427. break;
  428. default:
  429. musb_dbg(musb, "HNP: Stopping in unknown state %s",
  430. usb_otg_state_string(musb->xceiv->otg->state));
  431. }
  432. /*
  433. * When returning to A state after HNP, avoid hub_port_rebounce(),
  434. * which cause occasional OPT A "Did not receive reset after connect"
  435. * errors.
  436. */
  437. musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
  438. }
  439. static void musb_recover_from_babble(struct musb *musb);
  440. static void musb_handle_intr_resume(struct musb *musb, u8 devctl)
  441. {
  442. musb_dbg(musb, "RESUME (%s)",
  443. usb_otg_state_string(musb->xceiv->otg->state));
  444. if (devctl & MUSB_DEVCTL_HM) {
  445. switch (musb->xceiv->otg->state) {
  446. case OTG_STATE_A_SUSPEND:
  447. /* remote wakeup? */
  448. musb->port1_status |=
  449. (USB_PORT_STAT_C_SUSPEND << 16)
  450. | MUSB_PORT_STAT_RESUME;
  451. musb->rh_timer = jiffies
  452. + msecs_to_jiffies(USB_RESUME_TIMEOUT);
  453. musb->xceiv->otg->state = OTG_STATE_A_HOST;
  454. musb->is_active = 1;
  455. musb_host_resume_root_hub(musb);
  456. schedule_delayed_work(&musb->finish_resume_work,
  457. msecs_to_jiffies(USB_RESUME_TIMEOUT));
  458. break;
  459. case OTG_STATE_B_WAIT_ACON:
  460. musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
  461. musb->is_active = 1;
  462. MUSB_DEV_MODE(musb);
  463. break;
  464. default:
  465. WARNING("bogus %s RESUME (%s)\n",
  466. "host",
  467. usb_otg_state_string(musb->xceiv->otg->state));
  468. }
  469. } else {
  470. switch (musb->xceiv->otg->state) {
  471. case OTG_STATE_A_SUSPEND:
  472. /* possibly DISCONNECT is upcoming */
  473. musb->xceiv->otg->state = OTG_STATE_A_HOST;
  474. musb_host_resume_root_hub(musb);
  475. break;
  476. case OTG_STATE_B_WAIT_ACON:
  477. case OTG_STATE_B_PERIPHERAL:
  478. /* disconnect while suspended? we may
  479. * not get a disconnect irq...
  480. */
  481. if ((devctl & MUSB_DEVCTL_VBUS)
  482. != (3 << MUSB_DEVCTL_VBUS_SHIFT)
  483. ) {
  484. musb->int_usb |= MUSB_INTR_DISCONNECT;
  485. musb->int_usb &= ~MUSB_INTR_SUSPEND;
  486. break;
  487. }
  488. musb_g_resume(musb);
  489. break;
  490. case OTG_STATE_B_IDLE:
  491. musb->int_usb &= ~MUSB_INTR_SUSPEND;
  492. break;
  493. default:
  494. WARNING("bogus %s RESUME (%s)\n",
  495. "peripheral",
  496. usb_otg_state_string(musb->xceiv->otg->state));
  497. }
  498. }
  499. }
  500. /* return IRQ_HANDLED to tell the caller to return immediately */
  501. static irqreturn_t musb_handle_intr_sessreq(struct musb *musb, u8 devctl)
  502. {
  503. void __iomem *mbase = musb->mregs;
  504. if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
  505. && (devctl & MUSB_DEVCTL_BDEVICE)) {
  506. musb_dbg(musb, "SessReq while on B state");
  507. return IRQ_HANDLED;
  508. }
  509. musb_dbg(musb, "SESSION_REQUEST (%s)",
  510. usb_otg_state_string(musb->xceiv->otg->state));
  511. /* IRQ arrives from ID pin sense or (later, if VBUS power
  512. * is removed) SRP. responses are time critical:
  513. * - turn on VBUS (with silicon-specific mechanism)
  514. * - go through A_WAIT_VRISE
  515. * - ... to A_WAIT_BCON.
  516. * a_wait_vrise_tmout triggers VBUS_ERROR transitions
  517. */
  518. musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
  519. musb->ep0_stage = MUSB_EP0_START;
  520. musb->xceiv->otg->state = OTG_STATE_A_IDLE;
  521. MUSB_HST_MODE(musb);
  522. musb_platform_set_vbus(musb, 1);
  523. return IRQ_NONE;
  524. }
  525. static void musb_handle_intr_vbuserr(struct musb *musb, u8 devctl)
  526. {
  527. int ignore = 0;
  528. /* During connection as an A-Device, we may see a short
  529. * current spikes causing voltage drop, because of cable
  530. * and peripheral capacitance combined with vbus draw.
  531. * (So: less common with truly self-powered devices, where
  532. * vbus doesn't act like a power supply.)
  533. *
  534. * Such spikes are short; usually less than ~500 usec, max
  535. * of ~2 msec. That is, they're not sustained overcurrent
  536. * errors, though they're reported using VBUSERROR irqs.
  537. *
  538. * Workarounds: (a) hardware: use self powered devices.
  539. * (b) software: ignore non-repeated VBUS errors.
  540. *
  541. * REVISIT: do delays from lots of DEBUG_KERNEL checks
  542. * make trouble here, keeping VBUS < 4.4V ?
  543. */
  544. switch (musb->xceiv->otg->state) {
  545. case OTG_STATE_A_HOST:
  546. /* recovery is dicey once we've gotten past the
  547. * initial stages of enumeration, but if VBUS
  548. * stayed ok at the other end of the link, and
  549. * another reset is due (at least for high speed,
  550. * to redo the chirp etc), it might work OK...
  551. */
  552. case OTG_STATE_A_WAIT_BCON:
  553. case OTG_STATE_A_WAIT_VRISE:
  554. if (musb->vbuserr_retry) {
  555. void __iomem *mbase = musb->mregs;
  556. musb->vbuserr_retry--;
  557. ignore = 1;
  558. devctl |= MUSB_DEVCTL_SESSION;
  559. musb_writeb(mbase, MUSB_DEVCTL, devctl);
  560. } else {
  561. musb->port1_status |=
  562. USB_PORT_STAT_OVERCURRENT
  563. | (USB_PORT_STAT_C_OVERCURRENT << 16);
  564. }
  565. break;
  566. default:
  567. break;
  568. }
  569. dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
  570. "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
  571. usb_otg_state_string(musb->xceiv->otg->state),
  572. devctl,
  573. ({ char *s;
  574. switch (devctl & MUSB_DEVCTL_VBUS) {
  575. case 0 << MUSB_DEVCTL_VBUS_SHIFT:
  576. s = "<SessEnd"; break;
  577. case 1 << MUSB_DEVCTL_VBUS_SHIFT:
  578. s = "<AValid"; break;
  579. case 2 << MUSB_DEVCTL_VBUS_SHIFT:
  580. s = "<VBusValid"; break;
  581. /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
  582. default:
  583. s = "VALID"; break;
  584. } s; }),
  585. VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
  586. musb->port1_status);
  587. /* go through A_WAIT_VFALL then start a new session */
  588. if (!ignore)
  589. musb_platform_set_vbus(musb, 0);
  590. }
  591. static void musb_handle_intr_suspend(struct musb *musb, u8 devctl)
  592. {
  593. musb_dbg(musb, "SUSPEND (%s) devctl %02x",
  594. usb_otg_state_string(musb->xceiv->otg->state), devctl);
  595. switch (musb->xceiv->otg->state) {
  596. case OTG_STATE_A_PERIPHERAL:
  597. /* We also come here if the cable is removed, since
  598. * this silicon doesn't report ID-no-longer-grounded.
  599. *
  600. * We depend on T(a_wait_bcon) to shut us down, and
  601. * hope users don't do anything dicey during this
  602. * undesired detour through A_WAIT_BCON.
  603. */
  604. musb_hnp_stop(musb);
  605. musb_host_resume_root_hub(musb);
  606. musb_root_disconnect(musb);
  607. musb_platform_try_idle(musb, jiffies
  608. + msecs_to_jiffies(musb->a_wait_bcon
  609. ? : OTG_TIME_A_WAIT_BCON));
  610. break;
  611. case OTG_STATE_B_IDLE:
  612. if (!musb->is_active)
  613. break;
  614. /* fall through */
  615. case OTG_STATE_B_PERIPHERAL:
  616. musb_g_suspend(musb);
  617. musb->is_active = musb->g.b_hnp_enable;
  618. if (musb->is_active) {
  619. musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON;
  620. musb_dbg(musb, "HNP: Setting timer for b_ase0_brst");
  621. mod_timer(&musb->otg_timer, jiffies
  622. + msecs_to_jiffies(
  623. OTG_TIME_B_ASE0_BRST));
  624. }
  625. break;
  626. case OTG_STATE_A_WAIT_BCON:
  627. if (musb->a_wait_bcon != 0)
  628. musb_platform_try_idle(musb, jiffies
  629. + msecs_to_jiffies(musb->a_wait_bcon));
  630. break;
  631. case OTG_STATE_A_HOST:
  632. musb->xceiv->otg->state = OTG_STATE_A_SUSPEND;
  633. musb->is_active = musb->hcd->self.b_hnp_enable;
  634. break;
  635. case OTG_STATE_B_HOST:
  636. /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
  637. musb_dbg(musb, "REVISIT: SUSPEND as B_HOST");
  638. break;
  639. default:
  640. /* "should not happen" */
  641. musb->is_active = 0;
  642. break;
  643. }
  644. }
  645. static void musb_handle_intr_connect(struct musb *musb, u8 devctl, u8 int_usb)
  646. {
  647. struct usb_hcd *hcd = musb->hcd;
  648. musb->is_active = 1;
  649. musb->ep0_stage = MUSB_EP0_START;
  650. musb->intrtxe = musb->epmask;
  651. musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
  652. musb->intrrxe = musb->epmask & 0xfffe;
  653. musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
  654. musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
  655. musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
  656. |USB_PORT_STAT_HIGH_SPEED
  657. |USB_PORT_STAT_ENABLE
  658. );
  659. musb->port1_status |= USB_PORT_STAT_CONNECTION
  660. |(USB_PORT_STAT_C_CONNECTION << 16);
  661. /* high vs full speed is just a guess until after reset */
  662. if (devctl & MUSB_DEVCTL_LSDEV)
  663. musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
  664. /* indicate new connection to OTG machine */
  665. switch (musb->xceiv->otg->state) {
  666. case OTG_STATE_B_PERIPHERAL:
  667. if (int_usb & MUSB_INTR_SUSPEND) {
  668. musb_dbg(musb, "HNP: SUSPEND+CONNECT, now b_host");
  669. int_usb &= ~MUSB_INTR_SUSPEND;
  670. goto b_host;
  671. } else
  672. musb_dbg(musb, "CONNECT as b_peripheral???");
  673. break;
  674. case OTG_STATE_B_WAIT_ACON:
  675. musb_dbg(musb, "HNP: CONNECT, now b_host");
  676. b_host:
  677. musb->xceiv->otg->state = OTG_STATE_B_HOST;
  678. if (musb->hcd)
  679. musb->hcd->self.is_b_host = 1;
  680. del_timer(&musb->otg_timer);
  681. break;
  682. default:
  683. if ((devctl & MUSB_DEVCTL_VBUS)
  684. == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
  685. musb->xceiv->otg->state = OTG_STATE_A_HOST;
  686. if (hcd)
  687. hcd->self.is_b_host = 0;
  688. }
  689. break;
  690. }
  691. musb_host_poke_root_hub(musb);
  692. musb_dbg(musb, "CONNECT (%s) devctl %02x",
  693. usb_otg_state_string(musb->xceiv->otg->state), devctl);
  694. }
  695. static void musb_handle_intr_disconnect(struct musb *musb, u8 devctl)
  696. {
  697. musb_dbg(musb, "DISCONNECT (%s) as %s, devctl %02x",
  698. usb_otg_state_string(musb->xceiv->otg->state),
  699. MUSB_MODE(musb), devctl);
  700. switch (musb->xceiv->otg->state) {
  701. case OTG_STATE_A_HOST:
  702. case OTG_STATE_A_SUSPEND:
  703. musb_host_resume_root_hub(musb);
  704. musb_root_disconnect(musb);
  705. if (musb->a_wait_bcon != 0)
  706. musb_platform_try_idle(musb, jiffies
  707. + msecs_to_jiffies(musb->a_wait_bcon));
  708. break;
  709. case OTG_STATE_B_HOST:
  710. /* REVISIT this behaves for "real disconnect"
  711. * cases; make sure the other transitions from
  712. * from B_HOST act right too. The B_HOST code
  713. * in hnp_stop() is currently not used...
  714. */
  715. musb_root_disconnect(musb);
  716. if (musb->hcd)
  717. musb->hcd->self.is_b_host = 0;
  718. musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
  719. MUSB_DEV_MODE(musb);
  720. musb_g_disconnect(musb);
  721. break;
  722. case OTG_STATE_A_PERIPHERAL:
  723. musb_hnp_stop(musb);
  724. musb_root_disconnect(musb);
  725. /* FALLTHROUGH */
  726. case OTG_STATE_B_WAIT_ACON:
  727. /* FALLTHROUGH */
  728. case OTG_STATE_B_PERIPHERAL:
  729. case OTG_STATE_B_IDLE:
  730. musb_g_disconnect(musb);
  731. break;
  732. default:
  733. WARNING("unhandled DISCONNECT transition (%s)\n",
  734. usb_otg_state_string(musb->xceiv->otg->state));
  735. break;
  736. }
  737. }
  738. /*
  739. * mentor saves a bit: bus reset and babble share the same irq.
  740. * only host sees babble; only peripheral sees bus reset.
  741. */
  742. static void musb_handle_intr_reset(struct musb *musb)
  743. {
  744. if (is_host_active(musb)) {
  745. /*
  746. * When BABBLE happens what we can depends on which
  747. * platform MUSB is running, because some platforms
  748. * implemented proprietary means for 'recovering' from
  749. * Babble conditions. One such platform is AM335x. In
  750. * most cases, however, the only thing we can do is
  751. * drop the session.
  752. */
  753. dev_err(musb->controller, "Babble\n");
  754. musb_recover_from_babble(musb);
  755. } else {
  756. musb_dbg(musb, "BUS RESET as %s",
  757. usb_otg_state_string(musb->xceiv->otg->state));
  758. switch (musb->xceiv->otg->state) {
  759. case OTG_STATE_A_SUSPEND:
  760. musb_g_reset(musb);
  761. /* FALLTHROUGH */
  762. case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
  763. /* never use invalid T(a_wait_bcon) */
  764. musb_dbg(musb, "HNP: in %s, %d msec timeout",
  765. usb_otg_state_string(musb->xceiv->otg->state),
  766. TA_WAIT_BCON(musb));
  767. mod_timer(&musb->otg_timer, jiffies
  768. + msecs_to_jiffies(TA_WAIT_BCON(musb)));
  769. break;
  770. case OTG_STATE_A_PERIPHERAL:
  771. del_timer(&musb->otg_timer);
  772. musb_g_reset(musb);
  773. break;
  774. case OTG_STATE_B_WAIT_ACON:
  775. musb_dbg(musb, "HNP: RESET (%s), to b_peripheral",
  776. usb_otg_state_string(musb->xceiv->otg->state));
  777. musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
  778. musb_g_reset(musb);
  779. break;
  780. case OTG_STATE_B_IDLE:
  781. musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
  782. /* FALLTHROUGH */
  783. case OTG_STATE_B_PERIPHERAL:
  784. musb_g_reset(musb);
  785. break;
  786. default:
  787. musb_dbg(musb, "Unhandled BUS RESET as %s",
  788. usb_otg_state_string(musb->xceiv->otg->state));
  789. }
  790. }
  791. }
  792. /*
  793. * Interrupt Service Routine to record USB "global" interrupts.
  794. * Since these do not happen often and signify things of
  795. * paramount importance, it seems OK to check them individually;
  796. * the order of the tests is specified in the manual
  797. *
  798. * @param musb instance pointer
  799. * @param int_usb register contents
  800. * @param devctl
  801. * @param power
  802. */
  803. static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
  804. u8 devctl)
  805. {
  806. irqreturn_t handled = IRQ_NONE;
  807. musb_dbg(musb, "<== DevCtl=%02x, int_usb=0x%x", devctl, int_usb);
  808. /* in host mode, the peripheral may issue remote wakeup.
  809. * in peripheral mode, the host may resume the link.
  810. * spurious RESUME irqs happen too, paired with SUSPEND.
  811. */
  812. if (int_usb & MUSB_INTR_RESUME) {
  813. musb_handle_intr_resume(musb, devctl);
  814. handled = IRQ_HANDLED;
  815. }
  816. /* see manual for the order of the tests */
  817. if (int_usb & MUSB_INTR_SESSREQ) {
  818. if (musb_handle_intr_sessreq(musb, devctl))
  819. return IRQ_HANDLED;
  820. handled = IRQ_HANDLED;
  821. }
  822. if (int_usb & MUSB_INTR_VBUSERROR) {
  823. musb_handle_intr_vbuserr(musb, devctl);
  824. handled = IRQ_HANDLED;
  825. }
  826. if (int_usb & MUSB_INTR_SUSPEND) {
  827. musb_handle_intr_suspend(musb, devctl);
  828. handled = IRQ_HANDLED;
  829. }
  830. if (int_usb & MUSB_INTR_CONNECT) {
  831. musb_handle_intr_connect(musb, devctl, int_usb);
  832. handled = IRQ_HANDLED;
  833. }
  834. if (int_usb & MUSB_INTR_DISCONNECT) {
  835. musb_handle_intr_disconnect(musb, devctl);
  836. handled = IRQ_HANDLED;
  837. }
  838. if (int_usb & MUSB_INTR_RESET) {
  839. musb_handle_intr_reset(musb);
  840. handled = IRQ_HANDLED;
  841. }
  842. #if 0
  843. /* REVISIT ... this would be for multiplexing periodic endpoints, or
  844. * supporting transfer phasing to prevent exceeding ISO bandwidth
  845. * limits of a given frame or microframe.
  846. *
  847. * It's not needed for peripheral side, which dedicates endpoints;
  848. * though it _might_ use SOF irqs for other purposes.
  849. *
  850. * And it's not currently needed for host side, which also dedicates
  851. * endpoints, relies on TX/RX interval registers, and isn't claimed
  852. * to support ISO transfers yet.
  853. */
  854. if (int_usb & MUSB_INTR_SOF) {
  855. void __iomem *mbase = musb->mregs;
  856. struct musb_hw_ep *ep;
  857. u8 epnum;
  858. u16 frame;
  859. dev_dbg(musb->controller, "START_OF_FRAME\n");
  860. handled = IRQ_HANDLED;
  861. /* start any periodic Tx transfers waiting for current frame */
  862. frame = musb_readw(mbase, MUSB_FRAME);
  863. ep = musb->endpoints;
  864. for (epnum = 1; (epnum < musb->nr_endpoints)
  865. && (musb->epmask >= (1 << epnum));
  866. epnum++, ep++) {
  867. /*
  868. * FIXME handle framecounter wraps (12 bits)
  869. * eliminate duplicated StartUrb logic
  870. */
  871. if (ep->dwWaitFrame >= frame) {
  872. ep->dwWaitFrame = 0;
  873. pr_debug("SOF --> periodic TX%s on %d\n",
  874. ep->tx_channel ? " DMA" : "",
  875. epnum);
  876. if (!ep->tx_channel)
  877. musb_h_tx_start(musb, epnum);
  878. else
  879. cppi_hostdma_start(musb, epnum);
  880. }
  881. } /* end of for loop */
  882. }
  883. #endif
  884. schedule_delayed_work(&musb->irq_work, 0);
  885. return handled;
  886. }
  887. /*-------------------------------------------------------------------------*/
  888. static void musb_disable_interrupts(struct musb *musb)
  889. {
  890. void __iomem *mbase = musb->mregs;
  891. u16 temp;
  892. /* disable interrupts */
  893. musb_writeb(mbase, MUSB_INTRUSBE, 0);
  894. musb->intrtxe = 0;
  895. musb_writew(mbase, MUSB_INTRTXE, 0);
  896. musb->intrrxe = 0;
  897. musb_writew(mbase, MUSB_INTRRXE, 0);
  898. /* flush pending interrupts */
  899. temp = musb_readb(mbase, MUSB_INTRUSB);
  900. temp = musb_readw(mbase, MUSB_INTRTX);
  901. temp = musb_readw(mbase, MUSB_INTRRX);
  902. }
  903. static void musb_enable_interrupts(struct musb *musb)
  904. {
  905. void __iomem *regs = musb->mregs;
  906. /* Set INT enable registers, enable interrupts */
  907. musb->intrtxe = musb->epmask;
  908. musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
  909. musb->intrrxe = musb->epmask & 0xfffe;
  910. musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
  911. musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
  912. }
  913. /*
  914. * Program the HDRC to start (enable interrupts, dma, etc.).
  915. */
  916. void musb_start(struct musb *musb)
  917. {
  918. void __iomem *regs = musb->mregs;
  919. u8 devctl = musb_readb(regs, MUSB_DEVCTL);
  920. u8 power;
  921. musb_dbg(musb, "<== devctl %02x", devctl);
  922. musb_enable_interrupts(musb);
  923. musb_writeb(regs, MUSB_TESTMODE, 0);
  924. power = MUSB_POWER_ISOUPDATE;
  925. /*
  926. * treating UNKNOWN as unspecified maximum speed, in which case
  927. * we will default to high-speed.
  928. */
  929. if (musb->config->maximum_speed == USB_SPEED_HIGH ||
  930. musb->config->maximum_speed == USB_SPEED_UNKNOWN)
  931. power |= MUSB_POWER_HSENAB;
  932. musb_writeb(regs, MUSB_POWER, power);
  933. musb->is_active = 0;
  934. devctl = musb_readb(regs, MUSB_DEVCTL);
  935. devctl &= ~MUSB_DEVCTL_SESSION;
  936. /* session started after:
  937. * (a) ID-grounded irq, host mode;
  938. * (b) vbus present/connect IRQ, peripheral mode;
  939. * (c) peripheral initiates, using SRP
  940. */
  941. if (musb->port_mode != MUSB_HOST &&
  942. musb->xceiv->otg->state != OTG_STATE_A_WAIT_BCON &&
  943. (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
  944. musb->is_active = 1;
  945. } else {
  946. devctl |= MUSB_DEVCTL_SESSION;
  947. }
  948. musb_platform_enable(musb);
  949. musb_writeb(regs, MUSB_DEVCTL, devctl);
  950. }
  951. /*
  952. * Make the HDRC stop (disable interrupts, etc.);
  953. * reversible by musb_start
  954. * called on gadget driver unregister
  955. * with controller locked, irqs blocked
  956. * acts as a NOP unless some role activated the hardware
  957. */
  958. void musb_stop(struct musb *musb)
  959. {
  960. /* stop IRQs, timers, ... */
  961. musb_platform_disable(musb);
  962. musb_disable_interrupts(musb);
  963. musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
  964. /* FIXME
  965. * - mark host and/or peripheral drivers unusable/inactive
  966. * - disable DMA (and enable it in HdrcStart)
  967. * - make sure we can musb_start() after musb_stop(); with
  968. * OTG mode, gadget driver module rmmod/modprobe cycles that
  969. * - ...
  970. */
  971. musb_platform_try_idle(musb, 0);
  972. }
  973. /*-------------------------------------------------------------------------*/
  974. /*
  975. * The silicon either has hard-wired endpoint configurations, or else
  976. * "dynamic fifo" sizing. The driver has support for both, though at this
  977. * writing only the dynamic sizing is very well tested. Since we switched
  978. * away from compile-time hardware parameters, we can no longer rely on
  979. * dead code elimination to leave only the relevant one in the object file.
  980. *
  981. * We don't currently use dynamic fifo setup capability to do anything
  982. * more than selecting one of a bunch of predefined configurations.
  983. */
  984. static ushort fifo_mode;
  985. /* "modprobe ... fifo_mode=1" etc */
  986. module_param(fifo_mode, ushort, 0);
  987. MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
  988. /*
  989. * tables defining fifo_mode values. define more if you like.
  990. * for host side, make sure both halves of ep1 are set up.
  991. */
  992. /* mode 0 - fits in 2KB */
  993. static struct musb_fifo_cfg mode_0_cfg[] = {
  994. { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
  995. { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
  996. { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
  997. { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
  998. { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
  999. };
  1000. /* mode 1 - fits in 4KB */
  1001. static struct musb_fifo_cfg mode_1_cfg[] = {
  1002. { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
  1003. { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
  1004. { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
  1005. { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
  1006. { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
  1007. };
  1008. /* mode 2 - fits in 4KB */
  1009. static struct musb_fifo_cfg mode_2_cfg[] = {
  1010. { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
  1011. { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
  1012. { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
  1013. { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
  1014. { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 960, },
  1015. { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 1024, },
  1016. };
  1017. /* mode 3 - fits in 4KB */
  1018. static struct musb_fifo_cfg mode_3_cfg[] = {
  1019. { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
  1020. { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
  1021. { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
  1022. { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
  1023. { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
  1024. { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
  1025. };
  1026. /* mode 4 - fits in 16KB */
  1027. static struct musb_fifo_cfg mode_4_cfg[] = {
  1028. { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
  1029. { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
  1030. { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
  1031. { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
  1032. { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
  1033. { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
  1034. { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
  1035. { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
  1036. { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
  1037. { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
  1038. { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
  1039. { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
  1040. { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
  1041. { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
  1042. { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
  1043. { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
  1044. { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
  1045. { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
  1046. { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
  1047. { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
  1048. { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
  1049. { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
  1050. { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
  1051. { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
  1052. { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
  1053. { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
  1054. { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
  1055. };
  1056. /* mode 5 - fits in 8KB */
  1057. static struct musb_fifo_cfg mode_5_cfg[] = {
  1058. { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
  1059. { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
  1060. { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
  1061. { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
  1062. { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
  1063. { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
  1064. { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
  1065. { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
  1066. { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
  1067. { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
  1068. { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
  1069. { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
  1070. { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
  1071. { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
  1072. { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
  1073. { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
  1074. { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
  1075. { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
  1076. { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
  1077. { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
  1078. { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
  1079. { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
  1080. { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
  1081. { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
  1082. { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
  1083. { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
  1084. { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
  1085. };
  1086. /*
  1087. * configure a fifo; for non-shared endpoints, this may be called
  1088. * once for a tx fifo and once for an rx fifo.
  1089. *
  1090. * returns negative errno or offset for next fifo.
  1091. */
  1092. static int
  1093. fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
  1094. const struct musb_fifo_cfg *cfg, u16 offset)
  1095. {
  1096. void __iomem *mbase = musb->mregs;
  1097. int size = 0;
  1098. u16 maxpacket = cfg->maxpacket;
  1099. u16 c_off = offset >> 3;
  1100. u8 c_size;
  1101. /* expect hw_ep has already been zero-initialized */
  1102. size = ffs(max(maxpacket, (u16) 8)) - 1;
  1103. maxpacket = 1 << size;
  1104. c_size = size - 3;
  1105. if (cfg->mode == BUF_DOUBLE) {
  1106. if ((offset + (maxpacket << 1)) >
  1107. (1 << (musb->config->ram_bits + 2)))
  1108. return -EMSGSIZE;
  1109. c_size |= MUSB_FIFOSZ_DPB;
  1110. } else {
  1111. if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
  1112. return -EMSGSIZE;
  1113. }
  1114. /* configure the FIFO */
  1115. musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
  1116. /* EP0 reserved endpoint for control, bidirectional;
  1117. * EP1 reserved for bulk, two unidirectional halves.
  1118. */
  1119. if (hw_ep->epnum == 1)
  1120. musb->bulk_ep = hw_ep;
  1121. /* REVISIT error check: be sure ep0 can both rx and tx ... */
  1122. switch (cfg->style) {
  1123. case FIFO_TX:
  1124. musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
  1125. musb_writew(mbase, MUSB_TXFIFOADD, c_off);
  1126. hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
  1127. hw_ep->max_packet_sz_tx = maxpacket;
  1128. break;
  1129. case FIFO_RX:
  1130. musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
  1131. musb_writew(mbase, MUSB_RXFIFOADD, c_off);
  1132. hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
  1133. hw_ep->max_packet_sz_rx = maxpacket;
  1134. break;
  1135. case FIFO_RXTX:
  1136. musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
  1137. musb_writew(mbase, MUSB_TXFIFOADD, c_off);
  1138. hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
  1139. hw_ep->max_packet_sz_rx = maxpacket;
  1140. musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
  1141. musb_writew(mbase, MUSB_RXFIFOADD, c_off);
  1142. hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
  1143. hw_ep->max_packet_sz_tx = maxpacket;
  1144. hw_ep->is_shared_fifo = true;
  1145. break;
  1146. }
  1147. /* NOTE rx and tx endpoint irqs aren't managed separately,
  1148. * which happens to be ok
  1149. */
  1150. musb->epmask |= (1 << hw_ep->epnum);
  1151. return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
  1152. }
  1153. static struct musb_fifo_cfg ep0_cfg = {
  1154. .style = FIFO_RXTX, .maxpacket = 64,
  1155. };
  1156. static int ep_config_from_table(struct musb *musb)
  1157. {
  1158. const struct musb_fifo_cfg *cfg;
  1159. unsigned i, n;
  1160. int offset;
  1161. struct musb_hw_ep *hw_ep = musb->endpoints;
  1162. if (musb->config->fifo_cfg) {
  1163. cfg = musb->config->fifo_cfg;
  1164. n = musb->config->fifo_cfg_size;
  1165. goto done;
  1166. }
  1167. switch (fifo_mode) {
  1168. default:
  1169. fifo_mode = 0;
  1170. /* FALLTHROUGH */
  1171. case 0:
  1172. cfg = mode_0_cfg;
  1173. n = ARRAY_SIZE(mode_0_cfg);
  1174. break;
  1175. case 1:
  1176. cfg = mode_1_cfg;
  1177. n = ARRAY_SIZE(mode_1_cfg);
  1178. break;
  1179. case 2:
  1180. cfg = mode_2_cfg;
  1181. n = ARRAY_SIZE(mode_2_cfg);
  1182. break;
  1183. case 3:
  1184. cfg = mode_3_cfg;
  1185. n = ARRAY_SIZE(mode_3_cfg);
  1186. break;
  1187. case 4:
  1188. cfg = mode_4_cfg;
  1189. n = ARRAY_SIZE(mode_4_cfg);
  1190. break;
  1191. case 5:
  1192. cfg = mode_5_cfg;
  1193. n = ARRAY_SIZE(mode_5_cfg);
  1194. break;
  1195. }
  1196. pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode);
  1197. done:
  1198. offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
  1199. /* assert(offset > 0) */
  1200. /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
  1201. * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
  1202. */
  1203. for (i = 0; i < n; i++) {
  1204. u8 epn = cfg->hw_ep_num;
  1205. if (epn >= musb->config->num_eps) {
  1206. pr_debug("%s: invalid ep %d\n",
  1207. musb_driver_name, epn);
  1208. return -EINVAL;
  1209. }
  1210. offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
  1211. if (offset < 0) {
  1212. pr_debug("%s: mem overrun, ep %d\n",
  1213. musb_driver_name, epn);
  1214. return offset;
  1215. }
  1216. epn++;
  1217. musb->nr_endpoints = max(epn, musb->nr_endpoints);
  1218. }
  1219. pr_debug("%s: %d/%d max ep, %d/%d memory\n",
  1220. musb_driver_name,
  1221. n + 1, musb->config->num_eps * 2 - 1,
  1222. offset, (1 << (musb->config->ram_bits + 2)));
  1223. if (!musb->bulk_ep) {
  1224. pr_debug("%s: missing bulk\n", musb_driver_name);
  1225. return -EINVAL;
  1226. }
  1227. return 0;
  1228. }
  1229. /*
  1230. * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
  1231. * @param musb the controller
  1232. */
  1233. static int ep_config_from_hw(struct musb *musb)
  1234. {
  1235. u8 epnum = 0;
  1236. struct musb_hw_ep *hw_ep;
  1237. void __iomem *mbase = musb->mregs;
  1238. int ret = 0;
  1239. musb_dbg(musb, "<== static silicon ep config");
  1240. /* FIXME pick up ep0 maxpacket size */
  1241. for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
  1242. musb_ep_select(mbase, epnum);
  1243. hw_ep = musb->endpoints + epnum;
  1244. ret = musb_read_fifosize(musb, hw_ep, epnum);
  1245. if (ret < 0)
  1246. break;
  1247. /* FIXME set up hw_ep->{rx,tx}_double_buffered */
  1248. /* pick an RX/TX endpoint for bulk */
  1249. if (hw_ep->max_packet_sz_tx < 512
  1250. || hw_ep->max_packet_sz_rx < 512)
  1251. continue;
  1252. /* REVISIT: this algorithm is lazy, we should at least
  1253. * try to pick a double buffered endpoint.
  1254. */
  1255. if (musb->bulk_ep)
  1256. continue;
  1257. musb->bulk_ep = hw_ep;
  1258. }
  1259. if (!musb->bulk_ep) {
  1260. pr_debug("%s: missing bulk\n", musb_driver_name);
  1261. return -EINVAL;
  1262. }
  1263. return 0;
  1264. }
  1265. enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
  1266. /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
  1267. * configure endpoints, or take their config from silicon
  1268. */
  1269. static int musb_core_init(u16 musb_type, struct musb *musb)
  1270. {
  1271. u8 reg;
  1272. char *type;
  1273. char aInfo[90];
  1274. void __iomem *mbase = musb->mregs;
  1275. int status = 0;
  1276. int i;
  1277. /* log core options (read using indexed model) */
  1278. reg = musb_read_configdata(mbase);
  1279. strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
  1280. if (reg & MUSB_CONFIGDATA_DYNFIFO) {
  1281. strcat(aInfo, ", dyn FIFOs");
  1282. musb->dyn_fifo = true;
  1283. }
  1284. if (reg & MUSB_CONFIGDATA_MPRXE) {
  1285. strcat(aInfo, ", bulk combine");
  1286. musb->bulk_combine = true;
  1287. }
  1288. if (reg & MUSB_CONFIGDATA_MPTXE) {
  1289. strcat(aInfo, ", bulk split");
  1290. musb->bulk_split = true;
  1291. }
  1292. if (reg & MUSB_CONFIGDATA_HBRXE) {
  1293. strcat(aInfo, ", HB-ISO Rx");
  1294. musb->hb_iso_rx = true;
  1295. }
  1296. if (reg & MUSB_CONFIGDATA_HBTXE) {
  1297. strcat(aInfo, ", HB-ISO Tx");
  1298. musb->hb_iso_tx = true;
  1299. }
  1300. if (reg & MUSB_CONFIGDATA_SOFTCONE)
  1301. strcat(aInfo, ", SoftConn");
  1302. pr_debug("%s: ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo);
  1303. if (MUSB_CONTROLLER_MHDRC == musb_type) {
  1304. musb->is_multipoint = 1;
  1305. type = "M";
  1306. } else {
  1307. musb->is_multipoint = 0;
  1308. type = "";
  1309. if (IS_ENABLED(CONFIG_USB) &&
  1310. !IS_ENABLED(CONFIG_USB_OTG_BLACKLIST_HUB)) {
  1311. pr_err("%s: kernel must blacklist external hubs\n",
  1312. musb_driver_name);
  1313. }
  1314. }
  1315. /* log release info */
  1316. musb->hwvers = musb_readw(mbase, MUSB_HWVERS);
  1317. pr_debug("%s: %sHDRC RTL version %d.%d%s\n",
  1318. musb_driver_name, type, MUSB_HWVERS_MAJOR(musb->hwvers),
  1319. MUSB_HWVERS_MINOR(musb->hwvers),
  1320. (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
  1321. /* configure ep0 */
  1322. musb_configure_ep0(musb);
  1323. /* discover endpoint configuration */
  1324. musb->nr_endpoints = 1;
  1325. musb->epmask = 1;
  1326. if (musb->dyn_fifo)
  1327. status = ep_config_from_table(musb);
  1328. else
  1329. status = ep_config_from_hw(musb);
  1330. if (status < 0)
  1331. return status;
  1332. /* finish init, and print endpoint config */
  1333. for (i = 0; i < musb->nr_endpoints; i++) {
  1334. struct musb_hw_ep *hw_ep = musb->endpoints + i;
  1335. hw_ep->fifo = musb->io.fifo_offset(i) + mbase;
  1336. #if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
  1337. if (musb->ops->quirks & MUSB_IN_TUSB) {
  1338. hw_ep->fifo_async = musb->async + 0x400 +
  1339. musb->io.fifo_offset(i);
  1340. hw_ep->fifo_sync = musb->sync + 0x400 +
  1341. musb->io.fifo_offset(i);
  1342. hw_ep->fifo_sync_va =
  1343. musb->sync_va + 0x400 + musb->io.fifo_offset(i);
  1344. if (i == 0)
  1345. hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
  1346. else
  1347. hw_ep->conf = mbase + 0x400 +
  1348. (((i - 1) & 0xf) << 2);
  1349. }
  1350. #endif
  1351. hw_ep->regs = musb->io.ep_offset(i, 0) + mbase;
  1352. hw_ep->rx_reinit = 1;
  1353. hw_ep->tx_reinit = 1;
  1354. if (hw_ep->max_packet_sz_tx) {
  1355. musb_dbg(musb, "%s: hw_ep %d%s, %smax %d",
  1356. musb_driver_name, i,
  1357. hw_ep->is_shared_fifo ? "shared" : "tx",
  1358. hw_ep->tx_double_buffered
  1359. ? "doublebuffer, " : "",
  1360. hw_ep->max_packet_sz_tx);
  1361. }
  1362. if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
  1363. musb_dbg(musb, "%s: hw_ep %d%s, %smax %d",
  1364. musb_driver_name, i,
  1365. "rx",
  1366. hw_ep->rx_double_buffered
  1367. ? "doublebuffer, " : "",
  1368. hw_ep->max_packet_sz_rx);
  1369. }
  1370. if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
  1371. musb_dbg(musb, "hw_ep %d not configured", i);
  1372. }
  1373. return 0;
  1374. }
  1375. /*-------------------------------------------------------------------------*/
  1376. /*
  1377. * handle all the irqs defined by the HDRC core. for now we expect: other
  1378. * irq sources (phy, dma, etc) will be handled first, musb->int_* values
  1379. * will be assigned, and the irq will already have been acked.
  1380. *
  1381. * called in irq context with spinlock held, irqs blocked
  1382. */
  1383. irqreturn_t musb_interrupt(struct musb *musb)
  1384. {
  1385. irqreturn_t retval = IRQ_NONE;
  1386. unsigned long status;
  1387. unsigned long epnum;
  1388. u8 devctl;
  1389. if (!musb->int_usb && !musb->int_tx && !musb->int_rx)
  1390. return IRQ_NONE;
  1391. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  1392. trace_musb_isr(musb);
  1393. /**
  1394. * According to Mentor Graphics' documentation, flowchart on page 98,
  1395. * IRQ should be handled as follows:
  1396. *
  1397. * . Resume IRQ
  1398. * . Session Request IRQ
  1399. * . VBUS Error IRQ
  1400. * . Suspend IRQ
  1401. * . Connect IRQ
  1402. * . Disconnect IRQ
  1403. * . Reset/Babble IRQ
  1404. * . SOF IRQ (we're not using this one)
  1405. * . Endpoint 0 IRQ
  1406. * . TX Endpoints
  1407. * . RX Endpoints
  1408. *
  1409. * We will be following that flowchart in order to avoid any problems
  1410. * that might arise with internal Finite State Machine.
  1411. */
  1412. if (musb->int_usb)
  1413. retval |= musb_stage0_irq(musb, musb->int_usb, devctl);
  1414. if (musb->int_tx & 1) {
  1415. if (is_host_active(musb))
  1416. retval |= musb_h_ep0_irq(musb);
  1417. else
  1418. retval |= musb_g_ep0_irq(musb);
  1419. /* we have just handled endpoint 0 IRQ, clear it */
  1420. musb->int_tx &= ~BIT(0);
  1421. }
  1422. status = musb->int_tx;
  1423. for_each_set_bit(epnum, &status, 16) {
  1424. retval = IRQ_HANDLED;
  1425. if (is_host_active(musb))
  1426. musb_host_tx(musb, epnum);
  1427. else
  1428. musb_g_tx(musb, epnum);
  1429. }
  1430. status = musb->int_rx;
  1431. for_each_set_bit(epnum, &status, 16) {
  1432. retval = IRQ_HANDLED;
  1433. if (is_host_active(musb))
  1434. musb_host_rx(musb, epnum);
  1435. else
  1436. musb_g_rx(musb, epnum);
  1437. }
  1438. return retval;
  1439. }
  1440. EXPORT_SYMBOL_GPL(musb_interrupt);
  1441. #ifndef CONFIG_MUSB_PIO_ONLY
  1442. static bool use_dma = 1;
  1443. /* "modprobe ... use_dma=0" etc */
  1444. module_param(use_dma, bool, 0644);
  1445. MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
  1446. void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
  1447. {
  1448. /* called with controller lock already held */
  1449. if (!epnum) {
  1450. if (!is_cppi_enabled(musb)) {
  1451. /* endpoint 0 */
  1452. if (is_host_active(musb))
  1453. musb_h_ep0_irq(musb);
  1454. else
  1455. musb_g_ep0_irq(musb);
  1456. }
  1457. } else {
  1458. /* endpoints 1..15 */
  1459. if (transmit) {
  1460. if (is_host_active(musb))
  1461. musb_host_tx(musb, epnum);
  1462. else
  1463. musb_g_tx(musb, epnum);
  1464. } else {
  1465. /* receive */
  1466. if (is_host_active(musb))
  1467. musb_host_rx(musb, epnum);
  1468. else
  1469. musb_g_rx(musb, epnum);
  1470. }
  1471. }
  1472. }
  1473. EXPORT_SYMBOL_GPL(musb_dma_completion);
  1474. #else
  1475. #define use_dma 0
  1476. #endif
  1477. static int (*musb_phy_callback)(enum musb_vbus_id_status status);
  1478. /*
  1479. * musb_mailbox - optional phy notifier function
  1480. * @status phy state change
  1481. *
  1482. * Optionally gets called from the USB PHY. Note that the USB PHY must be
  1483. * disabled at the point the phy_callback is registered or unregistered.
  1484. */
  1485. int musb_mailbox(enum musb_vbus_id_status status)
  1486. {
  1487. if (musb_phy_callback)
  1488. return musb_phy_callback(status);
  1489. return -ENODEV;
  1490. };
  1491. EXPORT_SYMBOL_GPL(musb_mailbox);
  1492. /*-------------------------------------------------------------------------*/
  1493. static ssize_t
  1494. mode_show(struct device *dev, struct device_attribute *attr, char *buf)
  1495. {
  1496. struct musb *musb = dev_to_musb(dev);
  1497. unsigned long flags;
  1498. int ret;
  1499. spin_lock_irqsave(&musb->lock, flags);
  1500. ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state));
  1501. spin_unlock_irqrestore(&musb->lock, flags);
  1502. return ret;
  1503. }
  1504. static ssize_t
  1505. mode_store(struct device *dev, struct device_attribute *attr,
  1506. const char *buf, size_t n)
  1507. {
  1508. struct musb *musb = dev_to_musb(dev);
  1509. unsigned long flags;
  1510. int status;
  1511. spin_lock_irqsave(&musb->lock, flags);
  1512. if (sysfs_streq(buf, "host"))
  1513. status = musb_platform_set_mode(musb, MUSB_HOST);
  1514. else if (sysfs_streq(buf, "peripheral"))
  1515. status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
  1516. else if (sysfs_streq(buf, "otg"))
  1517. status = musb_platform_set_mode(musb, MUSB_OTG);
  1518. else
  1519. status = -EINVAL;
  1520. spin_unlock_irqrestore(&musb->lock, flags);
  1521. return (status == 0) ? n : status;
  1522. }
  1523. static DEVICE_ATTR_RW(mode);
  1524. static ssize_t
  1525. vbus_store(struct device *dev, struct device_attribute *attr,
  1526. const char *buf, size_t n)
  1527. {
  1528. struct musb *musb = dev_to_musb(dev);
  1529. unsigned long flags;
  1530. unsigned long val;
  1531. if (sscanf(buf, "%lu", &val) < 1) {
  1532. dev_err(dev, "Invalid VBUS timeout ms value\n");
  1533. return -EINVAL;
  1534. }
  1535. spin_lock_irqsave(&musb->lock, flags);
  1536. /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
  1537. musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
  1538. if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)
  1539. musb->is_active = 0;
  1540. musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
  1541. spin_unlock_irqrestore(&musb->lock, flags);
  1542. return n;
  1543. }
  1544. static ssize_t
  1545. vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
  1546. {
  1547. struct musb *musb = dev_to_musb(dev);
  1548. unsigned long flags;
  1549. unsigned long val;
  1550. int vbus;
  1551. u8 devctl;
  1552. pm_runtime_get_sync(dev);
  1553. spin_lock_irqsave(&musb->lock, flags);
  1554. val = musb->a_wait_bcon;
  1555. vbus = musb_platform_get_vbus_status(musb);
  1556. if (vbus < 0) {
  1557. /* Use default MUSB method by means of DEVCTL register */
  1558. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  1559. if ((devctl & MUSB_DEVCTL_VBUS)
  1560. == (3 << MUSB_DEVCTL_VBUS_SHIFT))
  1561. vbus = 1;
  1562. else
  1563. vbus = 0;
  1564. }
  1565. spin_unlock_irqrestore(&musb->lock, flags);
  1566. pm_runtime_put_sync(dev);
  1567. return sprintf(buf, "Vbus %s, timeout %lu msec\n",
  1568. vbus ? "on" : "off", val);
  1569. }
  1570. static DEVICE_ATTR_RW(vbus);
  1571. /* Gadget drivers can't know that a host is connected so they might want
  1572. * to start SRP, but users can. This allows userspace to trigger SRP.
  1573. */
  1574. static ssize_t srp_store(struct device *dev, struct device_attribute *attr,
  1575. const char *buf, size_t n)
  1576. {
  1577. struct musb *musb = dev_to_musb(dev);
  1578. unsigned short srp;
  1579. if (sscanf(buf, "%hu", &srp) != 1
  1580. || (srp != 1)) {
  1581. dev_err(dev, "SRP: Value must be 1\n");
  1582. return -EINVAL;
  1583. }
  1584. if (srp == 1)
  1585. musb_g_wakeup(musb);
  1586. return n;
  1587. }
  1588. static DEVICE_ATTR_WO(srp);
  1589. static struct attribute *musb_attrs[] = {
  1590. &dev_attr_mode.attr,
  1591. &dev_attr_vbus.attr,
  1592. &dev_attr_srp.attr,
  1593. NULL
  1594. };
  1595. ATTRIBUTE_GROUPS(musb);
  1596. #define MUSB_QUIRK_B_INVALID_VBUS_91 (MUSB_DEVCTL_BDEVICE | \
  1597. (2 << MUSB_DEVCTL_VBUS_SHIFT) | \
  1598. MUSB_DEVCTL_SESSION)
  1599. #define MUSB_QUIRK_B_DISCONNECT_99 (MUSB_DEVCTL_BDEVICE | \
  1600. (3 << MUSB_DEVCTL_VBUS_SHIFT) | \
  1601. MUSB_DEVCTL_SESSION)
  1602. #define MUSB_QUIRK_A_DISCONNECT_19 ((3 << MUSB_DEVCTL_VBUS_SHIFT) | \
  1603. MUSB_DEVCTL_SESSION)
  1604. /*
  1605. * Check the musb devctl session bit to determine if we want to
  1606. * allow PM runtime for the device. In general, we want to keep things
  1607. * active when the session bit is set except after host disconnect.
  1608. *
  1609. * Only called from musb_irq_work. If this ever needs to get called
  1610. * elsewhere, proper locking must be implemented for musb->session.
  1611. */
  1612. static void musb_pm_runtime_check_session(struct musb *musb)
  1613. {
  1614. u8 devctl, s;
  1615. int error;
  1616. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  1617. /* Handle session status quirks first */
  1618. s = MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV |
  1619. MUSB_DEVCTL_HR;
  1620. switch (devctl & ~s) {
  1621. case MUSB_QUIRK_B_DISCONNECT_99:
  1622. if (musb->quirk_retries && !musb->flush_irq_work) {
  1623. musb_dbg(musb, "Poll devctl in case of suspend after disconnect\n");
  1624. schedule_delayed_work(&musb->irq_work,
  1625. msecs_to_jiffies(1000));
  1626. musb->quirk_retries--;
  1627. }
  1628. break;
  1629. case MUSB_QUIRK_B_INVALID_VBUS_91:
  1630. if (musb->quirk_retries && !musb->flush_irq_work) {
  1631. musb_dbg(musb,
  1632. "Poll devctl on invalid vbus, assume no session");
  1633. schedule_delayed_work(&musb->irq_work,
  1634. msecs_to_jiffies(1000));
  1635. musb->quirk_retries--;
  1636. return;
  1637. }
  1638. /* fall through */
  1639. case MUSB_QUIRK_A_DISCONNECT_19:
  1640. if (musb->quirk_retries && !musb->flush_irq_work) {
  1641. musb_dbg(musb,
  1642. "Poll devctl on possible host mode disconnect");
  1643. schedule_delayed_work(&musb->irq_work,
  1644. msecs_to_jiffies(1000));
  1645. musb->quirk_retries--;
  1646. return;
  1647. }
  1648. if (!musb->session)
  1649. break;
  1650. musb_dbg(musb, "Allow PM on possible host mode disconnect");
  1651. pm_runtime_mark_last_busy(musb->controller);
  1652. pm_runtime_put_autosuspend(musb->controller);
  1653. musb->session = false;
  1654. return;
  1655. default:
  1656. break;
  1657. }
  1658. /* No need to do anything if session has not changed */
  1659. s = devctl & MUSB_DEVCTL_SESSION;
  1660. if (s == musb->session)
  1661. return;
  1662. /* Block PM or allow PM? */
  1663. if (s) {
  1664. musb_dbg(musb, "Block PM on active session: %02x", devctl);
  1665. error = pm_runtime_get_sync(musb->controller);
  1666. if (error < 0)
  1667. dev_err(musb->controller, "Could not enable: %i\n",
  1668. error);
  1669. musb->quirk_retries = 3;
  1670. } else {
  1671. musb_dbg(musb, "Allow PM with no session: %02x", devctl);
  1672. pm_runtime_mark_last_busy(musb->controller);
  1673. pm_runtime_put_autosuspend(musb->controller);
  1674. }
  1675. musb->session = s;
  1676. }
  1677. /* Only used to provide driver mode change events */
  1678. static void musb_irq_work(struct work_struct *data)
  1679. {
  1680. struct musb *musb = container_of(data, struct musb, irq_work.work);
  1681. int error;
  1682. error = pm_runtime_resume_and_get(musb->controller);
  1683. if (error < 0) {
  1684. dev_err(musb->controller, "Could not enable: %i\n", error);
  1685. return;
  1686. }
  1687. musb_pm_runtime_check_session(musb);
  1688. if (musb->xceiv->otg->state != musb->xceiv_old_state) {
  1689. musb->xceiv_old_state = musb->xceiv->otg->state;
  1690. sysfs_notify(&musb->controller->kobj, NULL, "mode");
  1691. }
  1692. pm_runtime_mark_last_busy(musb->controller);
  1693. pm_runtime_put_autosuspend(musb->controller);
  1694. }
  1695. static void musb_recover_from_babble(struct musb *musb)
  1696. {
  1697. int ret;
  1698. u8 devctl;
  1699. musb_disable_interrupts(musb);
  1700. /*
  1701. * wait at least 320 cycles of 60MHz clock. That's 5.3us, we will give
  1702. * it some slack and wait for 10us.
  1703. */
  1704. udelay(10);
  1705. ret = musb_platform_recover(musb);
  1706. if (ret) {
  1707. musb_enable_interrupts(musb);
  1708. return;
  1709. }
  1710. /* drop session bit */
  1711. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  1712. devctl &= ~MUSB_DEVCTL_SESSION;
  1713. musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  1714. /* tell usbcore about it */
  1715. musb_root_disconnect(musb);
  1716. /*
  1717. * When a babble condition occurs, the musb controller
  1718. * removes the session bit and the endpoint config is lost.
  1719. */
  1720. if (musb->dyn_fifo)
  1721. ret = ep_config_from_table(musb);
  1722. else
  1723. ret = ep_config_from_hw(musb);
  1724. /* restart session */
  1725. if (ret == 0)
  1726. musb_start(musb);
  1727. }
  1728. /* --------------------------------------------------------------------------
  1729. * Init support
  1730. */
  1731. static struct musb *allocate_instance(struct device *dev,
  1732. const struct musb_hdrc_config *config, void __iomem *mbase)
  1733. {
  1734. struct musb *musb;
  1735. struct musb_hw_ep *ep;
  1736. int epnum;
  1737. int ret;
  1738. musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
  1739. if (!musb)
  1740. return NULL;
  1741. INIT_LIST_HEAD(&musb->control);
  1742. INIT_LIST_HEAD(&musb->in_bulk);
  1743. INIT_LIST_HEAD(&musb->out_bulk);
  1744. INIT_LIST_HEAD(&musb->pending_list);
  1745. musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
  1746. musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
  1747. musb->mregs = mbase;
  1748. musb->ctrl_base = mbase;
  1749. musb->nIrq = -ENODEV;
  1750. musb->config = config;
  1751. BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
  1752. for (epnum = 0, ep = musb->endpoints;
  1753. epnum < musb->config->num_eps;
  1754. epnum++, ep++) {
  1755. ep->musb = musb;
  1756. ep->epnum = epnum;
  1757. }
  1758. musb->controller = dev;
  1759. ret = musb_host_alloc(musb);
  1760. if (ret < 0)
  1761. goto err_free;
  1762. dev_set_drvdata(dev, musb);
  1763. return musb;
  1764. err_free:
  1765. return NULL;
  1766. }
  1767. static void musb_free(struct musb *musb)
  1768. {
  1769. /* this has multiple entry modes. it handles fault cleanup after
  1770. * probe(), where things may be partially set up, as well as rmmod
  1771. * cleanup after everything's been de-activated.
  1772. */
  1773. if (musb->nIrq >= 0) {
  1774. if (musb->irq_wake)
  1775. disable_irq_wake(musb->nIrq);
  1776. free_irq(musb->nIrq, musb);
  1777. }
  1778. musb_host_free(musb);
  1779. }
  1780. struct musb_pending_work {
  1781. int (*callback)(struct musb *musb, void *data);
  1782. void *data;
  1783. struct list_head node;
  1784. };
  1785. #ifdef CONFIG_PM
  1786. /*
  1787. * Called from musb_runtime_resume(), musb_resume(), and
  1788. * musb_queue_resume_work(). Callers must take musb->lock.
  1789. */
  1790. static int musb_run_resume_work(struct musb *musb)
  1791. {
  1792. struct musb_pending_work *w, *_w;
  1793. unsigned long flags;
  1794. int error = 0;
  1795. spin_lock_irqsave(&musb->list_lock, flags);
  1796. list_for_each_entry_safe(w, _w, &musb->pending_list, node) {
  1797. if (w->callback) {
  1798. error = w->callback(musb, w->data);
  1799. if (error < 0) {
  1800. dev_err(musb->controller,
  1801. "resume callback %p failed: %i\n",
  1802. w->callback, error);
  1803. }
  1804. }
  1805. list_del(&w->node);
  1806. devm_kfree(musb->controller, w);
  1807. }
  1808. spin_unlock_irqrestore(&musb->list_lock, flags);
  1809. return error;
  1810. }
  1811. #endif
  1812. /*
  1813. * Called to run work if device is active or else queue the work to happen
  1814. * on resume. Caller must take musb->lock and must hold an RPM reference.
  1815. *
  1816. * Note that we cowardly refuse queuing work after musb PM runtime
  1817. * resume is done calling musb_run_resume_work() and return -EINPROGRESS
  1818. * instead.
  1819. */
  1820. int musb_queue_resume_work(struct musb *musb,
  1821. int (*callback)(struct musb *musb, void *data),
  1822. void *data)
  1823. {
  1824. struct musb_pending_work *w;
  1825. unsigned long flags;
  1826. bool is_suspended;
  1827. int error;
  1828. if (WARN_ON(!callback))
  1829. return -EINVAL;
  1830. spin_lock_irqsave(&musb->list_lock, flags);
  1831. is_suspended = musb->is_runtime_suspended;
  1832. if (is_suspended) {
  1833. w = devm_kzalloc(musb->controller, sizeof(*w), GFP_ATOMIC);
  1834. if (!w) {
  1835. error = -ENOMEM;
  1836. goto out_unlock;
  1837. }
  1838. w->callback = callback;
  1839. w->data = data;
  1840. list_add_tail(&w->node, &musb->pending_list);
  1841. error = 0;
  1842. }
  1843. out_unlock:
  1844. spin_unlock_irqrestore(&musb->list_lock, flags);
  1845. if (!is_suspended)
  1846. error = callback(musb, data);
  1847. return error;
  1848. }
  1849. EXPORT_SYMBOL_GPL(musb_queue_resume_work);
  1850. static void musb_deassert_reset(struct work_struct *work)
  1851. {
  1852. struct musb *musb;
  1853. unsigned long flags;
  1854. musb = container_of(work, struct musb, deassert_reset_work.work);
  1855. spin_lock_irqsave(&musb->lock, flags);
  1856. if (musb->port1_status & USB_PORT_STAT_RESET)
  1857. musb_port_reset(musb, false);
  1858. spin_unlock_irqrestore(&musb->lock, flags);
  1859. }
  1860. /*
  1861. * Perform generic per-controller initialization.
  1862. *
  1863. * @dev: the controller (already clocked, etc)
  1864. * @nIrq: IRQ number
  1865. * @ctrl: virtual address of controller registers,
  1866. * not yet corrected for platform-specific offsets
  1867. */
  1868. static int
  1869. musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
  1870. {
  1871. int status;
  1872. struct musb *musb;
  1873. struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
  1874. /* The driver might handle more features than the board; OK.
  1875. * Fail when the board needs a feature that's not enabled.
  1876. */
  1877. if (!plat) {
  1878. dev_err(dev, "no platform_data?\n");
  1879. status = -ENODEV;
  1880. goto fail0;
  1881. }
  1882. /* allocate */
  1883. musb = allocate_instance(dev, plat->config, ctrl);
  1884. if (!musb) {
  1885. status = -ENOMEM;
  1886. goto fail0;
  1887. }
  1888. spin_lock_init(&musb->lock);
  1889. spin_lock_init(&musb->list_lock);
  1890. musb->board_set_power = plat->set_power;
  1891. musb->min_power = plat->min_power;
  1892. musb->ops = plat->platform_ops;
  1893. musb->port_mode = plat->mode;
  1894. /*
  1895. * Initialize the default IO functions. At least omap2430 needs
  1896. * these early. We initialize the platform specific IO functions
  1897. * later on.
  1898. */
  1899. musb_readb = musb_default_readb;
  1900. musb_writeb = musb_default_writeb;
  1901. musb_readw = musb_default_readw;
  1902. musb_writew = musb_default_writew;
  1903. /* The musb_platform_init() call:
  1904. * - adjusts musb->mregs
  1905. * - sets the musb->isr
  1906. * - may initialize an integrated transceiver
  1907. * - initializes musb->xceiv, usually by otg_get_phy()
  1908. * - stops powering VBUS
  1909. *
  1910. * There are various transceiver configurations.
  1911. * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
  1912. * external/discrete ones in various flavors (twl4030 family,
  1913. * isp1504, non-OTG, etc) mostly hooking up through ULPI.
  1914. */
  1915. status = musb_platform_init(musb);
  1916. if (status < 0)
  1917. goto fail1;
  1918. if (!musb->isr) {
  1919. status = -ENODEV;
  1920. goto fail2;
  1921. }
  1922. /* Most devices use indexed offset or flat offset */
  1923. if (musb->ops->quirks & MUSB_INDEXED_EP) {
  1924. musb->io.ep_offset = musb_indexed_ep_offset;
  1925. musb->io.ep_select = musb_indexed_ep_select;
  1926. } else {
  1927. musb->io.ep_offset = musb_flat_ep_offset;
  1928. musb->io.ep_select = musb_flat_ep_select;
  1929. }
  1930. if (musb->ops->quirks & MUSB_G_NO_SKB_RESERVE)
  1931. musb->g.quirk_avoids_skb_reserve = 1;
  1932. /* At least tusb6010 has its own offsets */
  1933. if (musb->ops->ep_offset)
  1934. musb->io.ep_offset = musb->ops->ep_offset;
  1935. if (musb->ops->ep_select)
  1936. musb->io.ep_select = musb->ops->ep_select;
  1937. if (musb->ops->fifo_mode)
  1938. fifo_mode = musb->ops->fifo_mode;
  1939. else
  1940. fifo_mode = 4;
  1941. if (musb->ops->fifo_offset)
  1942. musb->io.fifo_offset = musb->ops->fifo_offset;
  1943. else
  1944. musb->io.fifo_offset = musb_default_fifo_offset;
  1945. if (musb->ops->busctl_offset)
  1946. musb->io.busctl_offset = musb->ops->busctl_offset;
  1947. else
  1948. musb->io.busctl_offset = musb_default_busctl_offset;
  1949. if (musb->ops->readb)
  1950. musb_readb = musb->ops->readb;
  1951. if (musb->ops->writeb)
  1952. musb_writeb = musb->ops->writeb;
  1953. if (musb->ops->readw)
  1954. musb_readw = musb->ops->readw;
  1955. if (musb->ops->writew)
  1956. musb_writew = musb->ops->writew;
  1957. #ifndef CONFIG_MUSB_PIO_ONLY
  1958. if (!musb->ops->dma_init || !musb->ops->dma_exit) {
  1959. dev_err(dev, "DMA controller not set\n");
  1960. status = -ENODEV;
  1961. goto fail2;
  1962. }
  1963. musb_dma_controller_create = musb->ops->dma_init;
  1964. musb_dma_controller_destroy = musb->ops->dma_exit;
  1965. #endif
  1966. if (musb->ops->read_fifo)
  1967. musb->io.read_fifo = musb->ops->read_fifo;
  1968. else
  1969. musb->io.read_fifo = musb_default_read_fifo;
  1970. if (musb->ops->write_fifo)
  1971. musb->io.write_fifo = musb->ops->write_fifo;
  1972. else
  1973. musb->io.write_fifo = musb_default_write_fifo;
  1974. if (!musb->xceiv->io_ops) {
  1975. musb->xceiv->io_dev = musb->controller;
  1976. musb->xceiv->io_priv = musb->mregs;
  1977. musb->xceiv->io_ops = &musb_ulpi_access;
  1978. }
  1979. if (musb->ops->phy_callback)
  1980. musb_phy_callback = musb->ops->phy_callback;
  1981. /*
  1982. * We need musb_read/write functions initialized for PM.
  1983. * Note that at least 2430 glue needs autosuspend delay
  1984. * somewhere above 300 ms for the hardware to idle properly
  1985. * after disconnecting the cable in host mode. Let's use
  1986. * 500 ms for some margin.
  1987. */
  1988. pm_runtime_use_autosuspend(musb->controller);
  1989. pm_runtime_set_autosuspend_delay(musb->controller, 500);
  1990. pm_runtime_enable(musb->controller);
  1991. pm_runtime_get_sync(musb->controller);
  1992. status = usb_phy_init(musb->xceiv);
  1993. if (status < 0)
  1994. goto err_usb_phy_init;
  1995. if (use_dma && dev->dma_mask) {
  1996. musb->dma_controller =
  1997. musb_dma_controller_create(musb, musb->mregs);
  1998. if (IS_ERR(musb->dma_controller)) {
  1999. status = PTR_ERR(musb->dma_controller);
  2000. goto fail2_5;
  2001. }
  2002. }
  2003. /* be sure interrupts are disabled before connecting ISR */
  2004. musb_platform_disable(musb);
  2005. musb_disable_interrupts(musb);
  2006. musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
  2007. /* MUSB_POWER_SOFTCONN might be already set, JZ4740 does this. */
  2008. musb_writeb(musb->mregs, MUSB_POWER, 0);
  2009. /* Init IRQ workqueue before request_irq */
  2010. INIT_DELAYED_WORK(&musb->irq_work, musb_irq_work);
  2011. INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
  2012. INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
  2013. /* setup musb parts of the core (especially endpoints) */
  2014. status = musb_core_init(plat->config->multipoint
  2015. ? MUSB_CONTROLLER_MHDRC
  2016. : MUSB_CONTROLLER_HDRC, musb);
  2017. if (status < 0)
  2018. goto fail3;
  2019. timer_setup(&musb->otg_timer, musb_otg_timer_func, 0);
  2020. /* attach to the IRQ */
  2021. if (request_irq(nIrq, musb->isr, IRQF_SHARED, dev_name(dev), musb)) {
  2022. dev_err(dev, "request_irq %d failed!\n", nIrq);
  2023. status = -ENODEV;
  2024. goto fail3;
  2025. }
  2026. musb->nIrq = nIrq;
  2027. /* FIXME this handles wakeup irqs wrong */
  2028. if (enable_irq_wake(nIrq) == 0) {
  2029. musb->irq_wake = 1;
  2030. device_init_wakeup(dev, 1);
  2031. } else {
  2032. musb->irq_wake = 0;
  2033. }
  2034. /* program PHY to use external vBus if required */
  2035. if (plat->extvbus) {
  2036. u8 busctl = musb_readb(musb->mregs, MUSB_ULPI_BUSCONTROL);
  2037. busctl |= MUSB_ULPI_USE_EXTVBUS;
  2038. musb_writeb(musb->mregs, MUSB_ULPI_BUSCONTROL, busctl);
  2039. }
  2040. MUSB_DEV_MODE(musb);
  2041. musb->xceiv->otg->state = OTG_STATE_B_IDLE;
  2042. switch (musb->port_mode) {
  2043. case MUSB_HOST:
  2044. status = musb_host_setup(musb, plat->power);
  2045. if (status < 0)
  2046. goto fail3;
  2047. status = musb_platform_set_mode(musb, MUSB_HOST);
  2048. break;
  2049. case MUSB_PERIPHERAL:
  2050. status = musb_gadget_setup(musb);
  2051. if (status < 0)
  2052. goto fail3;
  2053. status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
  2054. break;
  2055. case MUSB_OTG:
  2056. status = musb_host_setup(musb, plat->power);
  2057. if (status < 0)
  2058. goto fail3;
  2059. status = musb_gadget_setup(musb);
  2060. if (status) {
  2061. musb_host_cleanup(musb);
  2062. goto fail3;
  2063. }
  2064. status = musb_platform_set_mode(musb, MUSB_OTG);
  2065. break;
  2066. default:
  2067. dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
  2068. break;
  2069. }
  2070. if (status < 0)
  2071. goto fail3;
  2072. musb_init_debugfs(musb);
  2073. musb->is_initialized = 1;
  2074. pm_runtime_mark_last_busy(musb->controller);
  2075. pm_runtime_put_autosuspend(musb->controller);
  2076. return 0;
  2077. fail3:
  2078. cancel_delayed_work_sync(&musb->irq_work);
  2079. cancel_delayed_work_sync(&musb->finish_resume_work);
  2080. cancel_delayed_work_sync(&musb->deassert_reset_work);
  2081. if (musb->dma_controller)
  2082. musb_dma_controller_destroy(musb->dma_controller);
  2083. fail2_5:
  2084. usb_phy_shutdown(musb->xceiv);
  2085. err_usb_phy_init:
  2086. pm_runtime_dont_use_autosuspend(musb->controller);
  2087. pm_runtime_put_sync(musb->controller);
  2088. pm_runtime_disable(musb->controller);
  2089. fail2:
  2090. if (musb->irq_wake)
  2091. device_init_wakeup(dev, 0);
  2092. musb_platform_exit(musb);
  2093. fail1:
  2094. if (status != -EPROBE_DEFER)
  2095. dev_err(musb->controller,
  2096. "%s failed with status %d\n", __func__, status);
  2097. musb_free(musb);
  2098. fail0:
  2099. return status;
  2100. }
  2101. /*-------------------------------------------------------------------------*/
  2102. /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
  2103. * bridge to a platform device; this driver then suffices.
  2104. */
  2105. static int musb_probe(struct platform_device *pdev)
  2106. {
  2107. struct device *dev = &pdev->dev;
  2108. int irq = platform_get_irq_byname(pdev, "mc");
  2109. struct resource *iomem;
  2110. void __iomem *base;
  2111. if (irq <= 0)
  2112. return -ENODEV;
  2113. iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  2114. base = devm_ioremap_resource(dev, iomem);
  2115. if (IS_ERR(base))
  2116. return PTR_ERR(base);
  2117. return musb_init_controller(dev, irq, base);
  2118. }
  2119. static int musb_remove(struct platform_device *pdev)
  2120. {
  2121. struct device *dev = &pdev->dev;
  2122. struct musb *musb = dev_to_musb(dev);
  2123. unsigned long flags;
  2124. /* this gets called on rmmod.
  2125. * - Host mode: host may still be active
  2126. * - Peripheral mode: peripheral is deactivated (or never-activated)
  2127. * - OTG mode: both roles are deactivated (or never-activated)
  2128. */
  2129. musb_exit_debugfs(musb);
  2130. cancel_delayed_work_sync(&musb->irq_work);
  2131. cancel_delayed_work_sync(&musb->finish_resume_work);
  2132. cancel_delayed_work_sync(&musb->deassert_reset_work);
  2133. pm_runtime_get_sync(musb->controller);
  2134. musb_host_cleanup(musb);
  2135. musb_gadget_cleanup(musb);
  2136. musb_platform_disable(musb);
  2137. spin_lock_irqsave(&musb->lock, flags);
  2138. musb_disable_interrupts(musb);
  2139. musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
  2140. spin_unlock_irqrestore(&musb->lock, flags);
  2141. musb_platform_exit(musb);
  2142. pm_runtime_dont_use_autosuspend(musb->controller);
  2143. pm_runtime_put_sync(musb->controller);
  2144. pm_runtime_disable(musb->controller);
  2145. musb_phy_callback = NULL;
  2146. if (musb->dma_controller)
  2147. musb_dma_controller_destroy(musb->dma_controller);
  2148. usb_phy_shutdown(musb->xceiv);
  2149. musb_free(musb);
  2150. device_init_wakeup(dev, 0);
  2151. return 0;
  2152. }
  2153. #ifdef CONFIG_PM
  2154. static void musb_save_context(struct musb *musb)
  2155. {
  2156. int i;
  2157. void __iomem *musb_base = musb->mregs;
  2158. void __iomem *epio;
  2159. musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
  2160. musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
  2161. musb->context.busctl = musb_readb(musb_base, MUSB_ULPI_BUSCONTROL);
  2162. musb->context.power = musb_readb(musb_base, MUSB_POWER);
  2163. musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
  2164. musb->context.index = musb_readb(musb_base, MUSB_INDEX);
  2165. musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
  2166. for (i = 0; i < musb->config->num_eps; ++i) {
  2167. struct musb_hw_ep *hw_ep;
  2168. hw_ep = &musb->endpoints[i];
  2169. if (!hw_ep)
  2170. continue;
  2171. epio = hw_ep->regs;
  2172. if (!epio)
  2173. continue;
  2174. musb_writeb(musb_base, MUSB_INDEX, i);
  2175. musb->context.index_regs[i].txmaxp =
  2176. musb_readw(epio, MUSB_TXMAXP);
  2177. musb->context.index_regs[i].txcsr =
  2178. musb_readw(epio, MUSB_TXCSR);
  2179. musb->context.index_regs[i].rxmaxp =
  2180. musb_readw(epio, MUSB_RXMAXP);
  2181. musb->context.index_regs[i].rxcsr =
  2182. musb_readw(epio, MUSB_RXCSR);
  2183. if (musb->dyn_fifo) {
  2184. musb->context.index_regs[i].txfifoadd =
  2185. musb_readw(musb_base, MUSB_TXFIFOADD);
  2186. musb->context.index_regs[i].rxfifoadd =
  2187. musb_readw(musb_base, MUSB_RXFIFOADD);
  2188. musb->context.index_regs[i].txfifosz =
  2189. musb_readb(musb_base, MUSB_TXFIFOSZ);
  2190. musb->context.index_regs[i].rxfifosz =
  2191. musb_readb(musb_base, MUSB_RXFIFOSZ);
  2192. }
  2193. musb->context.index_regs[i].txtype =
  2194. musb_readb(epio, MUSB_TXTYPE);
  2195. musb->context.index_regs[i].txinterval =
  2196. musb_readb(epio, MUSB_TXINTERVAL);
  2197. musb->context.index_regs[i].rxtype =
  2198. musb_readb(epio, MUSB_RXTYPE);
  2199. musb->context.index_regs[i].rxinterval =
  2200. musb_readb(epio, MUSB_RXINTERVAL);
  2201. musb->context.index_regs[i].txfunaddr =
  2202. musb_read_txfunaddr(musb, i);
  2203. musb->context.index_regs[i].txhubaddr =
  2204. musb_read_txhubaddr(musb, i);
  2205. musb->context.index_regs[i].txhubport =
  2206. musb_read_txhubport(musb, i);
  2207. musb->context.index_regs[i].rxfunaddr =
  2208. musb_read_rxfunaddr(musb, i);
  2209. musb->context.index_regs[i].rxhubaddr =
  2210. musb_read_rxhubaddr(musb, i);
  2211. musb->context.index_regs[i].rxhubport =
  2212. musb_read_rxhubport(musb, i);
  2213. }
  2214. }
  2215. static void musb_restore_context(struct musb *musb)
  2216. {
  2217. int i;
  2218. void __iomem *musb_base = musb->mregs;
  2219. void __iomem *epio;
  2220. u8 power;
  2221. musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
  2222. musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
  2223. musb_writeb(musb_base, MUSB_ULPI_BUSCONTROL, musb->context.busctl);
  2224. /* Don't affect SUSPENDM/RESUME bits in POWER reg */
  2225. power = musb_readb(musb_base, MUSB_POWER);
  2226. power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
  2227. musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
  2228. power |= musb->context.power;
  2229. musb_writeb(musb_base, MUSB_POWER, power);
  2230. musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
  2231. musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
  2232. musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
  2233. if (musb->context.devctl & MUSB_DEVCTL_SESSION)
  2234. musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
  2235. for (i = 0; i < musb->config->num_eps; ++i) {
  2236. struct musb_hw_ep *hw_ep;
  2237. hw_ep = &musb->endpoints[i];
  2238. if (!hw_ep)
  2239. continue;
  2240. epio = hw_ep->regs;
  2241. if (!epio)
  2242. continue;
  2243. musb_writeb(musb_base, MUSB_INDEX, i);
  2244. musb_writew(epio, MUSB_TXMAXP,
  2245. musb->context.index_regs[i].txmaxp);
  2246. musb_writew(epio, MUSB_TXCSR,
  2247. musb->context.index_regs[i].txcsr);
  2248. musb_writew(epio, MUSB_RXMAXP,
  2249. musb->context.index_regs[i].rxmaxp);
  2250. musb_writew(epio, MUSB_RXCSR,
  2251. musb->context.index_regs[i].rxcsr);
  2252. if (musb->dyn_fifo) {
  2253. musb_writeb(musb_base, MUSB_TXFIFOSZ,
  2254. musb->context.index_regs[i].txfifosz);
  2255. musb_writeb(musb_base, MUSB_RXFIFOSZ,
  2256. musb->context.index_regs[i].rxfifosz);
  2257. musb_writew(musb_base, MUSB_TXFIFOADD,
  2258. musb->context.index_regs[i].txfifoadd);
  2259. musb_writew(musb_base, MUSB_RXFIFOADD,
  2260. musb->context.index_regs[i].rxfifoadd);
  2261. }
  2262. musb_writeb(epio, MUSB_TXTYPE,
  2263. musb->context.index_regs[i].txtype);
  2264. musb_writeb(epio, MUSB_TXINTERVAL,
  2265. musb->context.index_regs[i].txinterval);
  2266. musb_writeb(epio, MUSB_RXTYPE,
  2267. musb->context.index_regs[i].rxtype);
  2268. musb_writeb(epio, MUSB_RXINTERVAL,
  2269. musb->context.index_regs[i].rxinterval);
  2270. musb_write_txfunaddr(musb, i,
  2271. musb->context.index_regs[i].txfunaddr);
  2272. musb_write_txhubaddr(musb, i,
  2273. musb->context.index_regs[i].txhubaddr);
  2274. musb_write_txhubport(musb, i,
  2275. musb->context.index_regs[i].txhubport);
  2276. musb_write_rxfunaddr(musb, i,
  2277. musb->context.index_regs[i].rxfunaddr);
  2278. musb_write_rxhubaddr(musb, i,
  2279. musb->context.index_regs[i].rxhubaddr);
  2280. musb_write_rxhubport(musb, i,
  2281. musb->context.index_regs[i].rxhubport);
  2282. }
  2283. musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
  2284. }
  2285. static int musb_suspend(struct device *dev)
  2286. {
  2287. struct musb *musb = dev_to_musb(dev);
  2288. unsigned long flags;
  2289. int ret;
  2290. ret = pm_runtime_get_sync(dev);
  2291. if (ret < 0) {
  2292. pm_runtime_put_noidle(dev);
  2293. return ret;
  2294. }
  2295. musb_platform_disable(musb);
  2296. musb_disable_interrupts(musb);
  2297. musb->flush_irq_work = true;
  2298. while (flush_delayed_work(&musb->irq_work))
  2299. ;
  2300. musb->flush_irq_work = false;
  2301. if (!(musb->ops->quirks & MUSB_PRESERVE_SESSION))
  2302. musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
  2303. WARN_ON(!list_empty(&musb->pending_list));
  2304. spin_lock_irqsave(&musb->lock, flags);
  2305. if (is_peripheral_active(musb)) {
  2306. /* FIXME force disconnect unless we know USB will wake
  2307. * the system up quickly enough to respond ...
  2308. */
  2309. } else if (is_host_active(musb)) {
  2310. /* we know all the children are suspended; sometimes
  2311. * they will even be wakeup-enabled.
  2312. */
  2313. }
  2314. musb_save_context(musb);
  2315. spin_unlock_irqrestore(&musb->lock, flags);
  2316. return 0;
  2317. }
  2318. static int musb_resume(struct device *dev)
  2319. {
  2320. struct musb *musb = dev_to_musb(dev);
  2321. unsigned long flags;
  2322. int error;
  2323. u8 devctl;
  2324. u8 mask;
  2325. /*
  2326. * For static cmos like DaVinci, register values were preserved
  2327. * unless for some reason the whole soc powered down or the USB
  2328. * module got reset through the PSC (vs just being disabled).
  2329. *
  2330. * For the DSPS glue layer though, a full register restore has to
  2331. * be done. As it shouldn't harm other platforms, we do it
  2332. * unconditionally.
  2333. */
  2334. musb_restore_context(musb);
  2335. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  2336. mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV;
  2337. if ((devctl & mask) != (musb->context.devctl & mask))
  2338. musb->port1_status = 0;
  2339. musb_enable_interrupts(musb);
  2340. musb_platform_enable(musb);
  2341. /* session might be disabled in suspend */
  2342. if (musb->port_mode == MUSB_HOST &&
  2343. !(musb->ops->quirks & MUSB_PRESERVE_SESSION)) {
  2344. devctl |= MUSB_DEVCTL_SESSION;
  2345. musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  2346. }
  2347. spin_lock_irqsave(&musb->lock, flags);
  2348. error = musb_run_resume_work(musb);
  2349. if (error)
  2350. dev_err(musb->controller, "resume work failed with %i\n",
  2351. error);
  2352. spin_unlock_irqrestore(&musb->lock, flags);
  2353. pm_runtime_mark_last_busy(dev);
  2354. pm_runtime_put_autosuspend(dev);
  2355. return 0;
  2356. }
  2357. static int musb_runtime_suspend(struct device *dev)
  2358. {
  2359. struct musb *musb = dev_to_musb(dev);
  2360. musb_save_context(musb);
  2361. musb->is_runtime_suspended = 1;
  2362. return 0;
  2363. }
  2364. static int musb_runtime_resume(struct device *dev)
  2365. {
  2366. struct musb *musb = dev_to_musb(dev);
  2367. unsigned long flags;
  2368. int error;
  2369. /*
  2370. * When pm_runtime_get_sync called for the first time in driver
  2371. * init, some of the structure is still not initialized which is
  2372. * used in restore function. But clock needs to be
  2373. * enabled before any register access, so
  2374. * pm_runtime_get_sync has to be called.
  2375. * Also context restore without save does not make
  2376. * any sense
  2377. */
  2378. if (!musb->is_initialized)
  2379. return 0;
  2380. musb_restore_context(musb);
  2381. spin_lock_irqsave(&musb->lock, flags);
  2382. error = musb_run_resume_work(musb);
  2383. if (error)
  2384. dev_err(musb->controller, "resume work failed with %i\n",
  2385. error);
  2386. musb->is_runtime_suspended = 0;
  2387. spin_unlock_irqrestore(&musb->lock, flags);
  2388. return 0;
  2389. }
  2390. static const struct dev_pm_ops musb_dev_pm_ops = {
  2391. .suspend = musb_suspend,
  2392. .resume = musb_resume,
  2393. .runtime_suspend = musb_runtime_suspend,
  2394. .runtime_resume = musb_runtime_resume,
  2395. };
  2396. #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
  2397. #else
  2398. #define MUSB_DEV_PM_OPS NULL
  2399. #endif
  2400. static struct platform_driver musb_driver = {
  2401. .driver = {
  2402. .name = (char *)musb_driver_name,
  2403. .bus = &platform_bus_type,
  2404. .pm = MUSB_DEV_PM_OPS,
  2405. .dev_groups = musb_groups,
  2406. },
  2407. .probe = musb_probe,
  2408. .remove = musb_remove,
  2409. };
  2410. module_platform_driver(musb_driver);