xhci-ext-caps.h 4.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * xHCI host controller driver
  4. *
  5. * Copyright (C) 2008 Intel Corp.
  6. *
  7. * Author: Sarah Sharp
  8. * Some code borrowed from the Linux EHCI driver.
  9. */
  10. /* HC should halt within 16 ms, but use 32 ms as some hosts take longer */
  11. #define XHCI_MAX_HALT_USEC (32 * 1000)
  12. /* HC not running - set to 1 when run/stop bit is cleared. */
  13. #define XHCI_STS_HALT (1<<0)
  14. /* HCCPARAMS offset from PCI base address */
  15. #define XHCI_HCC_PARAMS_OFFSET 0x10
  16. /* HCCPARAMS contains the first extended capability pointer */
  17. #define XHCI_HCC_EXT_CAPS(p) (((p)>>16)&0xffff)
  18. /* Command and Status registers offset from the Operational Registers address */
  19. #define XHCI_CMD_OFFSET 0x00
  20. #define XHCI_STS_OFFSET 0x04
  21. #define XHCI_MAX_EXT_CAPS 50
  22. /* Capability Register */
  23. /* bits 7:0 - how long is the Capabilities register */
  24. #define XHCI_HC_LENGTH(p) (((p)>>00)&0x00ff)
  25. /* Extended capability register fields */
  26. #define XHCI_EXT_CAPS_ID(p) (((p)>>0)&0xff)
  27. #define XHCI_EXT_CAPS_NEXT(p) (((p)>>8)&0xff)
  28. #define XHCI_EXT_CAPS_VAL(p) ((p)>>16)
  29. /* Extended capability IDs - ID 0 reserved */
  30. #define XHCI_EXT_CAPS_LEGACY 1
  31. #define XHCI_EXT_CAPS_PROTOCOL 2
  32. #define XHCI_EXT_CAPS_PM 3
  33. #define XHCI_EXT_CAPS_VIRT 4
  34. #define XHCI_EXT_CAPS_ROUTE 5
  35. /* IDs 6-9 reserved */
  36. #define XHCI_EXT_CAPS_DEBUG 10
  37. /* Vendor caps */
  38. #define XHCI_EXT_CAPS_VENDOR_INTEL 192
  39. /* USB Legacy Support Capability - section 7.1.1 */
  40. #define XHCI_HC_BIOS_OWNED (1 << 16)
  41. #define XHCI_HC_OS_OWNED (1 << 24)
  42. /* USB Legacy Support Capability - section 7.1.1 */
  43. /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */
  44. #define XHCI_LEGACY_SUPPORT_OFFSET (0x00)
  45. /* USB Legacy Support Control and Status Register - section 7.1.2 */
  46. /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */
  47. #define XHCI_LEGACY_CONTROL_OFFSET (0x04)
  48. /* bits 1:3, 5:12, and 17:19 need to be preserved; bits 21:28 should be zero */
  49. #define XHCI_LEGACY_DISABLE_SMI ((0x7 << 1) + (0xff << 5) + (0x7 << 17))
  50. #define XHCI_LEGACY_SMI_EVENTS (0x7 << 29)
  51. /* USB 2.0 xHCI 0.96 L1C capability - section 7.2.2.1.3.2 */
  52. #define XHCI_L1C (1 << 16)
  53. /* USB 2.0 xHCI 1.0 hardware LMP capability - section 7.2.2.1.3.2 */
  54. #define XHCI_HLC (1 << 19)
  55. #define XHCI_BLC (1 << 20)
  56. /* command register values to disable interrupts and halt the HC */
  57. /* start/stop HC execution - do not write unless HC is halted*/
  58. #define XHCI_CMD_RUN (1 << 0)
  59. /* Event Interrupt Enable - get irq when EINT bit is set in USBSTS register */
  60. #define XHCI_CMD_EIE (1 << 2)
  61. /* Host System Error Interrupt Enable - get irq when HSEIE bit set in USBSTS */
  62. #define XHCI_CMD_HSEIE (1 << 3)
  63. /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
  64. #define XHCI_CMD_EWE (1 << 10)
  65. #define XHCI_IRQS (XHCI_CMD_EIE | XHCI_CMD_HSEIE | XHCI_CMD_EWE)
  66. /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
  67. #define XHCI_STS_CNR (1 << 11)
  68. #include <linux/io.h>
  69. /**
  70. * Find the offset of the extended capabilities with capability ID id.
  71. *
  72. * @base PCI MMIO registers base address.
  73. * @start address at which to start looking, (0 or HCC_PARAMS to start at
  74. * beginning of list)
  75. * @id Extended capability ID to search for, or 0 for the next
  76. * capability
  77. *
  78. * Returns the offset of the next matching extended capability structure.
  79. * Some capabilities can occur several times, e.g., the XHCI_EXT_CAPS_PROTOCOL,
  80. * and this provides a way to find them all.
  81. */
  82. static inline int xhci_find_next_ext_cap(void __iomem *base, u32 start, int id)
  83. {
  84. u32 val;
  85. u32 next;
  86. u32 offset;
  87. offset = start;
  88. if (!start || start == XHCI_HCC_PARAMS_OFFSET) {
  89. val = readl(base + XHCI_HCC_PARAMS_OFFSET);
  90. if (val == ~0)
  91. return 0;
  92. offset = XHCI_HCC_EXT_CAPS(val) << 2;
  93. if (!offset)
  94. return 0;
  95. }
  96. do {
  97. val = readl(base + offset);
  98. if (val == ~0)
  99. return 0;
  100. if (offset != start && (id == 0 || XHCI_EXT_CAPS_ID(val) == id))
  101. return offset;
  102. next = XHCI_EXT_CAPS_NEXT(val);
  103. offset += next << 2;
  104. } while (next);
  105. return 0;
  106. }