ucc_uart.c 41 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Freescale QUICC Engine UART device driver
  4. *
  5. * Author: Timur Tabi <timur@freescale.com>
  6. *
  7. * Copyright 2007 Freescale Semiconductor, Inc.
  8. *
  9. * This driver adds support for UART devices via Freescale's QUICC Engine
  10. * found on some Freescale SOCs.
  11. *
  12. * If Soft-UART support is needed but not already present, then this driver
  13. * will request and upload the "Soft-UART" microcode upon probe. The
  14. * filename of the microcode should be fsl_qe_ucode_uart_X_YZ.bin, where "X"
  15. * is the name of the SOC (e.g. 8323), and YZ is the revision of the SOC,
  16. * (e.g. "11" for 1.1).
  17. */
  18. #include <linux/module.h>
  19. #include <linux/serial.h>
  20. #include <linux/serial_core.h>
  21. #include <linux/slab.h>
  22. #include <linux/tty.h>
  23. #include <linux/tty_flip.h>
  24. #include <linux/io.h>
  25. #include <linux/of_address.h>
  26. #include <linux/of_irq.h>
  27. #include <linux/of_platform.h>
  28. #include <linux/dma-mapping.h>
  29. #include <linux/fs_uart_pd.h>
  30. #include <soc/fsl/qe/ucc_slow.h>
  31. #include <linux/firmware.h>
  32. #include <asm/reg.h>
  33. /*
  34. * The GUMR flag for Soft UART. This would normally be defined in qe.h,
  35. * but Soft-UART is a hack and we want to keep everything related to it in
  36. * this file.
  37. */
  38. #define UCC_SLOW_GUMR_H_SUART 0x00004000 /* Soft-UART */
  39. /*
  40. * soft_uart is 1 if we need to use Soft-UART mode
  41. */
  42. static int soft_uart;
  43. /*
  44. * firmware_loaded is 1 if the firmware has been loaded, 0 otherwise.
  45. */
  46. static int firmware_loaded;
  47. /* Enable this macro to configure all serial ports in internal loopback
  48. mode */
  49. /* #define LOOPBACK */
  50. /* The major and minor device numbers are defined in
  51. * http://www.lanana.org/docs/device-list/devices-2.6+.txt. For the QE
  52. * UART, we have major number 204 and minor numbers 46 - 49, which are the
  53. * same as for the CPM2. This decision was made because no Freescale part
  54. * has both a CPM and a QE.
  55. */
  56. #define SERIAL_QE_MAJOR 204
  57. #define SERIAL_QE_MINOR 46
  58. /* Since we only have minor numbers 46 - 49, there is a hard limit of 4 ports */
  59. #define UCC_MAX_UART 4
  60. /* The number of buffer descriptors for receiving characters. */
  61. #define RX_NUM_FIFO 4
  62. /* The number of buffer descriptors for transmitting characters. */
  63. #define TX_NUM_FIFO 4
  64. /* The maximum size of the character buffer for a single RX BD. */
  65. #define RX_BUF_SIZE 32
  66. /* The maximum size of the character buffer for a single TX BD. */
  67. #define TX_BUF_SIZE 32
  68. /*
  69. * The number of jiffies to wait after receiving a close command before the
  70. * device is actually closed. This allows the last few characters to be
  71. * sent over the wire.
  72. */
  73. #define UCC_WAIT_CLOSING 100
  74. struct ucc_uart_pram {
  75. struct ucc_slow_pram common;
  76. u8 res1[8]; /* reserved */
  77. __be16 maxidl; /* Maximum idle chars */
  78. __be16 idlc; /* temp idle counter */
  79. __be16 brkcr; /* Break count register */
  80. __be16 parec; /* receive parity error counter */
  81. __be16 frmec; /* receive framing error counter */
  82. __be16 nosec; /* receive noise counter */
  83. __be16 brkec; /* receive break condition counter */
  84. __be16 brkln; /* last received break length */
  85. __be16 uaddr[2]; /* UART address character 1 & 2 */
  86. __be16 rtemp; /* Temp storage */
  87. __be16 toseq; /* Transmit out of sequence char */
  88. __be16 cchars[8]; /* control characters 1-8 */
  89. __be16 rccm; /* receive control character mask */
  90. __be16 rccr; /* receive control character register */
  91. __be16 rlbc; /* receive last break character */
  92. __be16 res2; /* reserved */
  93. __be32 res3; /* reserved, should be cleared */
  94. u8 res4; /* reserved, should be cleared */
  95. u8 res5[3]; /* reserved, should be cleared */
  96. __be32 res6; /* reserved, should be cleared */
  97. __be32 res7; /* reserved, should be cleared */
  98. __be32 res8; /* reserved, should be cleared */
  99. __be32 res9; /* reserved, should be cleared */
  100. __be32 res10; /* reserved, should be cleared */
  101. __be32 res11; /* reserved, should be cleared */
  102. __be32 res12; /* reserved, should be cleared */
  103. __be32 res13; /* reserved, should be cleared */
  104. /* The rest is for Soft-UART only */
  105. __be16 supsmr; /* 0x90, Shadow UPSMR */
  106. __be16 res92; /* 0x92, reserved, initialize to 0 */
  107. __be32 rx_state; /* 0x94, RX state, initialize to 0 */
  108. __be32 rx_cnt; /* 0x98, RX count, initialize to 0 */
  109. u8 rx_length; /* 0x9C, Char length, set to 1+CL+PEN+1+SL */
  110. u8 rx_bitmark; /* 0x9D, reserved, initialize to 0 */
  111. u8 rx_temp_dlst_qe; /* 0x9E, reserved, initialize to 0 */
  112. u8 res14[0xBC - 0x9F]; /* reserved */
  113. __be32 dump_ptr; /* 0xBC, Dump pointer */
  114. __be32 rx_frame_rem; /* 0xC0, reserved, initialize to 0 */
  115. u8 rx_frame_rem_size; /* 0xC4, reserved, initialize to 0 */
  116. u8 tx_mode; /* 0xC5, mode, 0=AHDLC, 1=UART */
  117. __be16 tx_state; /* 0xC6, TX state */
  118. u8 res15[0xD0 - 0xC8]; /* reserved */
  119. __be32 resD0; /* 0xD0, reserved, initialize to 0 */
  120. u8 resD4; /* 0xD4, reserved, initialize to 0 */
  121. __be16 resD5; /* 0xD5, reserved, initialize to 0 */
  122. } __attribute__ ((packed));
  123. /* SUPSMR definitions, for Soft-UART only */
  124. #define UCC_UART_SUPSMR_SL 0x8000
  125. #define UCC_UART_SUPSMR_RPM_MASK 0x6000
  126. #define UCC_UART_SUPSMR_RPM_ODD 0x0000
  127. #define UCC_UART_SUPSMR_RPM_LOW 0x2000
  128. #define UCC_UART_SUPSMR_RPM_EVEN 0x4000
  129. #define UCC_UART_SUPSMR_RPM_HIGH 0x6000
  130. #define UCC_UART_SUPSMR_PEN 0x1000
  131. #define UCC_UART_SUPSMR_TPM_MASK 0x0C00
  132. #define UCC_UART_SUPSMR_TPM_ODD 0x0000
  133. #define UCC_UART_SUPSMR_TPM_LOW 0x0400
  134. #define UCC_UART_SUPSMR_TPM_EVEN 0x0800
  135. #define UCC_UART_SUPSMR_TPM_HIGH 0x0C00
  136. #define UCC_UART_SUPSMR_FRZ 0x0100
  137. #define UCC_UART_SUPSMR_UM_MASK 0x00c0
  138. #define UCC_UART_SUPSMR_UM_NORMAL 0x0000
  139. #define UCC_UART_SUPSMR_UM_MAN_MULTI 0x0040
  140. #define UCC_UART_SUPSMR_UM_AUTO_MULTI 0x00c0
  141. #define UCC_UART_SUPSMR_CL_MASK 0x0030
  142. #define UCC_UART_SUPSMR_CL_8 0x0030
  143. #define UCC_UART_SUPSMR_CL_7 0x0020
  144. #define UCC_UART_SUPSMR_CL_6 0x0010
  145. #define UCC_UART_SUPSMR_CL_5 0x0000
  146. #define UCC_UART_TX_STATE_AHDLC 0x00
  147. #define UCC_UART_TX_STATE_UART 0x01
  148. #define UCC_UART_TX_STATE_X1 0x00
  149. #define UCC_UART_TX_STATE_X16 0x80
  150. #define UCC_UART_PRAM_ALIGNMENT 0x100
  151. #define UCC_UART_SIZE_OF_BD UCC_SLOW_SIZE_OF_BD
  152. #define NUM_CONTROL_CHARS 8
  153. /* Private per-port data structure */
  154. struct uart_qe_port {
  155. struct uart_port port;
  156. struct ucc_slow __iomem *uccp;
  157. struct ucc_uart_pram __iomem *uccup;
  158. struct ucc_slow_info us_info;
  159. struct ucc_slow_private *us_private;
  160. struct device_node *np;
  161. unsigned int ucc_num; /* First ucc is 0, not 1 */
  162. u16 rx_nrfifos;
  163. u16 rx_fifosize;
  164. u16 tx_nrfifos;
  165. u16 tx_fifosize;
  166. int wait_closing;
  167. u32 flags;
  168. struct qe_bd *rx_bd_base;
  169. struct qe_bd *rx_cur;
  170. struct qe_bd *tx_bd_base;
  171. struct qe_bd *tx_cur;
  172. unsigned char *tx_buf;
  173. unsigned char *rx_buf;
  174. void *bd_virt; /* virtual address of the BD buffers */
  175. dma_addr_t bd_dma_addr; /* bus address of the BD buffers */
  176. unsigned int bd_size; /* size of BD buffer space */
  177. };
  178. static struct uart_driver ucc_uart_driver = {
  179. .owner = THIS_MODULE,
  180. .driver_name = "ucc_uart",
  181. .dev_name = "ttyQE",
  182. .major = SERIAL_QE_MAJOR,
  183. .minor = SERIAL_QE_MINOR,
  184. .nr = UCC_MAX_UART,
  185. };
  186. /*
  187. * Virtual to physical address translation.
  188. *
  189. * Given the virtual address for a character buffer, this function returns
  190. * the physical (DMA) equivalent.
  191. */
  192. static inline dma_addr_t cpu2qe_addr(void *addr, struct uart_qe_port *qe_port)
  193. {
  194. if (likely((addr >= qe_port->bd_virt)) &&
  195. (addr < (qe_port->bd_virt + qe_port->bd_size)))
  196. return qe_port->bd_dma_addr + (addr - qe_port->bd_virt);
  197. /* something nasty happened */
  198. printk(KERN_ERR "%s: addr=%p\n", __func__, addr);
  199. BUG();
  200. return 0;
  201. }
  202. /*
  203. * Physical to virtual address translation.
  204. *
  205. * Given the physical (DMA) address for a character buffer, this function
  206. * returns the virtual equivalent.
  207. */
  208. static inline void *qe2cpu_addr(dma_addr_t addr, struct uart_qe_port *qe_port)
  209. {
  210. /* sanity check */
  211. if (likely((addr >= qe_port->bd_dma_addr) &&
  212. (addr < (qe_port->bd_dma_addr + qe_port->bd_size))))
  213. return qe_port->bd_virt + (addr - qe_port->bd_dma_addr);
  214. /* something nasty happened */
  215. printk(KERN_ERR "%s: addr=%llx\n", __func__, (u64)addr);
  216. BUG();
  217. return NULL;
  218. }
  219. /*
  220. * Return 1 if the QE is done transmitting all buffers for this port
  221. *
  222. * This function scans each BD in sequence. If we find a BD that is not
  223. * ready (READY=1), then we return 0 indicating that the QE is still sending
  224. * data. If we reach the last BD (WRAP=1), then we know we've scanned
  225. * the entire list, and all BDs are done.
  226. */
  227. static unsigned int qe_uart_tx_empty(struct uart_port *port)
  228. {
  229. struct uart_qe_port *qe_port =
  230. container_of(port, struct uart_qe_port, port);
  231. struct qe_bd *bdp = qe_port->tx_bd_base;
  232. while (1) {
  233. if (in_be16(&bdp->status) & BD_SC_READY)
  234. /* This BD is not done, so return "not done" */
  235. return 0;
  236. if (in_be16(&bdp->status) & BD_SC_WRAP)
  237. /*
  238. * This BD is done and it's the last one, so return
  239. * "done"
  240. */
  241. return 1;
  242. bdp++;
  243. }
  244. }
  245. /*
  246. * Set the modem control lines
  247. *
  248. * Although the QE can control the modem control lines (e.g. CTS), we
  249. * don't need that support. This function must exist, however, otherwise
  250. * the kernel will panic.
  251. */
  252. void qe_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
  253. {
  254. }
  255. /*
  256. * Get the current modem control line status
  257. *
  258. * Although the QE can control the modem control lines (e.g. CTS), this
  259. * driver currently doesn't support that, so we always return Carrier
  260. * Detect, Data Set Ready, and Clear To Send.
  261. */
  262. static unsigned int qe_uart_get_mctrl(struct uart_port *port)
  263. {
  264. return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
  265. }
  266. /*
  267. * Disable the transmit interrupt.
  268. *
  269. * Although this function is called "stop_tx", it does not actually stop
  270. * transmission of data. Instead, it tells the QE to not generate an
  271. * interrupt when the UCC is finished sending characters.
  272. */
  273. static void qe_uart_stop_tx(struct uart_port *port)
  274. {
  275. struct uart_qe_port *qe_port =
  276. container_of(port, struct uart_qe_port, port);
  277. clrbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
  278. }
  279. /*
  280. * Transmit as many characters to the HW as possible.
  281. *
  282. * This function will attempt to stuff of all the characters from the
  283. * kernel's transmit buffer into TX BDs.
  284. *
  285. * A return value of non-zero indicates that it successfully stuffed all
  286. * characters from the kernel buffer.
  287. *
  288. * A return value of zero indicates that there are still characters in the
  289. * kernel's buffer that have not been transmitted, but there are no more BDs
  290. * available. This function should be called again after a BD has been made
  291. * available.
  292. */
  293. static int qe_uart_tx_pump(struct uart_qe_port *qe_port)
  294. {
  295. struct qe_bd *bdp;
  296. unsigned char *p;
  297. unsigned int count;
  298. struct uart_port *port = &qe_port->port;
  299. struct circ_buf *xmit = &port->state->xmit;
  300. bdp = qe_port->rx_cur;
  301. /* Handle xon/xoff */
  302. if (port->x_char) {
  303. /* Pick next descriptor and fill from buffer */
  304. bdp = qe_port->tx_cur;
  305. p = qe2cpu_addr(bdp->buf, qe_port);
  306. *p++ = port->x_char;
  307. out_be16(&bdp->length, 1);
  308. setbits16(&bdp->status, BD_SC_READY);
  309. /* Get next BD. */
  310. if (in_be16(&bdp->status) & BD_SC_WRAP)
  311. bdp = qe_port->tx_bd_base;
  312. else
  313. bdp++;
  314. qe_port->tx_cur = bdp;
  315. port->icount.tx++;
  316. port->x_char = 0;
  317. return 1;
  318. }
  319. if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
  320. qe_uart_stop_tx(port);
  321. return 0;
  322. }
  323. /* Pick next descriptor and fill from buffer */
  324. bdp = qe_port->tx_cur;
  325. while (!(in_be16(&bdp->status) & BD_SC_READY) &&
  326. (xmit->tail != xmit->head)) {
  327. count = 0;
  328. p = qe2cpu_addr(bdp->buf, qe_port);
  329. while (count < qe_port->tx_fifosize) {
  330. *p++ = xmit->buf[xmit->tail];
  331. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  332. port->icount.tx++;
  333. count++;
  334. if (xmit->head == xmit->tail)
  335. break;
  336. }
  337. out_be16(&bdp->length, count);
  338. setbits16(&bdp->status, BD_SC_READY);
  339. /* Get next BD. */
  340. if (in_be16(&bdp->status) & BD_SC_WRAP)
  341. bdp = qe_port->tx_bd_base;
  342. else
  343. bdp++;
  344. }
  345. qe_port->tx_cur = bdp;
  346. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  347. uart_write_wakeup(port);
  348. if (uart_circ_empty(xmit)) {
  349. /* The kernel buffer is empty, so turn off TX interrupts. We
  350. don't need to be told when the QE is finished transmitting
  351. the data. */
  352. qe_uart_stop_tx(port);
  353. return 0;
  354. }
  355. return 1;
  356. }
  357. /*
  358. * Start transmitting data
  359. *
  360. * This function will start transmitting any available data, if the port
  361. * isn't already transmitting data.
  362. */
  363. static void qe_uart_start_tx(struct uart_port *port)
  364. {
  365. struct uart_qe_port *qe_port =
  366. container_of(port, struct uart_qe_port, port);
  367. /* If we currently are transmitting, then just return */
  368. if (in_be16(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX)
  369. return;
  370. /* Otherwise, pump the port and start transmission */
  371. if (qe_uart_tx_pump(qe_port))
  372. setbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
  373. }
  374. /*
  375. * Stop transmitting data
  376. */
  377. static void qe_uart_stop_rx(struct uart_port *port)
  378. {
  379. struct uart_qe_port *qe_port =
  380. container_of(port, struct uart_qe_port, port);
  381. clrbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
  382. }
  383. /* Start or stop sending break signal
  384. *
  385. * This function controls the sending of a break signal. If break_state=1,
  386. * then we start sending a break signal. If break_state=0, then we stop
  387. * sending the break signal.
  388. */
  389. static void qe_uart_break_ctl(struct uart_port *port, int break_state)
  390. {
  391. struct uart_qe_port *qe_port =
  392. container_of(port, struct uart_qe_port, port);
  393. if (break_state)
  394. ucc_slow_stop_tx(qe_port->us_private);
  395. else
  396. ucc_slow_restart_tx(qe_port->us_private);
  397. }
  398. /* ISR helper function for receiving character.
  399. *
  400. * This function is called by the ISR to handling receiving characters
  401. */
  402. static void qe_uart_int_rx(struct uart_qe_port *qe_port)
  403. {
  404. int i;
  405. unsigned char ch, *cp;
  406. struct uart_port *port = &qe_port->port;
  407. struct tty_port *tport = &port->state->port;
  408. struct qe_bd *bdp;
  409. u16 status;
  410. unsigned int flg;
  411. /* Just loop through the closed BDs and copy the characters into
  412. * the buffer.
  413. */
  414. bdp = qe_port->rx_cur;
  415. while (1) {
  416. status = in_be16(&bdp->status);
  417. /* If this one is empty, then we assume we've read them all */
  418. if (status & BD_SC_EMPTY)
  419. break;
  420. /* get number of characters, and check space in RX buffer */
  421. i = in_be16(&bdp->length);
  422. /* If we don't have enough room in RX buffer for the entire BD,
  423. * then we try later, which will be the next RX interrupt.
  424. */
  425. if (tty_buffer_request_room(tport, i) < i) {
  426. dev_dbg(port->dev, "ucc-uart: no room in RX buffer\n");
  427. return;
  428. }
  429. /* get pointer */
  430. cp = qe2cpu_addr(bdp->buf, qe_port);
  431. /* loop through the buffer */
  432. while (i-- > 0) {
  433. ch = *cp++;
  434. port->icount.rx++;
  435. flg = TTY_NORMAL;
  436. if (!i && status &
  437. (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV))
  438. goto handle_error;
  439. if (uart_handle_sysrq_char(port, ch))
  440. continue;
  441. error_return:
  442. tty_insert_flip_char(tport, ch, flg);
  443. }
  444. /* This BD is ready to be used again. Clear status. get next */
  445. clrsetbits_be16(&bdp->status, BD_SC_BR | BD_SC_FR | BD_SC_PR |
  446. BD_SC_OV | BD_SC_ID, BD_SC_EMPTY);
  447. if (in_be16(&bdp->status) & BD_SC_WRAP)
  448. bdp = qe_port->rx_bd_base;
  449. else
  450. bdp++;
  451. }
  452. /* Write back buffer pointer */
  453. qe_port->rx_cur = bdp;
  454. /* Activate BH processing */
  455. tty_flip_buffer_push(tport);
  456. return;
  457. /* Error processing */
  458. handle_error:
  459. /* Statistics */
  460. if (status & BD_SC_BR)
  461. port->icount.brk++;
  462. if (status & BD_SC_PR)
  463. port->icount.parity++;
  464. if (status & BD_SC_FR)
  465. port->icount.frame++;
  466. if (status & BD_SC_OV)
  467. port->icount.overrun++;
  468. /* Mask out ignored conditions */
  469. status &= port->read_status_mask;
  470. /* Handle the remaining ones */
  471. if (status & BD_SC_BR)
  472. flg = TTY_BREAK;
  473. else if (status & BD_SC_PR)
  474. flg = TTY_PARITY;
  475. else if (status & BD_SC_FR)
  476. flg = TTY_FRAME;
  477. /* Overrun does not affect the current character ! */
  478. if (status & BD_SC_OV)
  479. tty_insert_flip_char(tport, 0, TTY_OVERRUN);
  480. #ifdef SUPPORT_SYSRQ
  481. port->sysrq = 0;
  482. #endif
  483. goto error_return;
  484. }
  485. /* Interrupt handler
  486. *
  487. * This interrupt handler is called after a BD is processed.
  488. */
  489. static irqreturn_t qe_uart_int(int irq, void *data)
  490. {
  491. struct uart_qe_port *qe_port = (struct uart_qe_port *) data;
  492. struct ucc_slow __iomem *uccp = qe_port->uccp;
  493. u16 events;
  494. /* Clear the interrupts */
  495. events = in_be16(&uccp->ucce);
  496. out_be16(&uccp->ucce, events);
  497. if (events & UCC_UART_UCCE_BRKE)
  498. uart_handle_break(&qe_port->port);
  499. if (events & UCC_UART_UCCE_RX)
  500. qe_uart_int_rx(qe_port);
  501. if (events & UCC_UART_UCCE_TX)
  502. qe_uart_tx_pump(qe_port);
  503. return events ? IRQ_HANDLED : IRQ_NONE;
  504. }
  505. /* Initialize buffer descriptors
  506. *
  507. * This function initializes all of the RX and TX buffer descriptors.
  508. */
  509. static void qe_uart_initbd(struct uart_qe_port *qe_port)
  510. {
  511. int i;
  512. void *bd_virt;
  513. struct qe_bd *bdp;
  514. /* Set the physical address of the host memory buffers in the buffer
  515. * descriptors, and the virtual address for us to work with.
  516. */
  517. bd_virt = qe_port->bd_virt;
  518. bdp = qe_port->rx_bd_base;
  519. qe_port->rx_cur = qe_port->rx_bd_base;
  520. for (i = 0; i < (qe_port->rx_nrfifos - 1); i++) {
  521. out_be16(&bdp->status, BD_SC_EMPTY | BD_SC_INTRPT);
  522. out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
  523. out_be16(&bdp->length, 0);
  524. bd_virt += qe_port->rx_fifosize;
  525. bdp++;
  526. }
  527. /* */
  528. out_be16(&bdp->status, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT);
  529. out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
  530. out_be16(&bdp->length, 0);
  531. /* Set the physical address of the host memory
  532. * buffers in the buffer descriptors, and the
  533. * virtual address for us to work with.
  534. */
  535. bd_virt = qe_port->bd_virt +
  536. L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize);
  537. qe_port->tx_cur = qe_port->tx_bd_base;
  538. bdp = qe_port->tx_bd_base;
  539. for (i = 0; i < (qe_port->tx_nrfifos - 1); i++) {
  540. out_be16(&bdp->status, BD_SC_INTRPT);
  541. out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
  542. out_be16(&bdp->length, 0);
  543. bd_virt += qe_port->tx_fifosize;
  544. bdp++;
  545. }
  546. /* Loopback requires the preamble bit to be set on the first TX BD */
  547. #ifdef LOOPBACK
  548. setbits16(&qe_port->tx_cur->status, BD_SC_P);
  549. #endif
  550. out_be16(&bdp->status, BD_SC_WRAP | BD_SC_INTRPT);
  551. out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
  552. out_be16(&bdp->length, 0);
  553. }
  554. /*
  555. * Initialize a UCC for UART.
  556. *
  557. * This function configures a given UCC to be used as a UART device. Basic
  558. * UCC initialization is handled in qe_uart_request_port(). This function
  559. * does all the UART-specific stuff.
  560. */
  561. static void qe_uart_init_ucc(struct uart_qe_port *qe_port)
  562. {
  563. u32 cecr_subblock;
  564. struct ucc_slow __iomem *uccp = qe_port->uccp;
  565. struct ucc_uart_pram *uccup = qe_port->uccup;
  566. unsigned int i;
  567. /* First, disable TX and RX in the UCC */
  568. ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
  569. /* Program the UCC UART parameter RAM */
  570. out_8(&uccup->common.rbmr, UCC_BMR_GBL | UCC_BMR_BO_BE);
  571. out_8(&uccup->common.tbmr, UCC_BMR_GBL | UCC_BMR_BO_BE);
  572. out_be16(&uccup->common.mrblr, qe_port->rx_fifosize);
  573. out_be16(&uccup->maxidl, 0x10);
  574. out_be16(&uccup->brkcr, 1);
  575. out_be16(&uccup->parec, 0);
  576. out_be16(&uccup->frmec, 0);
  577. out_be16(&uccup->nosec, 0);
  578. out_be16(&uccup->brkec, 0);
  579. out_be16(&uccup->uaddr[0], 0);
  580. out_be16(&uccup->uaddr[1], 0);
  581. out_be16(&uccup->toseq, 0);
  582. for (i = 0; i < 8; i++)
  583. out_be16(&uccup->cchars[i], 0xC000);
  584. out_be16(&uccup->rccm, 0xc0ff);
  585. /* Configure the GUMR registers for UART */
  586. if (soft_uart) {
  587. /* Soft-UART requires a 1X multiplier for TX */
  588. clrsetbits_be32(&uccp->gumr_l,
  589. UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
  590. UCC_SLOW_GUMR_L_RDCR_MASK,
  591. UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_1 |
  592. UCC_SLOW_GUMR_L_RDCR_16);
  593. clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW,
  594. UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX);
  595. } else {
  596. clrsetbits_be32(&uccp->gumr_l,
  597. UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
  598. UCC_SLOW_GUMR_L_RDCR_MASK,
  599. UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_16 |
  600. UCC_SLOW_GUMR_L_RDCR_16);
  601. clrsetbits_be32(&uccp->gumr_h,
  602. UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX,
  603. UCC_SLOW_GUMR_H_RFW);
  604. }
  605. #ifdef LOOPBACK
  606. clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
  607. UCC_SLOW_GUMR_L_DIAG_LOOP);
  608. clrsetbits_be32(&uccp->gumr_h,
  609. UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_RSYN,
  610. UCC_SLOW_GUMR_H_CDS);
  611. #endif
  612. /* Disable rx interrupts and clear all pending events. */
  613. out_be16(&uccp->uccm, 0);
  614. out_be16(&uccp->ucce, 0xffff);
  615. out_be16(&uccp->udsr, 0x7e7e);
  616. /* Initialize UPSMR */
  617. out_be16(&uccp->upsmr, 0);
  618. if (soft_uart) {
  619. out_be16(&uccup->supsmr, 0x30);
  620. out_be16(&uccup->res92, 0);
  621. out_be32(&uccup->rx_state, 0);
  622. out_be32(&uccup->rx_cnt, 0);
  623. out_8(&uccup->rx_bitmark, 0);
  624. out_8(&uccup->rx_length, 10);
  625. out_be32(&uccup->dump_ptr, 0x4000);
  626. out_8(&uccup->rx_temp_dlst_qe, 0);
  627. out_be32(&uccup->rx_frame_rem, 0);
  628. out_8(&uccup->rx_frame_rem_size, 0);
  629. /* Soft-UART requires TX to be 1X */
  630. out_8(&uccup->tx_mode,
  631. UCC_UART_TX_STATE_UART | UCC_UART_TX_STATE_X1);
  632. out_be16(&uccup->tx_state, 0);
  633. out_8(&uccup->resD4, 0);
  634. out_be16(&uccup->resD5, 0);
  635. /* Set UART mode.
  636. * Enable receive and transmit.
  637. */
  638. /* From the microcode errata:
  639. * 1.GUMR_L register, set mode=0010 (QMC).
  640. * 2.Set GUMR_H[17] bit. (UART/AHDLC mode).
  641. * 3.Set GUMR_H[19:20] (Transparent mode)
  642. * 4.Clear GUMR_H[26] (RFW)
  643. * ...
  644. * 6.Receiver must use 16x over sampling
  645. */
  646. clrsetbits_be32(&uccp->gumr_l,
  647. UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
  648. UCC_SLOW_GUMR_L_RDCR_MASK,
  649. UCC_SLOW_GUMR_L_MODE_QMC | UCC_SLOW_GUMR_L_TDCR_16 |
  650. UCC_SLOW_GUMR_L_RDCR_16);
  651. clrsetbits_be32(&uccp->gumr_h,
  652. UCC_SLOW_GUMR_H_RFW | UCC_SLOW_GUMR_H_RSYN,
  653. UCC_SLOW_GUMR_H_SUART | UCC_SLOW_GUMR_H_TRX |
  654. UCC_SLOW_GUMR_H_TTX | UCC_SLOW_GUMR_H_TFL);
  655. #ifdef LOOPBACK
  656. clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
  657. UCC_SLOW_GUMR_L_DIAG_LOOP);
  658. clrbits32(&uccp->gumr_h, UCC_SLOW_GUMR_H_CTSP |
  659. UCC_SLOW_GUMR_H_CDS);
  660. #endif
  661. cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
  662. qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
  663. QE_CR_PROTOCOL_UNSPECIFIED, 0);
  664. } else {
  665. cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
  666. qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
  667. QE_CR_PROTOCOL_UART, 0);
  668. }
  669. }
  670. /*
  671. * Initialize the port.
  672. */
  673. static int qe_uart_startup(struct uart_port *port)
  674. {
  675. struct uart_qe_port *qe_port =
  676. container_of(port, struct uart_qe_port, port);
  677. int ret;
  678. /*
  679. * If we're using Soft-UART mode, then we need to make sure the
  680. * firmware has been uploaded first.
  681. */
  682. if (soft_uart && !firmware_loaded) {
  683. dev_err(port->dev, "Soft-UART firmware not uploaded\n");
  684. return -ENODEV;
  685. }
  686. qe_uart_initbd(qe_port);
  687. qe_uart_init_ucc(qe_port);
  688. /* Install interrupt handler. */
  689. ret = request_irq(port->irq, qe_uart_int, IRQF_SHARED, "ucc-uart",
  690. qe_port);
  691. if (ret) {
  692. dev_err(port->dev, "could not claim IRQ %u\n", port->irq);
  693. return ret;
  694. }
  695. /* Startup rx-int */
  696. setbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
  697. ucc_slow_enable(qe_port->us_private, COMM_DIR_RX_AND_TX);
  698. return 0;
  699. }
  700. /*
  701. * Shutdown the port.
  702. */
  703. static void qe_uart_shutdown(struct uart_port *port)
  704. {
  705. struct uart_qe_port *qe_port =
  706. container_of(port, struct uart_qe_port, port);
  707. struct ucc_slow __iomem *uccp = qe_port->uccp;
  708. unsigned int timeout = 20;
  709. /* Disable RX and TX */
  710. /* Wait for all the BDs marked sent */
  711. while (!qe_uart_tx_empty(port)) {
  712. if (!--timeout) {
  713. dev_warn(port->dev, "shutdown timeout\n");
  714. break;
  715. }
  716. set_current_state(TASK_UNINTERRUPTIBLE);
  717. schedule_timeout(2);
  718. }
  719. if (qe_port->wait_closing) {
  720. /* Wait a bit longer */
  721. set_current_state(TASK_UNINTERRUPTIBLE);
  722. schedule_timeout(qe_port->wait_closing);
  723. }
  724. /* Stop uarts */
  725. ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
  726. clrbits16(&uccp->uccm, UCC_UART_UCCE_TX | UCC_UART_UCCE_RX);
  727. /* Shut them really down and reinit buffer descriptors */
  728. ucc_slow_graceful_stop_tx(qe_port->us_private);
  729. qe_uart_initbd(qe_port);
  730. free_irq(port->irq, qe_port);
  731. }
  732. /*
  733. * Set the serial port parameters.
  734. */
  735. static void qe_uart_set_termios(struct uart_port *port,
  736. struct ktermios *termios, struct ktermios *old)
  737. {
  738. struct uart_qe_port *qe_port =
  739. container_of(port, struct uart_qe_port, port);
  740. struct ucc_slow __iomem *uccp = qe_port->uccp;
  741. unsigned int baud;
  742. unsigned long flags;
  743. u16 upsmr = in_be16(&uccp->upsmr);
  744. struct ucc_uart_pram __iomem *uccup = qe_port->uccup;
  745. u16 supsmr = in_be16(&uccup->supsmr);
  746. u8 char_length = 2; /* 1 + CL + PEN + 1 + SL */
  747. /* Character length programmed into the mode register is the
  748. * sum of: 1 start bit, number of data bits, 0 or 1 parity bit,
  749. * 1 or 2 stop bits, minus 1.
  750. * The value 'bits' counts this for us.
  751. */
  752. /* byte size */
  753. upsmr &= UCC_UART_UPSMR_CL_MASK;
  754. supsmr &= UCC_UART_SUPSMR_CL_MASK;
  755. switch (termios->c_cflag & CSIZE) {
  756. case CS5:
  757. upsmr |= UCC_UART_UPSMR_CL_5;
  758. supsmr |= UCC_UART_SUPSMR_CL_5;
  759. char_length += 5;
  760. break;
  761. case CS6:
  762. upsmr |= UCC_UART_UPSMR_CL_6;
  763. supsmr |= UCC_UART_SUPSMR_CL_6;
  764. char_length += 6;
  765. break;
  766. case CS7:
  767. upsmr |= UCC_UART_UPSMR_CL_7;
  768. supsmr |= UCC_UART_SUPSMR_CL_7;
  769. char_length += 7;
  770. break;
  771. default: /* case CS8 */
  772. upsmr |= UCC_UART_UPSMR_CL_8;
  773. supsmr |= UCC_UART_SUPSMR_CL_8;
  774. char_length += 8;
  775. break;
  776. }
  777. /* If CSTOPB is set, we want two stop bits */
  778. if (termios->c_cflag & CSTOPB) {
  779. upsmr |= UCC_UART_UPSMR_SL;
  780. supsmr |= UCC_UART_SUPSMR_SL;
  781. char_length++; /* + SL */
  782. }
  783. if (termios->c_cflag & PARENB) {
  784. upsmr |= UCC_UART_UPSMR_PEN;
  785. supsmr |= UCC_UART_SUPSMR_PEN;
  786. char_length++; /* + PEN */
  787. if (!(termios->c_cflag & PARODD)) {
  788. upsmr &= ~(UCC_UART_UPSMR_RPM_MASK |
  789. UCC_UART_UPSMR_TPM_MASK);
  790. upsmr |= UCC_UART_UPSMR_RPM_EVEN |
  791. UCC_UART_UPSMR_TPM_EVEN;
  792. supsmr &= ~(UCC_UART_SUPSMR_RPM_MASK |
  793. UCC_UART_SUPSMR_TPM_MASK);
  794. supsmr |= UCC_UART_SUPSMR_RPM_EVEN |
  795. UCC_UART_SUPSMR_TPM_EVEN;
  796. }
  797. }
  798. /*
  799. * Set up parity check flag
  800. */
  801. port->read_status_mask = BD_SC_EMPTY | BD_SC_OV;
  802. if (termios->c_iflag & INPCK)
  803. port->read_status_mask |= BD_SC_FR | BD_SC_PR;
  804. if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
  805. port->read_status_mask |= BD_SC_BR;
  806. /*
  807. * Characters to ignore
  808. */
  809. port->ignore_status_mask = 0;
  810. if (termios->c_iflag & IGNPAR)
  811. port->ignore_status_mask |= BD_SC_PR | BD_SC_FR;
  812. if (termios->c_iflag & IGNBRK) {
  813. port->ignore_status_mask |= BD_SC_BR;
  814. /*
  815. * If we're ignore parity and break indicators, ignore
  816. * overruns too. (For real raw support).
  817. */
  818. if (termios->c_iflag & IGNPAR)
  819. port->ignore_status_mask |= BD_SC_OV;
  820. }
  821. /*
  822. * !!! ignore all characters if CREAD is not set
  823. */
  824. if ((termios->c_cflag & CREAD) == 0)
  825. port->read_status_mask &= ~BD_SC_EMPTY;
  826. baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
  827. /* Do we really need a spinlock here? */
  828. spin_lock_irqsave(&port->lock, flags);
  829. /* Update the per-port timeout. */
  830. uart_update_timeout(port, termios->c_cflag, baud);
  831. out_be16(&uccp->upsmr, upsmr);
  832. if (soft_uart) {
  833. out_be16(&uccup->supsmr, supsmr);
  834. out_8(&uccup->rx_length, char_length);
  835. /* Soft-UART requires a 1X multiplier for TX */
  836. qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
  837. qe_setbrg(qe_port->us_info.tx_clock, baud, 1);
  838. } else {
  839. qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
  840. qe_setbrg(qe_port->us_info.tx_clock, baud, 16);
  841. }
  842. spin_unlock_irqrestore(&port->lock, flags);
  843. }
  844. /*
  845. * Return a pointer to a string that describes what kind of port this is.
  846. */
  847. static const char *qe_uart_type(struct uart_port *port)
  848. {
  849. return "QE";
  850. }
  851. /*
  852. * Allocate any memory and I/O resources required by the port.
  853. */
  854. static int qe_uart_request_port(struct uart_port *port)
  855. {
  856. int ret;
  857. struct uart_qe_port *qe_port =
  858. container_of(port, struct uart_qe_port, port);
  859. struct ucc_slow_info *us_info = &qe_port->us_info;
  860. struct ucc_slow_private *uccs;
  861. unsigned int rx_size, tx_size;
  862. void *bd_virt;
  863. dma_addr_t bd_dma_addr = 0;
  864. ret = ucc_slow_init(us_info, &uccs);
  865. if (ret) {
  866. dev_err(port->dev, "could not initialize UCC%u\n",
  867. qe_port->ucc_num);
  868. return ret;
  869. }
  870. qe_port->us_private = uccs;
  871. qe_port->uccp = uccs->us_regs;
  872. qe_port->uccup = (struct ucc_uart_pram *) uccs->us_pram;
  873. qe_port->rx_bd_base = uccs->rx_bd;
  874. qe_port->tx_bd_base = uccs->tx_bd;
  875. /*
  876. * Allocate the transmit and receive data buffers.
  877. */
  878. rx_size = L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize);
  879. tx_size = L1_CACHE_ALIGN(qe_port->tx_nrfifos * qe_port->tx_fifosize);
  880. bd_virt = dma_alloc_coherent(port->dev, rx_size + tx_size, &bd_dma_addr,
  881. GFP_KERNEL);
  882. if (!bd_virt) {
  883. dev_err(port->dev, "could not allocate buffer descriptors\n");
  884. return -ENOMEM;
  885. }
  886. qe_port->bd_virt = bd_virt;
  887. qe_port->bd_dma_addr = bd_dma_addr;
  888. qe_port->bd_size = rx_size + tx_size;
  889. qe_port->rx_buf = bd_virt;
  890. qe_port->tx_buf = qe_port->rx_buf + rx_size;
  891. return 0;
  892. }
  893. /*
  894. * Configure the port.
  895. *
  896. * We say we're a CPM-type port because that's mostly true. Once the device
  897. * is configured, this driver operates almost identically to the CPM serial
  898. * driver.
  899. */
  900. static void qe_uart_config_port(struct uart_port *port, int flags)
  901. {
  902. if (flags & UART_CONFIG_TYPE) {
  903. port->type = PORT_CPM;
  904. qe_uart_request_port(port);
  905. }
  906. }
  907. /*
  908. * Release any memory and I/O resources that were allocated in
  909. * qe_uart_request_port().
  910. */
  911. static void qe_uart_release_port(struct uart_port *port)
  912. {
  913. struct uart_qe_port *qe_port =
  914. container_of(port, struct uart_qe_port, port);
  915. struct ucc_slow_private *uccs = qe_port->us_private;
  916. dma_free_coherent(port->dev, qe_port->bd_size, qe_port->bd_virt,
  917. qe_port->bd_dma_addr);
  918. ucc_slow_free(uccs);
  919. }
  920. /*
  921. * Verify that the data in serial_struct is suitable for this device.
  922. */
  923. static int qe_uart_verify_port(struct uart_port *port,
  924. struct serial_struct *ser)
  925. {
  926. if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM)
  927. return -EINVAL;
  928. if (ser->irq < 0 || ser->irq >= nr_irqs)
  929. return -EINVAL;
  930. if (ser->baud_base < 9600)
  931. return -EINVAL;
  932. return 0;
  933. }
  934. /* UART operations
  935. *
  936. * Details on these functions can be found in Documentation/driver-api/serial/driver.rst
  937. */
  938. static const struct uart_ops qe_uart_pops = {
  939. .tx_empty = qe_uart_tx_empty,
  940. .set_mctrl = qe_uart_set_mctrl,
  941. .get_mctrl = qe_uart_get_mctrl,
  942. .stop_tx = qe_uart_stop_tx,
  943. .start_tx = qe_uart_start_tx,
  944. .stop_rx = qe_uart_stop_rx,
  945. .break_ctl = qe_uart_break_ctl,
  946. .startup = qe_uart_startup,
  947. .shutdown = qe_uart_shutdown,
  948. .set_termios = qe_uart_set_termios,
  949. .type = qe_uart_type,
  950. .release_port = qe_uart_release_port,
  951. .request_port = qe_uart_request_port,
  952. .config_port = qe_uart_config_port,
  953. .verify_port = qe_uart_verify_port,
  954. };
  955. /*
  956. * Obtain the SOC model number and revision level
  957. *
  958. * This function parses the device tree to obtain the SOC model. It then
  959. * reads the SVR register to the revision.
  960. *
  961. * The device tree stores the SOC model two different ways.
  962. *
  963. * The new way is:
  964. *
  965. * cpu@0 {
  966. * compatible = "PowerPC,8323";
  967. * device_type = "cpu";
  968. * ...
  969. *
  970. *
  971. * The old way is:
  972. * PowerPC,8323@0 {
  973. * device_type = "cpu";
  974. * ...
  975. *
  976. * This code first checks the new way, and then the old way.
  977. */
  978. static unsigned int soc_info(unsigned int *rev_h, unsigned int *rev_l)
  979. {
  980. struct device_node *np;
  981. const char *soc_string;
  982. unsigned int svr;
  983. unsigned int soc;
  984. /* Find the CPU node */
  985. np = of_find_node_by_type(NULL, "cpu");
  986. if (!np)
  987. return 0;
  988. /* Find the compatible property */
  989. soc_string = of_get_property(np, "compatible", NULL);
  990. if (!soc_string)
  991. /* No compatible property, so try the name. */
  992. soc_string = np->name;
  993. /* Extract the SOC number from the "PowerPC," string */
  994. if ((sscanf(soc_string, "PowerPC,%u", &soc) != 1) || !soc)
  995. return 0;
  996. /* Get the revision from the SVR */
  997. svr = mfspr(SPRN_SVR);
  998. *rev_h = (svr >> 4) & 0xf;
  999. *rev_l = svr & 0xf;
  1000. return soc;
  1001. }
  1002. /*
  1003. * requst_firmware_nowait() callback function
  1004. *
  1005. * This function is called by the kernel when a firmware is made available,
  1006. * or if it times out waiting for the firmware.
  1007. */
  1008. static void uart_firmware_cont(const struct firmware *fw, void *context)
  1009. {
  1010. struct qe_firmware *firmware;
  1011. struct device *dev = context;
  1012. int ret;
  1013. if (!fw) {
  1014. dev_err(dev, "firmware not found\n");
  1015. return;
  1016. }
  1017. firmware = (struct qe_firmware *) fw->data;
  1018. if (firmware->header.length != fw->size) {
  1019. dev_err(dev, "invalid firmware\n");
  1020. goto out;
  1021. }
  1022. ret = qe_upload_firmware(firmware);
  1023. if (ret) {
  1024. dev_err(dev, "could not load firmware\n");
  1025. goto out;
  1026. }
  1027. firmware_loaded = 1;
  1028. out:
  1029. release_firmware(fw);
  1030. }
  1031. static int ucc_uart_probe(struct platform_device *ofdev)
  1032. {
  1033. struct device_node *np = ofdev->dev.of_node;
  1034. const unsigned int *iprop; /* Integer OF properties */
  1035. const char *sprop; /* String OF properties */
  1036. struct uart_qe_port *qe_port = NULL;
  1037. struct resource res;
  1038. int ret;
  1039. /*
  1040. * Determine if we need Soft-UART mode
  1041. */
  1042. if (of_find_property(np, "soft-uart", NULL)) {
  1043. dev_dbg(&ofdev->dev, "using Soft-UART mode\n");
  1044. soft_uart = 1;
  1045. }
  1046. /*
  1047. * If we are using Soft-UART, determine if we need to upload the
  1048. * firmware, too.
  1049. */
  1050. if (soft_uart) {
  1051. struct qe_firmware_info *qe_fw_info;
  1052. qe_fw_info = qe_get_firmware_info();
  1053. /* Check if the firmware has been uploaded. */
  1054. if (qe_fw_info && strstr(qe_fw_info->id, "Soft-UART")) {
  1055. firmware_loaded = 1;
  1056. } else {
  1057. char filename[32];
  1058. unsigned int soc;
  1059. unsigned int rev_h;
  1060. unsigned int rev_l;
  1061. soc = soc_info(&rev_h, &rev_l);
  1062. if (!soc) {
  1063. dev_err(&ofdev->dev, "unknown CPU model\n");
  1064. return -ENXIO;
  1065. }
  1066. sprintf(filename, "fsl_qe_ucode_uart_%u_%u%u.bin",
  1067. soc, rev_h, rev_l);
  1068. dev_info(&ofdev->dev, "waiting for firmware %s\n",
  1069. filename);
  1070. /*
  1071. * We call request_firmware_nowait instead of
  1072. * request_firmware so that the driver can load and
  1073. * initialize the ports without holding up the rest of
  1074. * the kernel. If hotplug support is enabled in the
  1075. * kernel, then we use it.
  1076. */
  1077. ret = request_firmware_nowait(THIS_MODULE,
  1078. FW_ACTION_HOTPLUG, filename, &ofdev->dev,
  1079. GFP_KERNEL, &ofdev->dev, uart_firmware_cont);
  1080. if (ret) {
  1081. dev_err(&ofdev->dev,
  1082. "could not load firmware %s\n",
  1083. filename);
  1084. return ret;
  1085. }
  1086. }
  1087. }
  1088. qe_port = kzalloc(sizeof(struct uart_qe_port), GFP_KERNEL);
  1089. if (!qe_port) {
  1090. dev_err(&ofdev->dev, "can't allocate QE port structure\n");
  1091. return -ENOMEM;
  1092. }
  1093. /* Search for IRQ and mapbase */
  1094. ret = of_address_to_resource(np, 0, &res);
  1095. if (ret) {
  1096. dev_err(&ofdev->dev, "missing 'reg' property in device tree\n");
  1097. goto out_free;
  1098. }
  1099. if (!res.start) {
  1100. dev_err(&ofdev->dev, "invalid 'reg' property in device tree\n");
  1101. ret = -EINVAL;
  1102. goto out_free;
  1103. }
  1104. qe_port->port.mapbase = res.start;
  1105. /* Get the UCC number (device ID) */
  1106. /* UCCs are numbered 1-7 */
  1107. iprop = of_get_property(np, "cell-index", NULL);
  1108. if (!iprop) {
  1109. iprop = of_get_property(np, "device-id", NULL);
  1110. if (!iprop) {
  1111. dev_err(&ofdev->dev, "UCC is unspecified in "
  1112. "device tree\n");
  1113. ret = -EINVAL;
  1114. goto out_free;
  1115. }
  1116. }
  1117. if ((*iprop < 1) || (*iprop > UCC_MAX_NUM)) {
  1118. dev_err(&ofdev->dev, "no support for UCC%u\n", *iprop);
  1119. ret = -ENODEV;
  1120. goto out_free;
  1121. }
  1122. qe_port->ucc_num = *iprop - 1;
  1123. /*
  1124. * In the future, we should not require the BRG to be specified in the
  1125. * device tree. If no clock-source is specified, then just pick a BRG
  1126. * to use. This requires a new QE library function that manages BRG
  1127. * assignments.
  1128. */
  1129. sprop = of_get_property(np, "rx-clock-name", NULL);
  1130. if (!sprop) {
  1131. dev_err(&ofdev->dev, "missing rx-clock-name in device tree\n");
  1132. ret = -ENODEV;
  1133. goto out_free;
  1134. }
  1135. qe_port->us_info.rx_clock = qe_clock_source(sprop);
  1136. if ((qe_port->us_info.rx_clock < QE_BRG1) ||
  1137. (qe_port->us_info.rx_clock > QE_BRG16)) {
  1138. dev_err(&ofdev->dev, "rx-clock-name must be a BRG for UART\n");
  1139. ret = -ENODEV;
  1140. goto out_free;
  1141. }
  1142. #ifdef LOOPBACK
  1143. /* In internal loopback mode, TX and RX must use the same clock */
  1144. qe_port->us_info.tx_clock = qe_port->us_info.rx_clock;
  1145. #else
  1146. sprop = of_get_property(np, "tx-clock-name", NULL);
  1147. if (!sprop) {
  1148. dev_err(&ofdev->dev, "missing tx-clock-name in device tree\n");
  1149. ret = -ENODEV;
  1150. goto out_free;
  1151. }
  1152. qe_port->us_info.tx_clock = qe_clock_source(sprop);
  1153. #endif
  1154. if ((qe_port->us_info.tx_clock < QE_BRG1) ||
  1155. (qe_port->us_info.tx_clock > QE_BRG16)) {
  1156. dev_err(&ofdev->dev, "tx-clock-name must be a BRG for UART\n");
  1157. ret = -ENODEV;
  1158. goto out_free;
  1159. }
  1160. /* Get the port number, numbered 0-3 */
  1161. iprop = of_get_property(np, "port-number", NULL);
  1162. if (!iprop) {
  1163. dev_err(&ofdev->dev, "missing port-number in device tree\n");
  1164. ret = -EINVAL;
  1165. goto out_free;
  1166. }
  1167. qe_port->port.line = *iprop;
  1168. if (qe_port->port.line >= UCC_MAX_UART) {
  1169. dev_err(&ofdev->dev, "port-number must be 0-%u\n",
  1170. UCC_MAX_UART - 1);
  1171. ret = -EINVAL;
  1172. goto out_free;
  1173. }
  1174. qe_port->port.irq = irq_of_parse_and_map(np, 0);
  1175. if (qe_port->port.irq == 0) {
  1176. dev_err(&ofdev->dev, "could not map IRQ for UCC%u\n",
  1177. qe_port->ucc_num + 1);
  1178. ret = -EINVAL;
  1179. goto out_free;
  1180. }
  1181. /*
  1182. * Newer device trees have an "fsl,qe" compatible property for the QE
  1183. * node, but we still need to support older device trees.
  1184. */
  1185. np = of_find_compatible_node(NULL, NULL, "fsl,qe");
  1186. if (!np) {
  1187. np = of_find_node_by_type(NULL, "qe");
  1188. if (!np) {
  1189. dev_err(&ofdev->dev, "could not find 'qe' node\n");
  1190. ret = -EINVAL;
  1191. goto out_free;
  1192. }
  1193. }
  1194. iprop = of_get_property(np, "brg-frequency", NULL);
  1195. if (!iprop) {
  1196. dev_err(&ofdev->dev,
  1197. "missing brg-frequency in device tree\n");
  1198. ret = -EINVAL;
  1199. goto out_np;
  1200. }
  1201. if (*iprop)
  1202. qe_port->port.uartclk = *iprop;
  1203. else {
  1204. /*
  1205. * Older versions of U-Boot do not initialize the brg-frequency
  1206. * property, so in this case we assume the BRG frequency is
  1207. * half the QE bus frequency.
  1208. */
  1209. iprop = of_get_property(np, "bus-frequency", NULL);
  1210. if (!iprop) {
  1211. dev_err(&ofdev->dev,
  1212. "missing QE bus-frequency in device tree\n");
  1213. ret = -EINVAL;
  1214. goto out_np;
  1215. }
  1216. if (*iprop)
  1217. qe_port->port.uartclk = *iprop / 2;
  1218. else {
  1219. dev_err(&ofdev->dev,
  1220. "invalid QE bus-frequency in device tree\n");
  1221. ret = -EINVAL;
  1222. goto out_np;
  1223. }
  1224. }
  1225. spin_lock_init(&qe_port->port.lock);
  1226. qe_port->np = np;
  1227. qe_port->port.dev = &ofdev->dev;
  1228. qe_port->port.ops = &qe_uart_pops;
  1229. qe_port->port.iotype = UPIO_MEM;
  1230. qe_port->tx_nrfifos = TX_NUM_FIFO;
  1231. qe_port->tx_fifosize = TX_BUF_SIZE;
  1232. qe_port->rx_nrfifos = RX_NUM_FIFO;
  1233. qe_port->rx_fifosize = RX_BUF_SIZE;
  1234. qe_port->wait_closing = UCC_WAIT_CLOSING;
  1235. qe_port->port.fifosize = 512;
  1236. qe_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
  1237. qe_port->us_info.ucc_num = qe_port->ucc_num;
  1238. qe_port->us_info.regs = (phys_addr_t) res.start;
  1239. qe_port->us_info.irq = qe_port->port.irq;
  1240. qe_port->us_info.rx_bd_ring_len = qe_port->rx_nrfifos;
  1241. qe_port->us_info.tx_bd_ring_len = qe_port->tx_nrfifos;
  1242. /* Make sure ucc_slow_init() initializes both TX and RX */
  1243. qe_port->us_info.init_tx = 1;
  1244. qe_port->us_info.init_rx = 1;
  1245. /* Add the port to the uart sub-system. This will cause
  1246. * qe_uart_config_port() to be called, so the us_info structure must
  1247. * be initialized.
  1248. */
  1249. ret = uart_add_one_port(&ucc_uart_driver, &qe_port->port);
  1250. if (ret) {
  1251. dev_err(&ofdev->dev, "could not add /dev/ttyQE%u\n",
  1252. qe_port->port.line);
  1253. goto out_np;
  1254. }
  1255. platform_set_drvdata(ofdev, qe_port);
  1256. dev_info(&ofdev->dev, "UCC%u assigned to /dev/ttyQE%u\n",
  1257. qe_port->ucc_num + 1, qe_port->port.line);
  1258. /* Display the mknod command for this device */
  1259. dev_dbg(&ofdev->dev, "mknod command is 'mknod /dev/ttyQE%u c %u %u'\n",
  1260. qe_port->port.line, SERIAL_QE_MAJOR,
  1261. SERIAL_QE_MINOR + qe_port->port.line);
  1262. return 0;
  1263. out_np:
  1264. of_node_put(np);
  1265. out_free:
  1266. kfree(qe_port);
  1267. return ret;
  1268. }
  1269. static int ucc_uart_remove(struct platform_device *ofdev)
  1270. {
  1271. struct uart_qe_port *qe_port = platform_get_drvdata(ofdev);
  1272. dev_info(&ofdev->dev, "removing /dev/ttyQE%u\n", qe_port->port.line);
  1273. uart_remove_one_port(&ucc_uart_driver, &qe_port->port);
  1274. kfree(qe_port);
  1275. return 0;
  1276. }
  1277. static const struct of_device_id ucc_uart_match[] = {
  1278. {
  1279. .type = "serial",
  1280. .compatible = "ucc_uart",
  1281. },
  1282. {
  1283. .compatible = "fsl,t1040-ucc-uart",
  1284. },
  1285. {},
  1286. };
  1287. MODULE_DEVICE_TABLE(of, ucc_uart_match);
  1288. static struct platform_driver ucc_uart_of_driver = {
  1289. .driver = {
  1290. .name = "ucc_uart",
  1291. .of_match_table = ucc_uart_match,
  1292. },
  1293. .probe = ucc_uart_probe,
  1294. .remove = ucc_uart_remove,
  1295. };
  1296. static int __init ucc_uart_init(void)
  1297. {
  1298. int ret;
  1299. printk(KERN_INFO "Freescale QUICC Engine UART device driver\n");
  1300. #ifdef LOOPBACK
  1301. printk(KERN_INFO "ucc-uart: Using loopback mode\n");
  1302. #endif
  1303. ret = uart_register_driver(&ucc_uart_driver);
  1304. if (ret) {
  1305. printk(KERN_ERR "ucc-uart: could not register UART driver\n");
  1306. return ret;
  1307. }
  1308. ret = platform_driver_register(&ucc_uart_of_driver);
  1309. if (ret) {
  1310. printk(KERN_ERR
  1311. "ucc-uart: could not register platform driver\n");
  1312. uart_unregister_driver(&ucc_uart_driver);
  1313. }
  1314. return ret;
  1315. }
  1316. static void __exit ucc_uart_exit(void)
  1317. {
  1318. printk(KERN_INFO
  1319. "Freescale QUICC Engine UART device driver unloading\n");
  1320. platform_driver_unregister(&ucc_uart_of_driver);
  1321. uart_unregister_driver(&ucc_uart_driver);
  1322. }
  1323. module_init(ucc_uart_init);
  1324. module_exit(ucc_uart_exit);
  1325. MODULE_DESCRIPTION("Freescale QUICC Engine (QE) UART");
  1326. MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
  1327. MODULE_LICENSE("GPL v2");
  1328. MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_QE_MAJOR);