pnx8xxx_uart.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * UART driver for PNX8XXX SoCs
  4. *
  5. * Author: Per Hallsmark per.hallsmark@mvista.com
  6. * Ported to 2.6 kernel by EmbeddedAlley
  7. * Reworked by Vitaly Wool <vitalywool@gmail.com>
  8. *
  9. * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
  10. * Copyright (C) 2000 Deep Blue Solutions Ltd.
  11. */
  12. #if defined(CONFIG_SERIAL_PNX8XXX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  13. #define SUPPORT_SYSRQ
  14. #endif
  15. #include <linux/module.h>
  16. #include <linux/ioport.h>
  17. #include <linux/init.h>
  18. #include <linux/console.h>
  19. #include <linux/sysrq.h>
  20. #include <linux/device.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/tty.h>
  23. #include <linux/tty_flip.h>
  24. #include <linux/serial_core.h>
  25. #include <linux/serial.h>
  26. #include <linux/serial_pnx8xxx.h>
  27. #include <asm/io.h>
  28. #include <asm/irq.h>
  29. /* We'll be using StrongARM sa1100 serial port major/minor */
  30. #define SERIAL_PNX8XXX_MAJOR 204
  31. #define MINOR_START 5
  32. #define NR_PORTS 2
  33. #define PNX8XXX_ISR_PASS_LIMIT 256
  34. /*
  35. * Convert from ignore_status_mask or read_status_mask to FIFO
  36. * and interrupt status bits
  37. */
  38. #define SM_TO_FIFO(x) ((x) >> 10)
  39. #define SM_TO_ISTAT(x) ((x) & 0x000001ff)
  40. #define FIFO_TO_SM(x) ((x) << 10)
  41. #define ISTAT_TO_SM(x) ((x) & 0x000001ff)
  42. /*
  43. * This is the size of our serial port register set.
  44. */
  45. #define UART_PORT_SIZE 0x1000
  46. /*
  47. * This determines how often we check the modem status signals
  48. * for any change. They generally aren't connected to an IRQ
  49. * so we have to poll them. We also check immediately before
  50. * filling the TX fifo incase CTS has been dropped.
  51. */
  52. #define MCTRL_TIMEOUT (250*HZ/1000)
  53. extern struct pnx8xxx_port pnx8xxx_ports[];
  54. static inline int serial_in(struct pnx8xxx_port *sport, int offset)
  55. {
  56. return (__raw_readl(sport->port.membase + offset));
  57. }
  58. static inline void serial_out(struct pnx8xxx_port *sport, int offset, int value)
  59. {
  60. __raw_writel(value, sport->port.membase + offset);
  61. }
  62. /*
  63. * Handle any change of modem status signal since we were last called.
  64. */
  65. static void pnx8xxx_mctrl_check(struct pnx8xxx_port *sport)
  66. {
  67. unsigned int status, changed;
  68. status = sport->port.ops->get_mctrl(&sport->port);
  69. changed = status ^ sport->old_status;
  70. if (changed == 0)
  71. return;
  72. sport->old_status = status;
  73. if (changed & TIOCM_RI)
  74. sport->port.icount.rng++;
  75. if (changed & TIOCM_DSR)
  76. sport->port.icount.dsr++;
  77. if (changed & TIOCM_CAR)
  78. uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
  79. if (changed & TIOCM_CTS)
  80. uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
  81. wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
  82. }
  83. /*
  84. * This is our per-port timeout handler, for checking the
  85. * modem status signals.
  86. */
  87. static void pnx8xxx_timeout(struct timer_list *t)
  88. {
  89. struct pnx8xxx_port *sport = from_timer(sport, t, timer);
  90. unsigned long flags;
  91. if (sport->port.state) {
  92. spin_lock_irqsave(&sport->port.lock, flags);
  93. pnx8xxx_mctrl_check(sport);
  94. spin_unlock_irqrestore(&sport->port.lock, flags);
  95. mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
  96. }
  97. }
  98. /*
  99. * interrupts disabled on entry
  100. */
  101. static void pnx8xxx_stop_tx(struct uart_port *port)
  102. {
  103. struct pnx8xxx_port *sport =
  104. container_of(port, struct pnx8xxx_port, port);
  105. u32 ien;
  106. /* Disable TX intr */
  107. ien = serial_in(sport, PNX8XXX_IEN);
  108. serial_out(sport, PNX8XXX_IEN, ien & ~PNX8XXX_UART_INT_ALLTX);
  109. /* Clear all pending TX intr */
  110. serial_out(sport, PNX8XXX_ICLR, PNX8XXX_UART_INT_ALLTX);
  111. }
  112. /*
  113. * interrupts may not be disabled on entry
  114. */
  115. static void pnx8xxx_start_tx(struct uart_port *port)
  116. {
  117. struct pnx8xxx_port *sport =
  118. container_of(port, struct pnx8xxx_port, port);
  119. u32 ien;
  120. /* Clear all pending TX intr */
  121. serial_out(sport, PNX8XXX_ICLR, PNX8XXX_UART_INT_ALLTX);
  122. /* Enable TX intr */
  123. ien = serial_in(sport, PNX8XXX_IEN);
  124. serial_out(sport, PNX8XXX_IEN, ien | PNX8XXX_UART_INT_ALLTX);
  125. }
  126. /*
  127. * Interrupts enabled
  128. */
  129. static void pnx8xxx_stop_rx(struct uart_port *port)
  130. {
  131. struct pnx8xxx_port *sport =
  132. container_of(port, struct pnx8xxx_port, port);
  133. u32 ien;
  134. /* Disable RX intr */
  135. ien = serial_in(sport, PNX8XXX_IEN);
  136. serial_out(sport, PNX8XXX_IEN, ien & ~PNX8XXX_UART_INT_ALLRX);
  137. /* Clear all pending RX intr */
  138. serial_out(sport, PNX8XXX_ICLR, PNX8XXX_UART_INT_ALLRX);
  139. }
  140. /*
  141. * Set the modem control timer to fire immediately.
  142. */
  143. static void pnx8xxx_enable_ms(struct uart_port *port)
  144. {
  145. struct pnx8xxx_port *sport =
  146. container_of(port, struct pnx8xxx_port, port);
  147. mod_timer(&sport->timer, jiffies);
  148. }
  149. static void pnx8xxx_rx_chars(struct pnx8xxx_port *sport)
  150. {
  151. unsigned int status, ch, flg;
  152. status = FIFO_TO_SM(serial_in(sport, PNX8XXX_FIFO)) |
  153. ISTAT_TO_SM(serial_in(sport, PNX8XXX_ISTAT));
  154. while (status & FIFO_TO_SM(PNX8XXX_UART_FIFO_RXFIFO)) {
  155. ch = serial_in(sport, PNX8XXX_FIFO) & 0xff;
  156. sport->port.icount.rx++;
  157. flg = TTY_NORMAL;
  158. /*
  159. * note that the error handling code is
  160. * out of the main execution path
  161. */
  162. if (status & (FIFO_TO_SM(PNX8XXX_UART_FIFO_RXFE |
  163. PNX8XXX_UART_FIFO_RXPAR |
  164. PNX8XXX_UART_FIFO_RXBRK) |
  165. ISTAT_TO_SM(PNX8XXX_UART_INT_RXOVRN))) {
  166. if (status & FIFO_TO_SM(PNX8XXX_UART_FIFO_RXBRK)) {
  167. status &= ~(FIFO_TO_SM(PNX8XXX_UART_FIFO_RXFE) |
  168. FIFO_TO_SM(PNX8XXX_UART_FIFO_RXPAR));
  169. sport->port.icount.brk++;
  170. if (uart_handle_break(&sport->port))
  171. goto ignore_char;
  172. } else if (status & FIFO_TO_SM(PNX8XXX_UART_FIFO_RXPAR))
  173. sport->port.icount.parity++;
  174. else if (status & FIFO_TO_SM(PNX8XXX_UART_FIFO_RXFE))
  175. sport->port.icount.frame++;
  176. if (status & ISTAT_TO_SM(PNX8XXX_UART_INT_RXOVRN))
  177. sport->port.icount.overrun++;
  178. status &= sport->port.read_status_mask;
  179. if (status & FIFO_TO_SM(PNX8XXX_UART_FIFO_RXPAR))
  180. flg = TTY_PARITY;
  181. else if (status & FIFO_TO_SM(PNX8XXX_UART_FIFO_RXFE))
  182. flg = TTY_FRAME;
  183. #ifdef SUPPORT_SYSRQ
  184. sport->port.sysrq = 0;
  185. #endif
  186. }
  187. if (uart_handle_sysrq_char(&sport->port, ch))
  188. goto ignore_char;
  189. uart_insert_char(&sport->port, status,
  190. ISTAT_TO_SM(PNX8XXX_UART_INT_RXOVRN), ch, flg);
  191. ignore_char:
  192. serial_out(sport, PNX8XXX_LCR, serial_in(sport, PNX8XXX_LCR) |
  193. PNX8XXX_UART_LCR_RX_NEXT);
  194. status = FIFO_TO_SM(serial_in(sport, PNX8XXX_FIFO)) |
  195. ISTAT_TO_SM(serial_in(sport, PNX8XXX_ISTAT));
  196. }
  197. spin_unlock(&sport->port.lock);
  198. tty_flip_buffer_push(&sport->port.state->port);
  199. spin_lock(&sport->port.lock);
  200. }
  201. static void pnx8xxx_tx_chars(struct pnx8xxx_port *sport)
  202. {
  203. struct circ_buf *xmit = &sport->port.state->xmit;
  204. if (sport->port.x_char) {
  205. serial_out(sport, PNX8XXX_FIFO, sport->port.x_char);
  206. sport->port.icount.tx++;
  207. sport->port.x_char = 0;
  208. return;
  209. }
  210. /*
  211. * Check the modem control lines before
  212. * transmitting anything.
  213. */
  214. pnx8xxx_mctrl_check(sport);
  215. if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
  216. pnx8xxx_stop_tx(&sport->port);
  217. return;
  218. }
  219. /*
  220. * TX while bytes available
  221. */
  222. while (((serial_in(sport, PNX8XXX_FIFO) &
  223. PNX8XXX_UART_FIFO_TXFIFO) >> 16) < 16) {
  224. serial_out(sport, PNX8XXX_FIFO, xmit->buf[xmit->tail]);
  225. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  226. sport->port.icount.tx++;
  227. if (uart_circ_empty(xmit))
  228. break;
  229. }
  230. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  231. uart_write_wakeup(&sport->port);
  232. if (uart_circ_empty(xmit))
  233. pnx8xxx_stop_tx(&sport->port);
  234. }
  235. static irqreturn_t pnx8xxx_int(int irq, void *dev_id)
  236. {
  237. struct pnx8xxx_port *sport = dev_id;
  238. unsigned int status;
  239. spin_lock(&sport->port.lock);
  240. /* Get the interrupts */
  241. status = serial_in(sport, PNX8XXX_ISTAT) & serial_in(sport, PNX8XXX_IEN);
  242. /* Byte or break signal received */
  243. if (status & (PNX8XXX_UART_INT_RX | PNX8XXX_UART_INT_BREAK))
  244. pnx8xxx_rx_chars(sport);
  245. /* TX holding register empty - transmit a byte */
  246. if (status & PNX8XXX_UART_INT_TX)
  247. pnx8xxx_tx_chars(sport);
  248. /* Clear the ISTAT register */
  249. serial_out(sport, PNX8XXX_ICLR, status);
  250. spin_unlock(&sport->port.lock);
  251. return IRQ_HANDLED;
  252. }
  253. /*
  254. * Return TIOCSER_TEMT when transmitter is not busy.
  255. */
  256. static unsigned int pnx8xxx_tx_empty(struct uart_port *port)
  257. {
  258. struct pnx8xxx_port *sport =
  259. container_of(port, struct pnx8xxx_port, port);
  260. return serial_in(sport, PNX8XXX_FIFO) & PNX8XXX_UART_FIFO_TXFIFO_STA ? 0 : TIOCSER_TEMT;
  261. }
  262. static unsigned int pnx8xxx_get_mctrl(struct uart_port *port)
  263. {
  264. struct pnx8xxx_port *sport =
  265. container_of(port, struct pnx8xxx_port, port);
  266. unsigned int mctrl = TIOCM_DSR;
  267. unsigned int msr;
  268. /* REVISIT */
  269. msr = serial_in(sport, PNX8XXX_MCR);
  270. mctrl |= msr & PNX8XXX_UART_MCR_CTS ? TIOCM_CTS : 0;
  271. mctrl |= msr & PNX8XXX_UART_MCR_DCD ? TIOCM_CAR : 0;
  272. return mctrl;
  273. }
  274. static void pnx8xxx_set_mctrl(struct uart_port *port, unsigned int mctrl)
  275. {
  276. #if 0 /* FIXME */
  277. struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
  278. unsigned int msr;
  279. #endif
  280. }
  281. /*
  282. * Interrupts always disabled.
  283. */
  284. static void pnx8xxx_break_ctl(struct uart_port *port, int break_state)
  285. {
  286. struct pnx8xxx_port *sport =
  287. container_of(port, struct pnx8xxx_port, port);
  288. unsigned long flags;
  289. unsigned int lcr;
  290. spin_lock_irqsave(&sport->port.lock, flags);
  291. lcr = serial_in(sport, PNX8XXX_LCR);
  292. if (break_state == -1)
  293. lcr |= PNX8XXX_UART_LCR_TXBREAK;
  294. else
  295. lcr &= ~PNX8XXX_UART_LCR_TXBREAK;
  296. serial_out(sport, PNX8XXX_LCR, lcr);
  297. spin_unlock_irqrestore(&sport->port.lock, flags);
  298. }
  299. static int pnx8xxx_startup(struct uart_port *port)
  300. {
  301. struct pnx8xxx_port *sport =
  302. container_of(port, struct pnx8xxx_port, port);
  303. int retval;
  304. /*
  305. * Allocate the IRQ
  306. */
  307. retval = request_irq(sport->port.irq, pnx8xxx_int, 0,
  308. "pnx8xxx-uart", sport);
  309. if (retval)
  310. return retval;
  311. /*
  312. * Finally, clear and enable interrupts
  313. */
  314. serial_out(sport, PNX8XXX_ICLR, PNX8XXX_UART_INT_ALLRX |
  315. PNX8XXX_UART_INT_ALLTX);
  316. serial_out(sport, PNX8XXX_IEN, serial_in(sport, PNX8XXX_IEN) |
  317. PNX8XXX_UART_INT_ALLRX |
  318. PNX8XXX_UART_INT_ALLTX);
  319. /*
  320. * Enable modem status interrupts
  321. */
  322. spin_lock_irq(&sport->port.lock);
  323. pnx8xxx_enable_ms(&sport->port);
  324. spin_unlock_irq(&sport->port.lock);
  325. return 0;
  326. }
  327. static void pnx8xxx_shutdown(struct uart_port *port)
  328. {
  329. struct pnx8xxx_port *sport =
  330. container_of(port, struct pnx8xxx_port, port);
  331. int lcr;
  332. /*
  333. * Stop our timer.
  334. */
  335. del_timer_sync(&sport->timer);
  336. /*
  337. * Disable all interrupts
  338. */
  339. serial_out(sport, PNX8XXX_IEN, 0);
  340. /*
  341. * Reset the Tx and Rx FIFOS, disable the break condition
  342. */
  343. lcr = serial_in(sport, PNX8XXX_LCR);
  344. lcr &= ~PNX8XXX_UART_LCR_TXBREAK;
  345. lcr |= PNX8XXX_UART_LCR_TX_RST | PNX8XXX_UART_LCR_RX_RST;
  346. serial_out(sport, PNX8XXX_LCR, lcr);
  347. /*
  348. * Clear all interrupts
  349. */
  350. serial_out(sport, PNX8XXX_ICLR, PNX8XXX_UART_INT_ALLRX |
  351. PNX8XXX_UART_INT_ALLTX);
  352. /*
  353. * Free the interrupt
  354. */
  355. free_irq(sport->port.irq, sport);
  356. }
  357. static void
  358. pnx8xxx_set_termios(struct uart_port *port, struct ktermios *termios,
  359. struct ktermios *old)
  360. {
  361. struct pnx8xxx_port *sport =
  362. container_of(port, struct pnx8xxx_port, port);
  363. unsigned long flags;
  364. unsigned int lcr_fcr, old_ien, baud, quot;
  365. unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
  366. /*
  367. * We only support CS7 and CS8.
  368. */
  369. while ((termios->c_cflag & CSIZE) != CS7 &&
  370. (termios->c_cflag & CSIZE) != CS8) {
  371. termios->c_cflag &= ~CSIZE;
  372. termios->c_cflag |= old_csize;
  373. old_csize = CS8;
  374. }
  375. if ((termios->c_cflag & CSIZE) == CS8)
  376. lcr_fcr = PNX8XXX_UART_LCR_8BIT;
  377. else
  378. lcr_fcr = 0;
  379. if (termios->c_cflag & CSTOPB)
  380. lcr_fcr |= PNX8XXX_UART_LCR_2STOPB;
  381. if (termios->c_cflag & PARENB) {
  382. lcr_fcr |= PNX8XXX_UART_LCR_PAREN;
  383. if (!(termios->c_cflag & PARODD))
  384. lcr_fcr |= PNX8XXX_UART_LCR_PAREVN;
  385. }
  386. /*
  387. * Ask the core to calculate the divisor for us.
  388. */
  389. baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
  390. quot = uart_get_divisor(port, baud);
  391. spin_lock_irqsave(&sport->port.lock, flags);
  392. sport->port.read_status_mask = ISTAT_TO_SM(PNX8XXX_UART_INT_RXOVRN) |
  393. ISTAT_TO_SM(PNX8XXX_UART_INT_EMPTY) |
  394. ISTAT_TO_SM(PNX8XXX_UART_INT_RX);
  395. if (termios->c_iflag & INPCK)
  396. sport->port.read_status_mask |=
  397. FIFO_TO_SM(PNX8XXX_UART_FIFO_RXFE) |
  398. FIFO_TO_SM(PNX8XXX_UART_FIFO_RXPAR);
  399. if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
  400. sport->port.read_status_mask |=
  401. ISTAT_TO_SM(PNX8XXX_UART_INT_BREAK);
  402. /*
  403. * Characters to ignore
  404. */
  405. sport->port.ignore_status_mask = 0;
  406. if (termios->c_iflag & IGNPAR)
  407. sport->port.ignore_status_mask |=
  408. FIFO_TO_SM(PNX8XXX_UART_FIFO_RXFE) |
  409. FIFO_TO_SM(PNX8XXX_UART_FIFO_RXPAR);
  410. if (termios->c_iflag & IGNBRK) {
  411. sport->port.ignore_status_mask |=
  412. ISTAT_TO_SM(PNX8XXX_UART_INT_BREAK);
  413. /*
  414. * If we're ignoring parity and break indicators,
  415. * ignore overruns too (for real raw support).
  416. */
  417. if (termios->c_iflag & IGNPAR)
  418. sport->port.ignore_status_mask |=
  419. ISTAT_TO_SM(PNX8XXX_UART_INT_RXOVRN);
  420. }
  421. /*
  422. * ignore all characters if CREAD is not set
  423. */
  424. if ((termios->c_cflag & CREAD) == 0)
  425. sport->port.ignore_status_mask |=
  426. ISTAT_TO_SM(PNX8XXX_UART_INT_RX);
  427. del_timer_sync(&sport->timer);
  428. /*
  429. * Update the per-port timeout.
  430. */
  431. uart_update_timeout(port, termios->c_cflag, baud);
  432. /*
  433. * disable interrupts and drain transmitter
  434. */
  435. old_ien = serial_in(sport, PNX8XXX_IEN);
  436. serial_out(sport, PNX8XXX_IEN, old_ien & ~(PNX8XXX_UART_INT_ALLTX |
  437. PNX8XXX_UART_INT_ALLRX));
  438. while (serial_in(sport, PNX8XXX_FIFO) & PNX8XXX_UART_FIFO_TXFIFO_STA)
  439. barrier();
  440. /* then, disable everything */
  441. serial_out(sport, PNX8XXX_IEN, 0);
  442. /* Reset the Rx and Tx FIFOs too */
  443. lcr_fcr |= PNX8XXX_UART_LCR_TX_RST;
  444. lcr_fcr |= PNX8XXX_UART_LCR_RX_RST;
  445. /* set the parity, stop bits and data size */
  446. serial_out(sport, PNX8XXX_LCR, lcr_fcr);
  447. /* set the baud rate */
  448. quot -= 1;
  449. serial_out(sport, PNX8XXX_BAUD, quot);
  450. serial_out(sport, PNX8XXX_ICLR, -1);
  451. serial_out(sport, PNX8XXX_IEN, old_ien);
  452. if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
  453. pnx8xxx_enable_ms(&sport->port);
  454. spin_unlock_irqrestore(&sport->port.lock, flags);
  455. }
  456. static const char *pnx8xxx_type(struct uart_port *port)
  457. {
  458. struct pnx8xxx_port *sport =
  459. container_of(port, struct pnx8xxx_port, port);
  460. return sport->port.type == PORT_PNX8XXX ? "PNX8XXX" : NULL;
  461. }
  462. /*
  463. * Release the memory region(s) being used by 'port'.
  464. */
  465. static void pnx8xxx_release_port(struct uart_port *port)
  466. {
  467. struct pnx8xxx_port *sport =
  468. container_of(port, struct pnx8xxx_port, port);
  469. release_mem_region(sport->port.mapbase, UART_PORT_SIZE);
  470. }
  471. /*
  472. * Request the memory region(s) being used by 'port'.
  473. */
  474. static int pnx8xxx_request_port(struct uart_port *port)
  475. {
  476. struct pnx8xxx_port *sport =
  477. container_of(port, struct pnx8xxx_port, port);
  478. return request_mem_region(sport->port.mapbase, UART_PORT_SIZE,
  479. "pnx8xxx-uart") != NULL ? 0 : -EBUSY;
  480. }
  481. /*
  482. * Configure/autoconfigure the port.
  483. */
  484. static void pnx8xxx_config_port(struct uart_port *port, int flags)
  485. {
  486. struct pnx8xxx_port *sport =
  487. container_of(port, struct pnx8xxx_port, port);
  488. if (flags & UART_CONFIG_TYPE &&
  489. pnx8xxx_request_port(&sport->port) == 0)
  490. sport->port.type = PORT_PNX8XXX;
  491. }
  492. /*
  493. * Verify the new serial_struct (for TIOCSSERIAL).
  494. * The only change we allow are to the flags and type, and
  495. * even then only between PORT_PNX8XXX and PORT_UNKNOWN
  496. */
  497. static int
  498. pnx8xxx_verify_port(struct uart_port *port, struct serial_struct *ser)
  499. {
  500. struct pnx8xxx_port *sport =
  501. container_of(port, struct pnx8xxx_port, port);
  502. int ret = 0;
  503. if (ser->type != PORT_UNKNOWN && ser->type != PORT_PNX8XXX)
  504. ret = -EINVAL;
  505. if (sport->port.irq != ser->irq)
  506. ret = -EINVAL;
  507. if (ser->io_type != SERIAL_IO_MEM)
  508. ret = -EINVAL;
  509. if (sport->port.uartclk / 16 != ser->baud_base)
  510. ret = -EINVAL;
  511. if ((void *)sport->port.mapbase != ser->iomem_base)
  512. ret = -EINVAL;
  513. if (sport->port.iobase != ser->port)
  514. ret = -EINVAL;
  515. if (ser->hub6 != 0)
  516. ret = -EINVAL;
  517. return ret;
  518. }
  519. static const struct uart_ops pnx8xxx_pops = {
  520. .tx_empty = pnx8xxx_tx_empty,
  521. .set_mctrl = pnx8xxx_set_mctrl,
  522. .get_mctrl = pnx8xxx_get_mctrl,
  523. .stop_tx = pnx8xxx_stop_tx,
  524. .start_tx = pnx8xxx_start_tx,
  525. .stop_rx = pnx8xxx_stop_rx,
  526. .enable_ms = pnx8xxx_enable_ms,
  527. .break_ctl = pnx8xxx_break_ctl,
  528. .startup = pnx8xxx_startup,
  529. .shutdown = pnx8xxx_shutdown,
  530. .set_termios = pnx8xxx_set_termios,
  531. .type = pnx8xxx_type,
  532. .release_port = pnx8xxx_release_port,
  533. .request_port = pnx8xxx_request_port,
  534. .config_port = pnx8xxx_config_port,
  535. .verify_port = pnx8xxx_verify_port,
  536. };
  537. /*
  538. * Setup the PNX8XXX serial ports.
  539. *
  540. * Note also that we support "console=ttySx" where "x" is either 0 or 1.
  541. */
  542. static void __init pnx8xxx_init_ports(void)
  543. {
  544. static int first = 1;
  545. int i;
  546. if (!first)
  547. return;
  548. first = 0;
  549. for (i = 0; i < NR_PORTS; i++) {
  550. timer_setup(&pnx8xxx_ports[i].timer, pnx8xxx_timeout, 0);
  551. pnx8xxx_ports[i].port.ops = &pnx8xxx_pops;
  552. }
  553. }
  554. #ifdef CONFIG_SERIAL_PNX8XXX_CONSOLE
  555. static void pnx8xxx_console_putchar(struct uart_port *port, int ch)
  556. {
  557. struct pnx8xxx_port *sport =
  558. container_of(port, struct pnx8xxx_port, port);
  559. int status;
  560. do {
  561. /* Wait for UART_TX register to empty */
  562. status = serial_in(sport, PNX8XXX_FIFO);
  563. } while (status & PNX8XXX_UART_FIFO_TXFIFO);
  564. serial_out(sport, PNX8XXX_FIFO, ch);
  565. }
  566. /*
  567. * Interrupts are disabled on entering
  568. */static void
  569. pnx8xxx_console_write(struct console *co, const char *s, unsigned int count)
  570. {
  571. struct pnx8xxx_port *sport = &pnx8xxx_ports[co->index];
  572. unsigned int old_ien, status;
  573. /*
  574. * First, save IEN and then disable interrupts
  575. */
  576. old_ien = serial_in(sport, PNX8XXX_IEN);
  577. serial_out(sport, PNX8XXX_IEN, old_ien & ~(PNX8XXX_UART_INT_ALLTX |
  578. PNX8XXX_UART_INT_ALLRX));
  579. uart_console_write(&sport->port, s, count, pnx8xxx_console_putchar);
  580. /*
  581. * Finally, wait for transmitter to become empty
  582. * and restore IEN
  583. */
  584. do {
  585. /* Wait for UART_TX register to empty */
  586. status = serial_in(sport, PNX8XXX_FIFO);
  587. } while (status & PNX8XXX_UART_FIFO_TXFIFO);
  588. /* Clear TX and EMPTY interrupt */
  589. serial_out(sport, PNX8XXX_ICLR, PNX8XXX_UART_INT_TX |
  590. PNX8XXX_UART_INT_EMPTY);
  591. serial_out(sport, PNX8XXX_IEN, old_ien);
  592. }
  593. static int __init
  594. pnx8xxx_console_setup(struct console *co, char *options)
  595. {
  596. struct pnx8xxx_port *sport;
  597. int baud = 38400;
  598. int bits = 8;
  599. int parity = 'n';
  600. int flow = 'n';
  601. /*
  602. * Check whether an invalid uart number has been specified, and
  603. * if so, search for the first available port that does have
  604. * console support.
  605. */
  606. if (co->index == -1 || co->index >= NR_PORTS)
  607. co->index = 0;
  608. sport = &pnx8xxx_ports[co->index];
  609. if (options)
  610. uart_parse_options(options, &baud, &parity, &bits, &flow);
  611. return uart_set_options(&sport->port, co, baud, parity, bits, flow);
  612. }
  613. static struct uart_driver pnx8xxx_reg;
  614. static struct console pnx8xxx_console = {
  615. .name = "ttyS",
  616. .write = pnx8xxx_console_write,
  617. .device = uart_console_device,
  618. .setup = pnx8xxx_console_setup,
  619. .flags = CON_PRINTBUFFER,
  620. .index = -1,
  621. .data = &pnx8xxx_reg,
  622. };
  623. static int __init pnx8xxx_rs_console_init(void)
  624. {
  625. pnx8xxx_init_ports();
  626. register_console(&pnx8xxx_console);
  627. return 0;
  628. }
  629. console_initcall(pnx8xxx_rs_console_init);
  630. #define PNX8XXX_CONSOLE &pnx8xxx_console
  631. #else
  632. #define PNX8XXX_CONSOLE NULL
  633. #endif
  634. static struct uart_driver pnx8xxx_reg = {
  635. .owner = THIS_MODULE,
  636. .driver_name = "ttyS",
  637. .dev_name = "ttyS",
  638. .major = SERIAL_PNX8XXX_MAJOR,
  639. .minor = MINOR_START,
  640. .nr = NR_PORTS,
  641. .cons = PNX8XXX_CONSOLE,
  642. };
  643. static int pnx8xxx_serial_suspend(struct platform_device *pdev, pm_message_t state)
  644. {
  645. struct pnx8xxx_port *sport = platform_get_drvdata(pdev);
  646. return uart_suspend_port(&pnx8xxx_reg, &sport->port);
  647. }
  648. static int pnx8xxx_serial_resume(struct platform_device *pdev)
  649. {
  650. struct pnx8xxx_port *sport = platform_get_drvdata(pdev);
  651. return uart_resume_port(&pnx8xxx_reg, &sport->port);
  652. }
  653. static int pnx8xxx_serial_probe(struct platform_device *pdev)
  654. {
  655. struct resource *res = pdev->resource;
  656. int i;
  657. for (i = 0; i < pdev->num_resources; i++, res++) {
  658. if (!(res->flags & IORESOURCE_MEM))
  659. continue;
  660. for (i = 0; i < NR_PORTS; i++) {
  661. if (pnx8xxx_ports[i].port.mapbase != res->start)
  662. continue;
  663. pnx8xxx_ports[i].port.dev = &pdev->dev;
  664. uart_add_one_port(&pnx8xxx_reg, &pnx8xxx_ports[i].port);
  665. platform_set_drvdata(pdev, &pnx8xxx_ports[i]);
  666. break;
  667. }
  668. }
  669. return 0;
  670. }
  671. static int pnx8xxx_serial_remove(struct platform_device *pdev)
  672. {
  673. struct pnx8xxx_port *sport = platform_get_drvdata(pdev);
  674. if (sport)
  675. uart_remove_one_port(&pnx8xxx_reg, &sport->port);
  676. return 0;
  677. }
  678. static struct platform_driver pnx8xxx_serial_driver = {
  679. .driver = {
  680. .name = "pnx8xxx-uart",
  681. },
  682. .probe = pnx8xxx_serial_probe,
  683. .remove = pnx8xxx_serial_remove,
  684. .suspend = pnx8xxx_serial_suspend,
  685. .resume = pnx8xxx_serial_resume,
  686. };
  687. static int __init pnx8xxx_serial_init(void)
  688. {
  689. int ret;
  690. printk(KERN_INFO "Serial: PNX8XXX driver\n");
  691. pnx8xxx_init_ports();
  692. ret = uart_register_driver(&pnx8xxx_reg);
  693. if (ret == 0) {
  694. ret = platform_driver_register(&pnx8xxx_serial_driver);
  695. if (ret)
  696. uart_unregister_driver(&pnx8xxx_reg);
  697. }
  698. return ret;
  699. }
  700. static void __exit pnx8xxx_serial_exit(void)
  701. {
  702. platform_driver_unregister(&pnx8xxx_serial_driver);
  703. uart_unregister_driver(&pnx8xxx_reg);
  704. }
  705. module_init(pnx8xxx_serial_init);
  706. module_exit(pnx8xxx_serial_exit);
  707. MODULE_AUTHOR("Embedded Alley Solutions, Inc.");
  708. MODULE_DESCRIPTION("PNX8XXX SoCs serial port driver");
  709. MODULE_LICENSE("GPL");
  710. MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_PNX8XXX_MAJOR);
  711. MODULE_ALIAS("platform:pnx8xxx-uart");