mcf.c 19 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /****************************************************************************/
  3. /*
  4. * mcf.c -- Freescale ColdFire UART driver
  5. *
  6. * (C) Copyright 2003-2007, Greg Ungerer <gerg@uclinux.org>
  7. */
  8. /****************************************************************************/
  9. #include <linux/kernel.h>
  10. #include <linux/init.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/module.h>
  13. #include <linux/console.h>
  14. #include <linux/tty.h>
  15. #include <linux/tty_flip.h>
  16. #include <linux/serial.h>
  17. #include <linux/serial_core.h>
  18. #include <linux/io.h>
  19. #include <linux/uaccess.h>
  20. #include <linux/platform_device.h>
  21. #include <asm/coldfire.h>
  22. #include <asm/mcfsim.h>
  23. #include <asm/mcfuart.h>
  24. #include <asm/nettel.h>
  25. /****************************************************************************/
  26. /*
  27. * Some boards implement the DTR/DCD lines using GPIO lines, most
  28. * don't. Dummy out the access macros for those that don't. Those
  29. * that do should define these macros somewhere in there board
  30. * specific inlude files.
  31. */
  32. #if !defined(mcf_getppdcd)
  33. #define mcf_getppdcd(p) (1)
  34. #endif
  35. #if !defined(mcf_getppdtr)
  36. #define mcf_getppdtr(p) (1)
  37. #endif
  38. #if !defined(mcf_setppdtr)
  39. #define mcf_setppdtr(p, v) do { } while (0)
  40. #endif
  41. /****************************************************************************/
  42. /*
  43. * Local per-uart structure.
  44. */
  45. struct mcf_uart {
  46. struct uart_port port;
  47. unsigned int sigs; /* Local copy of line sigs */
  48. unsigned char imr; /* Local IMR mirror */
  49. };
  50. /****************************************************************************/
  51. static unsigned int mcf_tx_empty(struct uart_port *port)
  52. {
  53. return (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXEMPTY) ?
  54. TIOCSER_TEMT : 0;
  55. }
  56. /****************************************************************************/
  57. static unsigned int mcf_get_mctrl(struct uart_port *port)
  58. {
  59. struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
  60. unsigned int sigs;
  61. sigs = (readb(port->membase + MCFUART_UIPR) & MCFUART_UIPR_CTS) ?
  62. 0 : TIOCM_CTS;
  63. sigs |= (pp->sigs & TIOCM_RTS);
  64. sigs |= (mcf_getppdcd(port->line) ? TIOCM_CD : 0);
  65. sigs |= (mcf_getppdtr(port->line) ? TIOCM_DTR : 0);
  66. return sigs;
  67. }
  68. /****************************************************************************/
  69. static void mcf_set_mctrl(struct uart_port *port, unsigned int sigs)
  70. {
  71. struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
  72. pp->sigs = sigs;
  73. mcf_setppdtr(port->line, (sigs & TIOCM_DTR));
  74. if (sigs & TIOCM_RTS)
  75. writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1);
  76. else
  77. writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP0);
  78. }
  79. /****************************************************************************/
  80. static void mcf_start_tx(struct uart_port *port)
  81. {
  82. struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
  83. if (port->rs485.flags & SER_RS485_ENABLED) {
  84. /* Enable Transmitter */
  85. writeb(MCFUART_UCR_TXENABLE, port->membase + MCFUART_UCR);
  86. /* Manually assert RTS */
  87. writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1);
  88. }
  89. pp->imr |= MCFUART_UIR_TXREADY;
  90. writeb(pp->imr, port->membase + MCFUART_UIMR);
  91. }
  92. /****************************************************************************/
  93. static void mcf_stop_tx(struct uart_port *port)
  94. {
  95. struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
  96. pp->imr &= ~MCFUART_UIR_TXREADY;
  97. writeb(pp->imr, port->membase + MCFUART_UIMR);
  98. }
  99. /****************************************************************************/
  100. static void mcf_stop_rx(struct uart_port *port)
  101. {
  102. struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
  103. pp->imr &= ~MCFUART_UIR_RXREADY;
  104. writeb(pp->imr, port->membase + MCFUART_UIMR);
  105. }
  106. /****************************************************************************/
  107. static void mcf_break_ctl(struct uart_port *port, int break_state)
  108. {
  109. unsigned long flags;
  110. spin_lock_irqsave(&port->lock, flags);
  111. if (break_state == -1)
  112. writeb(MCFUART_UCR_CMDBREAKSTART, port->membase + MCFUART_UCR);
  113. else
  114. writeb(MCFUART_UCR_CMDBREAKSTOP, port->membase + MCFUART_UCR);
  115. spin_unlock_irqrestore(&port->lock, flags);
  116. }
  117. /****************************************************************************/
  118. static int mcf_startup(struct uart_port *port)
  119. {
  120. struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
  121. unsigned long flags;
  122. spin_lock_irqsave(&port->lock, flags);
  123. /* Reset UART, get it into known state... */
  124. writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
  125. writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
  126. /* Enable the UART transmitter and receiver */
  127. writeb(MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE,
  128. port->membase + MCFUART_UCR);
  129. /* Enable RX interrupts now */
  130. pp->imr = MCFUART_UIR_RXREADY;
  131. writeb(pp->imr, port->membase + MCFUART_UIMR);
  132. spin_unlock_irqrestore(&port->lock, flags);
  133. return 0;
  134. }
  135. /****************************************************************************/
  136. static void mcf_shutdown(struct uart_port *port)
  137. {
  138. struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
  139. unsigned long flags;
  140. spin_lock_irqsave(&port->lock, flags);
  141. /* Disable all interrupts now */
  142. pp->imr = 0;
  143. writeb(pp->imr, port->membase + MCFUART_UIMR);
  144. /* Disable UART transmitter and receiver */
  145. writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
  146. writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
  147. spin_unlock_irqrestore(&port->lock, flags);
  148. }
  149. /****************************************************************************/
  150. static void mcf_set_termios(struct uart_port *port, struct ktermios *termios,
  151. struct ktermios *old)
  152. {
  153. unsigned long flags;
  154. unsigned int baud, baudclk;
  155. #if defined(CONFIG_M5272)
  156. unsigned int baudfr;
  157. #endif
  158. unsigned char mr1, mr2;
  159. baud = uart_get_baud_rate(port, termios, old, 0, 230400);
  160. #if defined(CONFIG_M5272)
  161. baudclk = (MCF_BUSCLK / baud) / 32;
  162. baudfr = (((MCF_BUSCLK / baud) + 1) / 2) % 16;
  163. #else
  164. baudclk = ((MCF_BUSCLK / baud) + 16) / 32;
  165. #endif
  166. mr1 = MCFUART_MR1_RXIRQRDY | MCFUART_MR1_RXERRCHAR;
  167. mr2 = 0;
  168. switch (termios->c_cflag & CSIZE) {
  169. case CS5: mr1 |= MCFUART_MR1_CS5; break;
  170. case CS6: mr1 |= MCFUART_MR1_CS6; break;
  171. case CS7: mr1 |= MCFUART_MR1_CS7; break;
  172. case CS8:
  173. default: mr1 |= MCFUART_MR1_CS8; break;
  174. }
  175. if (termios->c_cflag & PARENB) {
  176. if (termios->c_cflag & CMSPAR) {
  177. if (termios->c_cflag & PARODD)
  178. mr1 |= MCFUART_MR1_PARITYMARK;
  179. else
  180. mr1 |= MCFUART_MR1_PARITYSPACE;
  181. } else {
  182. if (termios->c_cflag & PARODD)
  183. mr1 |= MCFUART_MR1_PARITYODD;
  184. else
  185. mr1 |= MCFUART_MR1_PARITYEVEN;
  186. }
  187. } else {
  188. mr1 |= MCFUART_MR1_PARITYNONE;
  189. }
  190. /*
  191. * FIXME: port->read_status_mask and port->ignore_status_mask
  192. * need to be initialized based on termios settings for
  193. * INPCK, IGNBRK, IGNPAR, PARMRK, BRKINT
  194. */
  195. if (termios->c_cflag & CSTOPB)
  196. mr2 |= MCFUART_MR2_STOP2;
  197. else
  198. mr2 |= MCFUART_MR2_STOP1;
  199. if (termios->c_cflag & CRTSCTS) {
  200. mr1 |= MCFUART_MR1_RXRTS;
  201. mr2 |= MCFUART_MR2_TXCTS;
  202. }
  203. spin_lock_irqsave(&port->lock, flags);
  204. if (port->rs485.flags & SER_RS485_ENABLED) {
  205. dev_dbg(port->dev, "Setting UART to RS485\n");
  206. mr2 |= MCFUART_MR2_TXRTS;
  207. }
  208. uart_update_timeout(port, termios->c_cflag, baud);
  209. writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
  210. writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
  211. writeb(MCFUART_UCR_CMDRESETMRPTR, port->membase + MCFUART_UCR);
  212. writeb(mr1, port->membase + MCFUART_UMR);
  213. writeb(mr2, port->membase + MCFUART_UMR);
  214. writeb((baudclk & 0xff00) >> 8, port->membase + MCFUART_UBG1);
  215. writeb((baudclk & 0xff), port->membase + MCFUART_UBG2);
  216. #if defined(CONFIG_M5272)
  217. writeb((baudfr & 0x0f), port->membase + MCFUART_UFPD);
  218. #endif
  219. writeb(MCFUART_UCSR_RXCLKTIMER | MCFUART_UCSR_TXCLKTIMER,
  220. port->membase + MCFUART_UCSR);
  221. writeb(MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE,
  222. port->membase + MCFUART_UCR);
  223. spin_unlock_irqrestore(&port->lock, flags);
  224. }
  225. /****************************************************************************/
  226. static void mcf_rx_chars(struct mcf_uart *pp)
  227. {
  228. struct uart_port *port = &pp->port;
  229. unsigned char status, ch, flag;
  230. while ((status = readb(port->membase + MCFUART_USR)) & MCFUART_USR_RXREADY) {
  231. ch = readb(port->membase + MCFUART_URB);
  232. flag = TTY_NORMAL;
  233. port->icount.rx++;
  234. if (status & MCFUART_USR_RXERR) {
  235. writeb(MCFUART_UCR_CMDRESETERR,
  236. port->membase + MCFUART_UCR);
  237. if (status & MCFUART_USR_RXBREAK) {
  238. port->icount.brk++;
  239. if (uart_handle_break(port))
  240. continue;
  241. } else if (status & MCFUART_USR_RXPARITY) {
  242. port->icount.parity++;
  243. } else if (status & MCFUART_USR_RXOVERRUN) {
  244. port->icount.overrun++;
  245. } else if (status & MCFUART_USR_RXFRAMING) {
  246. port->icount.frame++;
  247. }
  248. status &= port->read_status_mask;
  249. if (status & MCFUART_USR_RXBREAK)
  250. flag = TTY_BREAK;
  251. else if (status & MCFUART_USR_RXPARITY)
  252. flag = TTY_PARITY;
  253. else if (status & MCFUART_USR_RXFRAMING)
  254. flag = TTY_FRAME;
  255. }
  256. if (uart_handle_sysrq_char(port, ch))
  257. continue;
  258. uart_insert_char(port, status, MCFUART_USR_RXOVERRUN, ch, flag);
  259. }
  260. spin_unlock(&port->lock);
  261. tty_flip_buffer_push(&port->state->port);
  262. spin_lock(&port->lock);
  263. }
  264. /****************************************************************************/
  265. static void mcf_tx_chars(struct mcf_uart *pp)
  266. {
  267. struct uart_port *port = &pp->port;
  268. struct circ_buf *xmit = &port->state->xmit;
  269. if (port->x_char) {
  270. /* Send special char - probably flow control */
  271. writeb(port->x_char, port->membase + MCFUART_UTB);
  272. port->x_char = 0;
  273. port->icount.tx++;
  274. return;
  275. }
  276. while (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY) {
  277. if (xmit->head == xmit->tail)
  278. break;
  279. writeb(xmit->buf[xmit->tail], port->membase + MCFUART_UTB);
  280. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1);
  281. port->icount.tx++;
  282. }
  283. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  284. uart_write_wakeup(port);
  285. if (xmit->head == xmit->tail) {
  286. pp->imr &= ~MCFUART_UIR_TXREADY;
  287. writeb(pp->imr, port->membase + MCFUART_UIMR);
  288. /* Disable TX to negate RTS automatically */
  289. if (port->rs485.flags & SER_RS485_ENABLED)
  290. writeb(MCFUART_UCR_TXDISABLE,
  291. port->membase + MCFUART_UCR);
  292. }
  293. }
  294. /****************************************************************************/
  295. static irqreturn_t mcf_interrupt(int irq, void *data)
  296. {
  297. struct uart_port *port = data;
  298. struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
  299. unsigned int isr;
  300. irqreturn_t ret = IRQ_NONE;
  301. isr = readb(port->membase + MCFUART_UISR) & pp->imr;
  302. spin_lock(&port->lock);
  303. if (isr & MCFUART_UIR_RXREADY) {
  304. mcf_rx_chars(pp);
  305. ret = IRQ_HANDLED;
  306. }
  307. if (isr & MCFUART_UIR_TXREADY) {
  308. mcf_tx_chars(pp);
  309. ret = IRQ_HANDLED;
  310. }
  311. spin_unlock(&port->lock);
  312. return ret;
  313. }
  314. /****************************************************************************/
  315. static void mcf_config_port(struct uart_port *port, int flags)
  316. {
  317. port->type = PORT_MCF;
  318. port->fifosize = MCFUART_TXFIFOSIZE;
  319. /* Clear mask, so no surprise interrupts. */
  320. writeb(0, port->membase + MCFUART_UIMR);
  321. if (request_irq(port->irq, mcf_interrupt, 0, "UART", port))
  322. printk(KERN_ERR "MCF: unable to attach ColdFire UART %d "
  323. "interrupt vector=%d\n", port->line, port->irq);
  324. }
  325. /****************************************************************************/
  326. static const char *mcf_type(struct uart_port *port)
  327. {
  328. return (port->type == PORT_MCF) ? "ColdFire UART" : NULL;
  329. }
  330. /****************************************************************************/
  331. static int mcf_request_port(struct uart_port *port)
  332. {
  333. /* UARTs always present */
  334. return 0;
  335. }
  336. /****************************************************************************/
  337. static void mcf_release_port(struct uart_port *port)
  338. {
  339. /* Nothing to release... */
  340. }
  341. /****************************************************************************/
  342. static int mcf_verify_port(struct uart_port *port, struct serial_struct *ser)
  343. {
  344. if ((ser->type != PORT_UNKNOWN) && (ser->type != PORT_MCF))
  345. return -EINVAL;
  346. return 0;
  347. }
  348. /****************************************************************************/
  349. /* Enable or disable the RS485 support */
  350. static int mcf_config_rs485(struct uart_port *port, struct serial_rs485 *rs485)
  351. {
  352. unsigned char mr1, mr2;
  353. /* Get mode registers */
  354. mr1 = readb(port->membase + MCFUART_UMR);
  355. mr2 = readb(port->membase + MCFUART_UMR);
  356. if (rs485->flags & SER_RS485_ENABLED) {
  357. dev_dbg(port->dev, "Setting UART to RS485\n");
  358. /* Automatically negate RTS after TX completes */
  359. mr2 |= MCFUART_MR2_TXRTS;
  360. } else {
  361. dev_dbg(port->dev, "Setting UART to RS232\n");
  362. mr2 &= ~MCFUART_MR2_TXRTS;
  363. }
  364. writeb(mr1, port->membase + MCFUART_UMR);
  365. writeb(mr2, port->membase + MCFUART_UMR);
  366. port->rs485 = *rs485;
  367. return 0;
  368. }
  369. /****************************************************************************/
  370. /*
  371. * Define the basic serial functions we support.
  372. */
  373. static const struct uart_ops mcf_uart_ops = {
  374. .tx_empty = mcf_tx_empty,
  375. .get_mctrl = mcf_get_mctrl,
  376. .set_mctrl = mcf_set_mctrl,
  377. .start_tx = mcf_start_tx,
  378. .stop_tx = mcf_stop_tx,
  379. .stop_rx = mcf_stop_rx,
  380. .break_ctl = mcf_break_ctl,
  381. .startup = mcf_startup,
  382. .shutdown = mcf_shutdown,
  383. .set_termios = mcf_set_termios,
  384. .type = mcf_type,
  385. .request_port = mcf_request_port,
  386. .release_port = mcf_release_port,
  387. .config_port = mcf_config_port,
  388. .verify_port = mcf_verify_port,
  389. };
  390. static struct mcf_uart mcf_ports[4];
  391. #define MCF_MAXPORTS ARRAY_SIZE(mcf_ports)
  392. /****************************************************************************/
  393. #if defined(CONFIG_SERIAL_MCF_CONSOLE)
  394. /****************************************************************************/
  395. int __init early_mcf_setup(struct mcf_platform_uart *platp)
  396. {
  397. struct uart_port *port;
  398. int i;
  399. for (i = 0; ((i < MCF_MAXPORTS) && (platp[i].mapbase)); i++) {
  400. port = &mcf_ports[i].port;
  401. port->line = i;
  402. port->type = PORT_MCF;
  403. port->mapbase = platp[i].mapbase;
  404. port->membase = (platp[i].membase) ? platp[i].membase :
  405. (unsigned char __iomem *) port->mapbase;
  406. port->iotype = SERIAL_IO_MEM;
  407. port->irq = platp[i].irq;
  408. port->uartclk = MCF_BUSCLK;
  409. port->flags = UPF_BOOT_AUTOCONF;
  410. port->rs485_config = mcf_config_rs485;
  411. port->ops = &mcf_uart_ops;
  412. }
  413. return 0;
  414. }
  415. /****************************************************************************/
  416. static void mcf_console_putc(struct console *co, const char c)
  417. {
  418. struct uart_port *port = &(mcf_ports + co->index)->port;
  419. int i;
  420. for (i = 0; (i < 0x10000); i++) {
  421. if (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY)
  422. break;
  423. }
  424. writeb(c, port->membase + MCFUART_UTB);
  425. for (i = 0; (i < 0x10000); i++) {
  426. if (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY)
  427. break;
  428. }
  429. }
  430. /****************************************************************************/
  431. static void mcf_console_write(struct console *co, const char *s, unsigned int count)
  432. {
  433. for (; (count); count--, s++) {
  434. mcf_console_putc(co, *s);
  435. if (*s == '\n')
  436. mcf_console_putc(co, '\r');
  437. }
  438. }
  439. /****************************************************************************/
  440. static int __init mcf_console_setup(struct console *co, char *options)
  441. {
  442. struct uart_port *port;
  443. int baud = CONFIG_SERIAL_MCF_BAUDRATE;
  444. int bits = 8;
  445. int parity = 'n';
  446. int flow = 'n';
  447. if ((co->index < 0) || (co->index >= MCF_MAXPORTS))
  448. co->index = 0;
  449. port = &mcf_ports[co->index].port;
  450. if (port->membase == 0)
  451. return -ENODEV;
  452. if (options)
  453. uart_parse_options(options, &baud, &parity, &bits, &flow);
  454. return uart_set_options(port, co, baud, parity, bits, flow);
  455. }
  456. /****************************************************************************/
  457. static struct uart_driver mcf_driver;
  458. static struct console mcf_console = {
  459. .name = "ttyS",
  460. .write = mcf_console_write,
  461. .device = uart_console_device,
  462. .setup = mcf_console_setup,
  463. .flags = CON_PRINTBUFFER,
  464. .index = -1,
  465. .data = &mcf_driver,
  466. };
  467. static int __init mcf_console_init(void)
  468. {
  469. register_console(&mcf_console);
  470. return 0;
  471. }
  472. console_initcall(mcf_console_init);
  473. #define MCF_CONSOLE &mcf_console
  474. /****************************************************************************/
  475. #else
  476. /****************************************************************************/
  477. #define MCF_CONSOLE NULL
  478. /****************************************************************************/
  479. #endif /* CONFIG_SERIAL_MCF_CONSOLE */
  480. /****************************************************************************/
  481. /*
  482. * Define the mcf UART driver structure.
  483. */
  484. static struct uart_driver mcf_driver = {
  485. .owner = THIS_MODULE,
  486. .driver_name = "mcf",
  487. .dev_name = "ttyS",
  488. .major = TTY_MAJOR,
  489. .minor = 64,
  490. .nr = MCF_MAXPORTS,
  491. .cons = MCF_CONSOLE,
  492. };
  493. /****************************************************************************/
  494. static int mcf_probe(struct platform_device *pdev)
  495. {
  496. struct mcf_platform_uart *platp = dev_get_platdata(&pdev->dev);
  497. struct uart_port *port;
  498. int i;
  499. for (i = 0; ((i < MCF_MAXPORTS) && (platp[i].mapbase)); i++) {
  500. port = &mcf_ports[i].port;
  501. port->line = i;
  502. port->type = PORT_MCF;
  503. port->mapbase = platp[i].mapbase;
  504. port->membase = (platp[i].membase) ? platp[i].membase :
  505. (unsigned char __iomem *) platp[i].mapbase;
  506. port->dev = &pdev->dev;
  507. port->iotype = SERIAL_IO_MEM;
  508. port->irq = platp[i].irq;
  509. port->uartclk = MCF_BUSCLK;
  510. port->ops = &mcf_uart_ops;
  511. port->flags = UPF_BOOT_AUTOCONF;
  512. port->rs485_config = mcf_config_rs485;
  513. uart_add_one_port(&mcf_driver, port);
  514. }
  515. return 0;
  516. }
  517. /****************************************************************************/
  518. static int mcf_remove(struct platform_device *pdev)
  519. {
  520. struct uart_port *port;
  521. int i;
  522. for (i = 0; (i < MCF_MAXPORTS); i++) {
  523. port = &mcf_ports[i].port;
  524. if (port)
  525. uart_remove_one_port(&mcf_driver, port);
  526. }
  527. return 0;
  528. }
  529. /****************************************************************************/
  530. static struct platform_driver mcf_platform_driver = {
  531. .probe = mcf_probe,
  532. .remove = mcf_remove,
  533. .driver = {
  534. .name = "mcfuart",
  535. },
  536. };
  537. /****************************************************************************/
  538. static int __init mcf_init(void)
  539. {
  540. int rc;
  541. printk("ColdFire internal UART serial driver\n");
  542. rc = uart_register_driver(&mcf_driver);
  543. if (rc)
  544. return rc;
  545. rc = platform_driver_register(&mcf_platform_driver);
  546. if (rc) {
  547. uart_unregister_driver(&mcf_driver);
  548. return rc;
  549. }
  550. return 0;
  551. }
  552. /****************************************************************************/
  553. static void __exit mcf_exit(void)
  554. {
  555. platform_driver_unregister(&mcf_platform_driver);
  556. uart_unregister_driver(&mcf_driver);
  557. }
  558. /****************************************************************************/
  559. module_init(mcf_init);
  560. module_exit(mcf_exit);
  561. MODULE_AUTHOR("Greg Ungerer <gerg@uclinux.org>");
  562. MODULE_DESCRIPTION("Freescale ColdFire UART driver");
  563. MODULE_LICENSE("GPL");
  564. MODULE_ALIAS("platform:mcfuart");
  565. /****************************************************************************/