max3100.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. *
  4. * Copyright (C) 2008 Christian Pellegrin <chripell@evolware.org>
  5. *
  6. * Notes: the MAX3100 doesn't provide an interrupt on CTS so we have
  7. * to use polling for flow control. TX empty IRQ is unusable, since
  8. * writing conf clears FIFO buffer and we cannot have this interrupt
  9. * always asking us for attention.
  10. *
  11. * Example platform data:
  12. static struct plat_max3100 max3100_plat_data = {
  13. .loopback = 0,
  14. .crystal = 0,
  15. .poll_time = 100,
  16. };
  17. static struct spi_board_info spi_board_info[] = {
  18. {
  19. .modalias = "max3100",
  20. .platform_data = &max3100_plat_data,
  21. .irq = IRQ_EINT12,
  22. .max_speed_hz = 5*1000*1000,
  23. .chip_select = 0,
  24. },
  25. };
  26. * The initial minor number is 209 in the low-density serial port:
  27. * mknod /dev/ttyMAX0 c 204 209
  28. */
  29. #define MAX3100_MAJOR 204
  30. #define MAX3100_MINOR 209
  31. /* 4 MAX3100s should be enough for everyone */
  32. #define MAX_MAX3100 4
  33. #include <linux/delay.h>
  34. #include <linux/slab.h>
  35. #include <linux/device.h>
  36. #include <linux/module.h>
  37. #include <linux/serial_core.h>
  38. #include <linux/serial.h>
  39. #include <linux/spi/spi.h>
  40. #include <linux/freezer.h>
  41. #include <linux/tty.h>
  42. #include <linux/tty_flip.h>
  43. #include <linux/serial_max3100.h>
  44. #define MAX3100_C (1<<14)
  45. #define MAX3100_D (0<<14)
  46. #define MAX3100_W (1<<15)
  47. #define MAX3100_RX (0<<15)
  48. #define MAX3100_WC (MAX3100_W | MAX3100_C)
  49. #define MAX3100_RC (MAX3100_RX | MAX3100_C)
  50. #define MAX3100_WD (MAX3100_W | MAX3100_D)
  51. #define MAX3100_RD (MAX3100_RX | MAX3100_D)
  52. #define MAX3100_CMD (3 << 14)
  53. #define MAX3100_T (1<<14)
  54. #define MAX3100_R (1<<15)
  55. #define MAX3100_FEN (1<<13)
  56. #define MAX3100_SHDN (1<<12)
  57. #define MAX3100_TM (1<<11)
  58. #define MAX3100_RM (1<<10)
  59. #define MAX3100_PM (1<<9)
  60. #define MAX3100_RAM (1<<8)
  61. #define MAX3100_IR (1<<7)
  62. #define MAX3100_ST (1<<6)
  63. #define MAX3100_PE (1<<5)
  64. #define MAX3100_L (1<<4)
  65. #define MAX3100_BAUD (0xf)
  66. #define MAX3100_TE (1<<10)
  67. #define MAX3100_RAFE (1<<10)
  68. #define MAX3100_RTS (1<<9)
  69. #define MAX3100_CTS (1<<9)
  70. #define MAX3100_PT (1<<8)
  71. #define MAX3100_DATA (0xff)
  72. #define MAX3100_RT (MAX3100_R | MAX3100_T)
  73. #define MAX3100_RTC (MAX3100_RT | MAX3100_CTS | MAX3100_RAFE)
  74. /* the following simulate a status reg for ignore_status_mask */
  75. #define MAX3100_STATUS_PE 1
  76. #define MAX3100_STATUS_FE 2
  77. #define MAX3100_STATUS_OE 4
  78. struct max3100_port {
  79. struct uart_port port;
  80. struct spi_device *spi;
  81. int cts; /* last CTS received for flow ctrl */
  82. int tx_empty; /* last TX empty bit */
  83. spinlock_t conf_lock; /* shared data */
  84. int conf_commit; /* need to make changes */
  85. int conf; /* configuration for the MAX31000
  86. * (bits 0-7, bits 8-11 are irqs) */
  87. int rts_commit; /* need to change rts */
  88. int rts; /* rts status */
  89. int baud; /* current baud rate */
  90. int parity; /* keeps track if we should send parity */
  91. #define MAX3100_PARITY_ON 1
  92. #define MAX3100_PARITY_ODD 2
  93. #define MAX3100_7BIT 4
  94. int rx_enabled; /* if we should rx chars */
  95. int irq; /* irq assigned to the max3100 */
  96. int minor; /* minor number */
  97. int crystal; /* 1 if 3.6864Mhz crystal 0 for 1.8432 */
  98. int loopback; /* 1 if we are in loopback mode */
  99. /* for handling irqs: need workqueue since we do spi_sync */
  100. struct workqueue_struct *workqueue;
  101. struct work_struct work;
  102. /* set to 1 to make the workhandler exit as soon as possible */
  103. int force_end_work;
  104. /* need to know we are suspending to avoid deadlock on workqueue */
  105. int suspending;
  106. /* hook for suspending MAX3100 via dedicated pin */
  107. void (*max3100_hw_suspend) (int suspend);
  108. /* poll time (in ms) for ctrl lines */
  109. int poll_time;
  110. /* and its timer */
  111. struct timer_list timer;
  112. };
  113. static struct max3100_port *max3100s[MAX_MAX3100]; /* the chips */
  114. static DEFINE_MUTEX(max3100s_lock); /* race on probe */
  115. static int max3100_do_parity(struct max3100_port *s, u16 c)
  116. {
  117. int parity;
  118. if (s->parity & MAX3100_PARITY_ODD)
  119. parity = 1;
  120. else
  121. parity = 0;
  122. if (s->parity & MAX3100_7BIT)
  123. c &= 0x7f;
  124. else
  125. c &= 0xff;
  126. parity = parity ^ (hweight8(c) & 1);
  127. return parity;
  128. }
  129. static int max3100_check_parity(struct max3100_port *s, u16 c)
  130. {
  131. return max3100_do_parity(s, c) == ((c >> 8) & 1);
  132. }
  133. static void max3100_calc_parity(struct max3100_port *s, u16 *c)
  134. {
  135. if (s->parity & MAX3100_7BIT)
  136. *c &= 0x7f;
  137. else
  138. *c &= 0xff;
  139. if (s->parity & MAX3100_PARITY_ON)
  140. *c |= max3100_do_parity(s, *c) << 8;
  141. }
  142. static void max3100_work(struct work_struct *w);
  143. static void max3100_dowork(struct max3100_port *s)
  144. {
  145. if (!s->force_end_work && !freezing(current) && !s->suspending)
  146. queue_work(s->workqueue, &s->work);
  147. }
  148. static void max3100_timeout(struct timer_list *t)
  149. {
  150. struct max3100_port *s = from_timer(s, t, timer);
  151. if (s->port.state) {
  152. max3100_dowork(s);
  153. mod_timer(&s->timer, jiffies + s->poll_time);
  154. }
  155. }
  156. static int max3100_sr(struct max3100_port *s, u16 tx, u16 *rx)
  157. {
  158. struct spi_message message;
  159. u16 etx, erx;
  160. int status;
  161. struct spi_transfer tran = {
  162. .tx_buf = &etx,
  163. .rx_buf = &erx,
  164. .len = 2,
  165. };
  166. etx = cpu_to_be16(tx);
  167. spi_message_init(&message);
  168. spi_message_add_tail(&tran, &message);
  169. status = spi_sync(s->spi, &message);
  170. if (status) {
  171. dev_warn(&s->spi->dev, "error while calling spi_sync\n");
  172. return -EIO;
  173. }
  174. *rx = be16_to_cpu(erx);
  175. s->tx_empty = (*rx & MAX3100_T) > 0;
  176. dev_dbg(&s->spi->dev, "%04x - %04x\n", tx, *rx);
  177. return 0;
  178. }
  179. static int max3100_handlerx(struct max3100_port *s, u16 rx)
  180. {
  181. unsigned int ch, flg, status = 0;
  182. int ret = 0, cts;
  183. if (rx & MAX3100_R && s->rx_enabled) {
  184. dev_dbg(&s->spi->dev, "%s\n", __func__);
  185. ch = rx & (s->parity & MAX3100_7BIT ? 0x7f : 0xff);
  186. if (rx & MAX3100_RAFE) {
  187. s->port.icount.frame++;
  188. flg = TTY_FRAME;
  189. status |= MAX3100_STATUS_FE;
  190. } else {
  191. if (s->parity & MAX3100_PARITY_ON) {
  192. if (max3100_check_parity(s, rx)) {
  193. s->port.icount.rx++;
  194. flg = TTY_NORMAL;
  195. } else {
  196. s->port.icount.parity++;
  197. flg = TTY_PARITY;
  198. status |= MAX3100_STATUS_PE;
  199. }
  200. } else {
  201. s->port.icount.rx++;
  202. flg = TTY_NORMAL;
  203. }
  204. }
  205. uart_insert_char(&s->port, status, MAX3100_STATUS_OE, ch, flg);
  206. ret = 1;
  207. }
  208. cts = (rx & MAX3100_CTS) > 0;
  209. if (s->cts != cts) {
  210. s->cts = cts;
  211. uart_handle_cts_change(&s->port, cts ? TIOCM_CTS : 0);
  212. }
  213. return ret;
  214. }
  215. static void max3100_work(struct work_struct *w)
  216. {
  217. struct max3100_port *s = container_of(w, struct max3100_port, work);
  218. int rxchars;
  219. u16 tx, rx;
  220. int conf, cconf, crts;
  221. struct circ_buf *xmit = &s->port.state->xmit;
  222. dev_dbg(&s->spi->dev, "%s\n", __func__);
  223. rxchars = 0;
  224. do {
  225. spin_lock(&s->conf_lock);
  226. conf = s->conf;
  227. cconf = s->conf_commit;
  228. s->conf_commit = 0;
  229. crts = s->rts_commit;
  230. s->rts_commit = 0;
  231. spin_unlock(&s->conf_lock);
  232. if (cconf)
  233. max3100_sr(s, MAX3100_WC | conf, &rx);
  234. if (crts) {
  235. max3100_sr(s, MAX3100_WD | MAX3100_TE |
  236. (s->rts ? MAX3100_RTS : 0), &rx);
  237. rxchars += max3100_handlerx(s, rx);
  238. }
  239. max3100_sr(s, MAX3100_RD, &rx);
  240. rxchars += max3100_handlerx(s, rx);
  241. if (rx & MAX3100_T) {
  242. tx = 0xffff;
  243. if (s->port.x_char) {
  244. tx = s->port.x_char;
  245. s->port.icount.tx++;
  246. s->port.x_char = 0;
  247. } else if (!uart_circ_empty(xmit) &&
  248. !uart_tx_stopped(&s->port)) {
  249. tx = xmit->buf[xmit->tail];
  250. xmit->tail = (xmit->tail + 1) &
  251. (UART_XMIT_SIZE - 1);
  252. s->port.icount.tx++;
  253. }
  254. if (tx != 0xffff) {
  255. max3100_calc_parity(s, &tx);
  256. tx |= MAX3100_WD | (s->rts ? MAX3100_RTS : 0);
  257. max3100_sr(s, tx, &rx);
  258. rxchars += max3100_handlerx(s, rx);
  259. }
  260. }
  261. if (rxchars > 16) {
  262. tty_flip_buffer_push(&s->port.state->port);
  263. rxchars = 0;
  264. }
  265. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  266. uart_write_wakeup(&s->port);
  267. } while (!s->force_end_work &&
  268. !freezing(current) &&
  269. ((rx & MAX3100_R) ||
  270. (!uart_circ_empty(xmit) &&
  271. !uart_tx_stopped(&s->port))));
  272. if (rxchars > 0)
  273. tty_flip_buffer_push(&s->port.state->port);
  274. }
  275. static irqreturn_t max3100_irq(int irqno, void *dev_id)
  276. {
  277. struct max3100_port *s = dev_id;
  278. dev_dbg(&s->spi->dev, "%s\n", __func__);
  279. max3100_dowork(s);
  280. return IRQ_HANDLED;
  281. }
  282. static void max3100_enable_ms(struct uart_port *port)
  283. {
  284. struct max3100_port *s = container_of(port,
  285. struct max3100_port,
  286. port);
  287. if (s->poll_time > 0)
  288. mod_timer(&s->timer, jiffies);
  289. dev_dbg(&s->spi->dev, "%s\n", __func__);
  290. }
  291. static void max3100_start_tx(struct uart_port *port)
  292. {
  293. struct max3100_port *s = container_of(port,
  294. struct max3100_port,
  295. port);
  296. dev_dbg(&s->spi->dev, "%s\n", __func__);
  297. max3100_dowork(s);
  298. }
  299. static void max3100_stop_rx(struct uart_port *port)
  300. {
  301. struct max3100_port *s = container_of(port,
  302. struct max3100_port,
  303. port);
  304. dev_dbg(&s->spi->dev, "%s\n", __func__);
  305. s->rx_enabled = 0;
  306. spin_lock(&s->conf_lock);
  307. s->conf &= ~MAX3100_RM;
  308. s->conf_commit = 1;
  309. spin_unlock(&s->conf_lock);
  310. max3100_dowork(s);
  311. }
  312. static unsigned int max3100_tx_empty(struct uart_port *port)
  313. {
  314. struct max3100_port *s = container_of(port,
  315. struct max3100_port,
  316. port);
  317. dev_dbg(&s->spi->dev, "%s\n", __func__);
  318. /* may not be truly up-to-date */
  319. max3100_dowork(s);
  320. return s->tx_empty;
  321. }
  322. static unsigned int max3100_get_mctrl(struct uart_port *port)
  323. {
  324. struct max3100_port *s = container_of(port,
  325. struct max3100_port,
  326. port);
  327. dev_dbg(&s->spi->dev, "%s\n", __func__);
  328. /* may not be truly up-to-date */
  329. max3100_dowork(s);
  330. /* always assert DCD and DSR since these lines are not wired */
  331. return (s->cts ? TIOCM_CTS : 0) | TIOCM_DSR | TIOCM_CAR;
  332. }
  333. static void max3100_set_mctrl(struct uart_port *port, unsigned int mctrl)
  334. {
  335. struct max3100_port *s = container_of(port,
  336. struct max3100_port,
  337. port);
  338. int rts;
  339. dev_dbg(&s->spi->dev, "%s\n", __func__);
  340. rts = (mctrl & TIOCM_RTS) > 0;
  341. spin_lock(&s->conf_lock);
  342. if (s->rts != rts) {
  343. s->rts = rts;
  344. s->rts_commit = 1;
  345. max3100_dowork(s);
  346. }
  347. spin_unlock(&s->conf_lock);
  348. }
  349. static void
  350. max3100_set_termios(struct uart_port *port, struct ktermios *termios,
  351. struct ktermios *old)
  352. {
  353. struct max3100_port *s = container_of(port,
  354. struct max3100_port,
  355. port);
  356. int baud = 0;
  357. unsigned cflag;
  358. u32 param_new, param_mask, parity = 0;
  359. dev_dbg(&s->spi->dev, "%s\n", __func__);
  360. cflag = termios->c_cflag;
  361. param_mask = 0;
  362. baud = tty_termios_baud_rate(termios);
  363. param_new = s->conf & MAX3100_BAUD;
  364. switch (baud) {
  365. case 300:
  366. if (s->crystal)
  367. baud = s->baud;
  368. else
  369. param_new = 15;
  370. break;
  371. case 600:
  372. param_new = 14 + s->crystal;
  373. break;
  374. case 1200:
  375. param_new = 13 + s->crystal;
  376. break;
  377. case 2400:
  378. param_new = 12 + s->crystal;
  379. break;
  380. case 4800:
  381. param_new = 11 + s->crystal;
  382. break;
  383. case 9600:
  384. param_new = 10 + s->crystal;
  385. break;
  386. case 19200:
  387. param_new = 9 + s->crystal;
  388. break;
  389. case 38400:
  390. param_new = 8 + s->crystal;
  391. break;
  392. case 57600:
  393. param_new = 1 + s->crystal;
  394. break;
  395. case 115200:
  396. param_new = 0 + s->crystal;
  397. break;
  398. case 230400:
  399. if (s->crystal)
  400. param_new = 0;
  401. else
  402. baud = s->baud;
  403. break;
  404. default:
  405. baud = s->baud;
  406. }
  407. tty_termios_encode_baud_rate(termios, baud, baud);
  408. s->baud = baud;
  409. param_mask |= MAX3100_BAUD;
  410. if ((cflag & CSIZE) == CS8) {
  411. param_new &= ~MAX3100_L;
  412. parity &= ~MAX3100_7BIT;
  413. } else {
  414. param_new |= MAX3100_L;
  415. parity |= MAX3100_7BIT;
  416. cflag = (cflag & ~CSIZE) | CS7;
  417. }
  418. param_mask |= MAX3100_L;
  419. if (cflag & CSTOPB)
  420. param_new |= MAX3100_ST;
  421. else
  422. param_new &= ~MAX3100_ST;
  423. param_mask |= MAX3100_ST;
  424. if (cflag & PARENB) {
  425. param_new |= MAX3100_PE;
  426. parity |= MAX3100_PARITY_ON;
  427. } else {
  428. param_new &= ~MAX3100_PE;
  429. parity &= ~MAX3100_PARITY_ON;
  430. }
  431. param_mask |= MAX3100_PE;
  432. if (cflag & PARODD)
  433. parity |= MAX3100_PARITY_ODD;
  434. else
  435. parity &= ~MAX3100_PARITY_ODD;
  436. /* mask termios capabilities we don't support */
  437. cflag &= ~CMSPAR;
  438. termios->c_cflag = cflag;
  439. s->port.ignore_status_mask = 0;
  440. if (termios->c_iflag & IGNPAR)
  441. s->port.ignore_status_mask |=
  442. MAX3100_STATUS_PE | MAX3100_STATUS_FE |
  443. MAX3100_STATUS_OE;
  444. /* we are sending char from a workqueue so enable */
  445. s->port.state->port.low_latency = 1;
  446. if (s->poll_time > 0)
  447. del_timer_sync(&s->timer);
  448. uart_update_timeout(port, termios->c_cflag, baud);
  449. spin_lock(&s->conf_lock);
  450. s->conf = (s->conf & ~param_mask) | (param_new & param_mask);
  451. s->conf_commit = 1;
  452. s->parity = parity;
  453. spin_unlock(&s->conf_lock);
  454. max3100_dowork(s);
  455. if (UART_ENABLE_MS(&s->port, termios->c_cflag))
  456. max3100_enable_ms(&s->port);
  457. }
  458. static void max3100_shutdown(struct uart_port *port)
  459. {
  460. struct max3100_port *s = container_of(port,
  461. struct max3100_port,
  462. port);
  463. dev_dbg(&s->spi->dev, "%s\n", __func__);
  464. if (s->suspending)
  465. return;
  466. s->force_end_work = 1;
  467. if (s->poll_time > 0)
  468. del_timer_sync(&s->timer);
  469. if (s->workqueue) {
  470. flush_workqueue(s->workqueue);
  471. destroy_workqueue(s->workqueue);
  472. s->workqueue = NULL;
  473. }
  474. if (s->irq)
  475. free_irq(s->irq, s);
  476. /* set shutdown mode to save power */
  477. if (s->max3100_hw_suspend)
  478. s->max3100_hw_suspend(1);
  479. else {
  480. u16 tx, rx;
  481. tx = MAX3100_WC | MAX3100_SHDN;
  482. max3100_sr(s, tx, &rx);
  483. }
  484. }
  485. static int max3100_startup(struct uart_port *port)
  486. {
  487. struct max3100_port *s = container_of(port,
  488. struct max3100_port,
  489. port);
  490. char b[12];
  491. dev_dbg(&s->spi->dev, "%s\n", __func__);
  492. s->conf = MAX3100_RM;
  493. s->baud = s->crystal ? 230400 : 115200;
  494. s->rx_enabled = 1;
  495. if (s->suspending)
  496. return 0;
  497. s->force_end_work = 0;
  498. s->parity = 0;
  499. s->rts = 0;
  500. sprintf(b, "max3100-%d", s->minor);
  501. s->workqueue = create_freezable_workqueue(b);
  502. if (!s->workqueue) {
  503. dev_warn(&s->spi->dev, "cannot create workqueue\n");
  504. return -EBUSY;
  505. }
  506. INIT_WORK(&s->work, max3100_work);
  507. if (request_irq(s->irq, max3100_irq,
  508. IRQF_TRIGGER_FALLING, "max3100", s) < 0) {
  509. dev_warn(&s->spi->dev, "cannot allocate irq %d\n", s->irq);
  510. s->irq = 0;
  511. destroy_workqueue(s->workqueue);
  512. s->workqueue = NULL;
  513. return -EBUSY;
  514. }
  515. if (s->loopback) {
  516. u16 tx, rx;
  517. tx = 0x4001;
  518. max3100_sr(s, tx, &rx);
  519. }
  520. if (s->max3100_hw_suspend)
  521. s->max3100_hw_suspend(0);
  522. s->conf_commit = 1;
  523. max3100_dowork(s);
  524. /* wait for clock to settle */
  525. msleep(50);
  526. max3100_enable_ms(&s->port);
  527. return 0;
  528. }
  529. static const char *max3100_type(struct uart_port *port)
  530. {
  531. struct max3100_port *s = container_of(port,
  532. struct max3100_port,
  533. port);
  534. dev_dbg(&s->spi->dev, "%s\n", __func__);
  535. return s->port.type == PORT_MAX3100 ? "MAX3100" : NULL;
  536. }
  537. static void max3100_release_port(struct uart_port *port)
  538. {
  539. struct max3100_port *s = container_of(port,
  540. struct max3100_port,
  541. port);
  542. dev_dbg(&s->spi->dev, "%s\n", __func__);
  543. }
  544. static void max3100_config_port(struct uart_port *port, int flags)
  545. {
  546. struct max3100_port *s = container_of(port,
  547. struct max3100_port,
  548. port);
  549. dev_dbg(&s->spi->dev, "%s\n", __func__);
  550. if (flags & UART_CONFIG_TYPE)
  551. s->port.type = PORT_MAX3100;
  552. }
  553. static int max3100_verify_port(struct uart_port *port,
  554. struct serial_struct *ser)
  555. {
  556. struct max3100_port *s = container_of(port,
  557. struct max3100_port,
  558. port);
  559. int ret = -EINVAL;
  560. dev_dbg(&s->spi->dev, "%s\n", __func__);
  561. if (ser->type == PORT_UNKNOWN || ser->type == PORT_MAX3100)
  562. ret = 0;
  563. return ret;
  564. }
  565. static void max3100_stop_tx(struct uart_port *port)
  566. {
  567. struct max3100_port *s = container_of(port,
  568. struct max3100_port,
  569. port);
  570. dev_dbg(&s->spi->dev, "%s\n", __func__);
  571. }
  572. static int max3100_request_port(struct uart_port *port)
  573. {
  574. struct max3100_port *s = container_of(port,
  575. struct max3100_port,
  576. port);
  577. dev_dbg(&s->spi->dev, "%s\n", __func__);
  578. return 0;
  579. }
  580. static void max3100_break_ctl(struct uart_port *port, int break_state)
  581. {
  582. struct max3100_port *s = container_of(port,
  583. struct max3100_port,
  584. port);
  585. dev_dbg(&s->spi->dev, "%s\n", __func__);
  586. }
  587. static const struct uart_ops max3100_ops = {
  588. .tx_empty = max3100_tx_empty,
  589. .set_mctrl = max3100_set_mctrl,
  590. .get_mctrl = max3100_get_mctrl,
  591. .stop_tx = max3100_stop_tx,
  592. .start_tx = max3100_start_tx,
  593. .stop_rx = max3100_stop_rx,
  594. .enable_ms = max3100_enable_ms,
  595. .break_ctl = max3100_break_ctl,
  596. .startup = max3100_startup,
  597. .shutdown = max3100_shutdown,
  598. .set_termios = max3100_set_termios,
  599. .type = max3100_type,
  600. .release_port = max3100_release_port,
  601. .request_port = max3100_request_port,
  602. .config_port = max3100_config_port,
  603. .verify_port = max3100_verify_port,
  604. };
  605. static struct uart_driver max3100_uart_driver = {
  606. .owner = THIS_MODULE,
  607. .driver_name = "ttyMAX",
  608. .dev_name = "ttyMAX",
  609. .major = MAX3100_MAJOR,
  610. .minor = MAX3100_MINOR,
  611. .nr = MAX_MAX3100,
  612. };
  613. static int uart_driver_registered;
  614. static int max3100_probe(struct spi_device *spi)
  615. {
  616. int i, retval;
  617. struct plat_max3100 *pdata;
  618. u16 tx, rx;
  619. mutex_lock(&max3100s_lock);
  620. if (!uart_driver_registered) {
  621. uart_driver_registered = 1;
  622. retval = uart_register_driver(&max3100_uart_driver);
  623. if (retval) {
  624. printk(KERN_ERR "Couldn't register max3100 uart driver\n");
  625. mutex_unlock(&max3100s_lock);
  626. return retval;
  627. }
  628. }
  629. for (i = 0; i < MAX_MAX3100; i++)
  630. if (!max3100s[i])
  631. break;
  632. if (i == MAX_MAX3100) {
  633. dev_warn(&spi->dev, "too many MAX3100 chips\n");
  634. mutex_unlock(&max3100s_lock);
  635. return -ENOMEM;
  636. }
  637. max3100s[i] = kzalloc(sizeof(struct max3100_port), GFP_KERNEL);
  638. if (!max3100s[i]) {
  639. dev_warn(&spi->dev,
  640. "kmalloc for max3100 structure %d failed!\n", i);
  641. mutex_unlock(&max3100s_lock);
  642. return -ENOMEM;
  643. }
  644. max3100s[i]->spi = spi;
  645. max3100s[i]->irq = spi->irq;
  646. spin_lock_init(&max3100s[i]->conf_lock);
  647. spi_set_drvdata(spi, max3100s[i]);
  648. pdata = dev_get_platdata(&spi->dev);
  649. max3100s[i]->crystal = pdata->crystal;
  650. max3100s[i]->loopback = pdata->loopback;
  651. max3100s[i]->poll_time = msecs_to_jiffies(pdata->poll_time);
  652. if (pdata->poll_time > 0 && max3100s[i]->poll_time == 0)
  653. max3100s[i]->poll_time = 1;
  654. max3100s[i]->max3100_hw_suspend = pdata->max3100_hw_suspend;
  655. max3100s[i]->minor = i;
  656. timer_setup(&max3100s[i]->timer, max3100_timeout, 0);
  657. dev_dbg(&spi->dev, "%s: adding port %d\n", __func__, i);
  658. max3100s[i]->port.irq = max3100s[i]->irq;
  659. max3100s[i]->port.uartclk = max3100s[i]->crystal ? 3686400 : 1843200;
  660. max3100s[i]->port.fifosize = 16;
  661. max3100s[i]->port.ops = &max3100_ops;
  662. max3100s[i]->port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF;
  663. max3100s[i]->port.line = i;
  664. max3100s[i]->port.type = PORT_MAX3100;
  665. max3100s[i]->port.dev = &spi->dev;
  666. retval = uart_add_one_port(&max3100_uart_driver, &max3100s[i]->port);
  667. if (retval < 0)
  668. dev_warn(&spi->dev,
  669. "uart_add_one_port failed for line %d with error %d\n",
  670. i, retval);
  671. /* set shutdown mode to save power. Will be woken-up on open */
  672. if (max3100s[i]->max3100_hw_suspend)
  673. max3100s[i]->max3100_hw_suspend(1);
  674. else {
  675. tx = MAX3100_WC | MAX3100_SHDN;
  676. max3100_sr(max3100s[i], tx, &rx);
  677. }
  678. mutex_unlock(&max3100s_lock);
  679. return 0;
  680. }
  681. static int max3100_remove(struct spi_device *spi)
  682. {
  683. struct max3100_port *s = spi_get_drvdata(spi);
  684. int i;
  685. mutex_lock(&max3100s_lock);
  686. /* find out the index for the chip we are removing */
  687. for (i = 0; i < MAX_MAX3100; i++)
  688. if (max3100s[i] == s) {
  689. dev_dbg(&spi->dev, "%s: removing port %d\n", __func__, i);
  690. uart_remove_one_port(&max3100_uart_driver, &max3100s[i]->port);
  691. kfree(max3100s[i]);
  692. max3100s[i] = NULL;
  693. break;
  694. }
  695. WARN_ON(i == MAX_MAX3100);
  696. /* check if this is the last chip we have */
  697. for (i = 0; i < MAX_MAX3100; i++)
  698. if (max3100s[i]) {
  699. mutex_unlock(&max3100s_lock);
  700. return 0;
  701. }
  702. pr_debug("removing max3100 driver\n");
  703. uart_unregister_driver(&max3100_uart_driver);
  704. mutex_unlock(&max3100s_lock);
  705. return 0;
  706. }
  707. #ifdef CONFIG_PM_SLEEP
  708. static int max3100_suspend(struct device *dev)
  709. {
  710. struct max3100_port *s = dev_get_drvdata(dev);
  711. dev_dbg(&s->spi->dev, "%s\n", __func__);
  712. disable_irq(s->irq);
  713. s->suspending = 1;
  714. uart_suspend_port(&max3100_uart_driver, &s->port);
  715. if (s->max3100_hw_suspend)
  716. s->max3100_hw_suspend(1);
  717. else {
  718. /* no HW suspend, so do SW one */
  719. u16 tx, rx;
  720. tx = MAX3100_WC | MAX3100_SHDN;
  721. max3100_sr(s, tx, &rx);
  722. }
  723. return 0;
  724. }
  725. static int max3100_resume(struct device *dev)
  726. {
  727. struct max3100_port *s = dev_get_drvdata(dev);
  728. dev_dbg(&s->spi->dev, "%s\n", __func__);
  729. if (s->max3100_hw_suspend)
  730. s->max3100_hw_suspend(0);
  731. uart_resume_port(&max3100_uart_driver, &s->port);
  732. s->suspending = 0;
  733. enable_irq(s->irq);
  734. s->conf_commit = 1;
  735. if (s->workqueue)
  736. max3100_dowork(s);
  737. return 0;
  738. }
  739. static SIMPLE_DEV_PM_OPS(max3100_pm_ops, max3100_suspend, max3100_resume);
  740. #define MAX3100_PM_OPS (&max3100_pm_ops)
  741. #else
  742. #define MAX3100_PM_OPS NULL
  743. #endif
  744. static struct spi_driver max3100_driver = {
  745. .driver = {
  746. .name = "max3100",
  747. .pm = MAX3100_PM_OPS,
  748. },
  749. .probe = max3100_probe,
  750. .remove = max3100_remove,
  751. };
  752. module_spi_driver(max3100_driver);
  753. MODULE_DESCRIPTION("MAX3100 driver");
  754. MODULE_AUTHOR("Christian Pellegrin <chripell@evolware.org>");
  755. MODULE_LICENSE("GPL");
  756. MODULE_ALIAS("spi:max3100");