jsm.h 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /************************************************************************
  3. * Copyright 2003 Digi International (www.digi.com)
  4. *
  5. * Copyright (C) 2004 IBM Corporation. All rights reserved.
  6. *
  7. * Contact Information:
  8. * Scott H Kilau <Scott_Kilau@digi.com>
  9. * Wendy Xiong <wendyx@us.ibm.com>
  10. *
  11. ***********************************************************************/
  12. #ifndef __JSM_DRIVER_H
  13. #define __JSM_DRIVER_H
  14. #include <linux/kernel.h>
  15. #include <linux/types.h> /* To pick up the varions Linux types */
  16. #include <linux/tty.h>
  17. #include <linux/serial_core.h>
  18. #include <linux/device.h>
  19. /*
  20. * Debugging levels can be set using debug insmod variable
  21. * They can also be compiled out completely.
  22. */
  23. enum {
  24. DBG_INIT = 0x01,
  25. DBG_BASIC = 0x02,
  26. DBG_CORE = 0x04,
  27. DBG_OPEN = 0x08,
  28. DBG_CLOSE = 0x10,
  29. DBG_READ = 0x20,
  30. DBG_WRITE = 0x40,
  31. DBG_IOCTL = 0x80,
  32. DBG_PROC = 0x100,
  33. DBG_PARAM = 0x200,
  34. DBG_PSCAN = 0x400,
  35. DBG_EVENT = 0x800,
  36. DBG_DRAIN = 0x1000,
  37. DBG_MSIGS = 0x2000,
  38. DBG_MGMT = 0x4000,
  39. DBG_INTR = 0x8000,
  40. DBG_CARR = 0x10000,
  41. };
  42. #define jsm_dbg(nlevel, pdev, fmt, ...) \
  43. do { \
  44. if (DBG_##nlevel & jsm_debug) \
  45. dev_dbg(pdev->dev, fmt, ##__VA_ARGS__); \
  46. } while (0)
  47. #define MAXLINES 256
  48. #define MAXPORTS 8
  49. #define MAX_STOPS_SENT 5
  50. /* Board ids */
  51. #define PCI_DEVICE_ID_CLASSIC_4 0x0028
  52. #define PCI_DEVICE_ID_CLASSIC_8 0x0029
  53. #define PCI_DEVICE_ID_CLASSIC_4_422 0x00D0
  54. #define PCI_DEVICE_ID_CLASSIC_8_422 0x00D1
  55. #define PCI_DEVICE_ID_NEO_4 0x00B0
  56. #define PCI_DEVICE_ID_NEO_1_422 0x00CC
  57. #define PCI_DEVICE_ID_NEO_1_422_485 0x00CD
  58. #define PCI_DEVICE_ID_NEO_2_422_485 0x00CE
  59. #define PCIE_DEVICE_ID_NEO_8 0x00F0
  60. #define PCIE_DEVICE_ID_NEO_4 0x00F1
  61. #define PCIE_DEVICE_ID_NEO_4RJ45 0x00F2
  62. #define PCIE_DEVICE_ID_NEO_8RJ45 0x00F3
  63. /* Board type definitions */
  64. #define T_NEO 0000
  65. #define T_CLASSIC 0001
  66. #define T_PCIBUS 0400
  67. /* Board State Definitions */
  68. #define BD_RUNNING 0x0
  69. #define BD_REASON 0x7f
  70. #define BD_NOTFOUND 0x1
  71. #define BD_NOIOPORT 0x2
  72. #define BD_NOMEM 0x3
  73. #define BD_NOBIOS 0x4
  74. #define BD_NOFEP 0x5
  75. #define BD_FAILED 0x6
  76. #define BD_ALLOCATED 0x7
  77. #define BD_TRIBOOT 0x8
  78. #define BD_BADKME 0x80
  79. /* 4 extra for alignment play space */
  80. #define WRITEBUFLEN ((4096) + 4)
  81. #define JSM_VERSION "jsm: 1.2-1-INKERNEL"
  82. #define JSM_PARTNUM "40002438_A-INKERNEL"
  83. struct jsm_board;
  84. struct jsm_channel;
  85. /************************************************************************
  86. * Per board operations structure *
  87. ************************************************************************/
  88. struct board_ops {
  89. irq_handler_t intr;
  90. void (*uart_init)(struct jsm_channel *ch);
  91. void (*uart_off)(struct jsm_channel *ch);
  92. void (*param)(struct jsm_channel *ch);
  93. void (*assert_modem_signals)(struct jsm_channel *ch);
  94. void (*flush_uart_write)(struct jsm_channel *ch);
  95. void (*flush_uart_read)(struct jsm_channel *ch);
  96. void (*disable_receiver)(struct jsm_channel *ch);
  97. void (*enable_receiver)(struct jsm_channel *ch);
  98. void (*send_break)(struct jsm_channel *ch);
  99. void (*clear_break)(struct jsm_channel *ch);
  100. void (*send_start_character)(struct jsm_channel *ch);
  101. void (*send_stop_character)(struct jsm_channel *ch);
  102. void (*copy_data_from_queue_to_uart)(struct jsm_channel *ch);
  103. u32 (*get_uart_bytes_left)(struct jsm_channel *ch);
  104. void (*send_immediate_char)(struct jsm_channel *ch, unsigned char);
  105. };
  106. /*
  107. * Per-board information
  108. */
  109. struct jsm_board
  110. {
  111. int boardnum; /* Board number: 0-32 */
  112. int type; /* Type of board */
  113. u8 rev; /* PCI revision ID */
  114. struct pci_dev *pci_dev;
  115. u32 maxports; /* MAX ports this board can handle */
  116. spinlock_t bd_intr_lock; /* Used to protect the poller tasklet and
  117. * the interrupt routine from each other.
  118. */
  119. u32 nasync; /* Number of ports on card */
  120. u32 irq; /* Interrupt request number */
  121. u64 membase; /* Start of base memory of the card */
  122. u64 membase_end; /* End of base memory of the card */
  123. u8 __iomem *re_map_membase;/* Remapped memory of the card */
  124. u64 iobase; /* Start of io base of the card */
  125. u64 iobase_end; /* End of io base of the card */
  126. u32 bd_uart_offset; /* Space between each UART */
  127. struct jsm_channel *channels[MAXPORTS]; /* array of pointers to our channels. */
  128. u32 bd_dividend; /* Board/UARTs specific dividend */
  129. struct board_ops *bd_ops;
  130. struct list_head jsm_board_entry;
  131. };
  132. /************************************************************************
  133. * Device flag definitions for ch_flags.
  134. ************************************************************************/
  135. #define CH_PRON 0x0001 /* Printer on string */
  136. #define CH_STOP 0x0002 /* Output is stopped */
  137. #define CH_STOPI 0x0004 /* Input is stopped */
  138. #define CH_CD 0x0008 /* Carrier is present */
  139. #define CH_FCAR 0x0010 /* Carrier forced on */
  140. #define CH_HANGUP 0x0020 /* Hangup received */
  141. #define CH_RECEIVER_OFF 0x0040 /* Receiver is off */
  142. #define CH_OPENING 0x0080 /* Port in fragile open state */
  143. #define CH_CLOSING 0x0100 /* Port in fragile close state */
  144. #define CH_FIFO_ENABLED 0x0200 /* Port has FIFOs enabled */
  145. #define CH_TX_FIFO_EMPTY 0x0400 /* TX Fifo is completely empty */
  146. #define CH_TX_FIFO_LWM 0x0800 /* TX Fifo is below Low Water */
  147. #define CH_BREAK_SENDING 0x1000 /* Break is being sent */
  148. #define CH_LOOPBACK 0x2000 /* Channel is in lookback mode */
  149. #define CH_BAUD0 0x08000 /* Used for checking B0 transitions */
  150. /* Our Read/Error queue sizes */
  151. #define RQUEUEMASK 0x1FFF /* 8 K - 1 */
  152. #define EQUEUEMASK 0x1FFF /* 8 K - 1 */
  153. #define RQUEUESIZE (RQUEUEMASK + 1)
  154. #define EQUEUESIZE RQUEUESIZE
  155. /************************************************************************
  156. * Channel information structure.
  157. ************************************************************************/
  158. struct jsm_channel {
  159. struct uart_port uart_port;
  160. struct jsm_board *ch_bd; /* Board structure pointer */
  161. spinlock_t ch_lock; /* provide for serialization */
  162. wait_queue_head_t ch_flags_wait;
  163. u32 ch_portnum; /* Port number, 0 offset. */
  164. u32 ch_open_count; /* open count */
  165. u32 ch_flags; /* Channel flags */
  166. u64 ch_close_delay; /* How long we should drop RTS/DTR for */
  167. tcflag_t ch_c_iflag; /* channel iflags */
  168. tcflag_t ch_c_cflag; /* channel cflags */
  169. tcflag_t ch_c_oflag; /* channel oflags */
  170. tcflag_t ch_c_lflag; /* channel lflags */
  171. u8 ch_stopc; /* Stop character */
  172. u8 ch_startc; /* Start character */
  173. u8 ch_mostat; /* FEP output modem status */
  174. u8 ch_mistat; /* FEP input modem status */
  175. /* Pointers to the "mapped" UART structs */
  176. struct neo_uart_struct __iomem *ch_neo_uart; /* NEO card */
  177. struct cls_uart_struct __iomem *ch_cls_uart; /* Classic card */
  178. u8 ch_cached_lsr; /* Cached value of the LSR register */
  179. u8 *ch_rqueue; /* Our read queue buffer - malloc'ed */
  180. u16 ch_r_head; /* Head location of the read queue */
  181. u16 ch_r_tail; /* Tail location of the read queue */
  182. u8 *ch_equeue; /* Our error queue buffer - malloc'ed */
  183. u16 ch_e_head; /* Head location of the error queue */
  184. u16 ch_e_tail; /* Tail location of the error queue */
  185. u64 ch_rxcount; /* total of data received so far */
  186. u64 ch_txcount; /* total of data transmitted so far */
  187. u8 ch_r_tlevel; /* Receive Trigger level */
  188. u8 ch_t_tlevel; /* Transmit Trigger level */
  189. u8 ch_r_watermark; /* Receive Watermark */
  190. u32 ch_stops_sent; /* How many times I have sent a stop character
  191. * to try to stop the other guy sending.
  192. */
  193. u64 ch_err_parity; /* Count of parity errors on channel */
  194. u64 ch_err_frame; /* Count of framing errors on channel */
  195. u64 ch_err_break; /* Count of breaks on channel */
  196. u64 ch_err_overrun; /* Count of overruns on channel */
  197. u64 ch_xon_sends; /* Count of xons transmitted */
  198. u64 ch_xoff_sends; /* Count of xoffs transmitted */
  199. };
  200. /************************************************************************
  201. * Per channel/port Classic UART structures *
  202. ************************************************************************
  203. * Base Structure Entries Usage Meanings to Host *
  204. * *
  205. * W = read write R = read only *
  206. * U = Unused. *
  207. ************************************************************************/
  208. struct cls_uart_struct {
  209. u8 txrx; /* WR RHR/THR - Holding Reg */
  210. u8 ier; /* WR IER - Interrupt Enable Reg */
  211. u8 isr_fcr; /* WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg*/
  212. u8 lcr; /* WR LCR - Line Control Reg */
  213. u8 mcr; /* WR MCR - Modem Control Reg */
  214. u8 lsr; /* WR LSR - Line Status Reg */
  215. u8 msr; /* WR MSR - Modem Status Reg */
  216. u8 spr; /* WR SPR - Scratch Pad Reg */
  217. };
  218. /* Where to read the interrupt register (8bits) */
  219. #define UART_CLASSIC_POLL_ADDR_OFFSET 0x40
  220. #define UART_EXAR654_ENHANCED_REGISTER_SET 0xBF
  221. #define UART_16654_FCR_TXTRIGGER_8 0x0
  222. #define UART_16654_FCR_TXTRIGGER_16 0x10
  223. #define UART_16654_FCR_TXTRIGGER_32 0x20
  224. #define UART_16654_FCR_TXTRIGGER_56 0x30
  225. #define UART_16654_FCR_RXTRIGGER_8 0x0
  226. #define UART_16654_FCR_RXTRIGGER_16 0x40
  227. #define UART_16654_FCR_RXTRIGGER_56 0x80
  228. #define UART_16654_FCR_RXTRIGGER_60 0xC0
  229. #define UART_IIR_CTSRTS 0x20 /* Received CTS/RTS change of state */
  230. #define UART_IIR_RDI_TIMEOUT 0x0C /* Receiver data TIMEOUT */
  231. /*
  232. * These are the EXTENDED definitions for the Exar 654's Interrupt
  233. * Enable Register.
  234. */
  235. #define UART_EXAR654_EFR_ECB 0x10 /* Enhanced control bit */
  236. #define UART_EXAR654_EFR_IXON 0x2 /* Receiver compares Xon1/Xoff1 */
  237. #define UART_EXAR654_EFR_IXOFF 0x8 /* Transmit Xon1/Xoff1 */
  238. #define UART_EXAR654_EFR_RTSDTR 0x40 /* Auto RTS/DTR Flow Control Enable */
  239. #define UART_EXAR654_EFR_CTSDSR 0x80 /* Auto CTS/DSR Flow COntrol Enable */
  240. #define UART_EXAR654_XOFF_DETECT 0x1 /* Indicates whether chip saw an incoming XOFF char */
  241. #define UART_EXAR654_XON_DETECT 0x2 /* Indicates whether chip saw an incoming XON char */
  242. #define UART_EXAR654_IER_XOFF 0x20 /* Xoff Interrupt Enable */
  243. #define UART_EXAR654_IER_RTSDTR 0x40 /* Output Interrupt Enable */
  244. #define UART_EXAR654_IER_CTSDSR 0x80 /* Input Interrupt Enable */
  245. /************************************************************************
  246. * Per channel/port NEO UART structure *
  247. ************************************************************************
  248. * Base Structure Entries Usage Meanings to Host *
  249. * *
  250. * W = read write R = read only *
  251. * U = Unused. *
  252. ************************************************************************/
  253. struct neo_uart_struct {
  254. u8 txrx; /* WR RHR/THR - Holding Reg */
  255. u8 ier; /* WR IER - Interrupt Enable Reg */
  256. u8 isr_fcr; /* WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg */
  257. u8 lcr; /* WR LCR - Line Control Reg */
  258. u8 mcr; /* WR MCR - Modem Control Reg */
  259. u8 lsr; /* WR LSR - Line Status Reg */
  260. u8 msr; /* WR MSR - Modem Status Reg */
  261. u8 spr; /* WR SPR - Scratch Pad Reg */
  262. u8 fctr; /* WR FCTR - Feature Control Reg */
  263. u8 efr; /* WR EFR - Enhanced Function Reg */
  264. u8 tfifo; /* WR TXCNT/TXTRG - Transmit FIFO Reg */
  265. u8 rfifo; /* WR RXCNT/RXTRG - Receive FIFO Reg */
  266. u8 xoffchar1; /* WR XOFF 1 - XOff Character 1 Reg */
  267. u8 xoffchar2; /* WR XOFF 2 - XOff Character 2 Reg */
  268. u8 xonchar1; /* WR XON 1 - Xon Character 1 Reg */
  269. u8 xonchar2; /* WR XON 2 - XOn Character 2 Reg */
  270. u8 reserved1[0x2ff - 0x200]; /* U Reserved by Exar */
  271. u8 txrxburst[64]; /* RW 64 bytes of RX/TX FIFO Data */
  272. u8 reserved2[0x37f - 0x340]; /* U Reserved by Exar */
  273. u8 rxburst_with_errors[64]; /* R 64 bytes of RX FIFO Data + LSR */
  274. };
  275. /* Where to read the extended interrupt register (32bits instead of 8bits) */
  276. #define UART_17158_POLL_ADDR_OFFSET 0x80
  277. /*
  278. * These are the redefinitions for the FCTR on the XR17C158, since
  279. * Exar made them different than their earlier design. (XR16C854)
  280. */
  281. /* These are only applicable when table D is selected */
  282. #define UART_17158_FCTR_RTS_NODELAY 0x00
  283. #define UART_17158_FCTR_RTS_4DELAY 0x01
  284. #define UART_17158_FCTR_RTS_6DELAY 0x02
  285. #define UART_17158_FCTR_RTS_8DELAY 0x03
  286. #define UART_17158_FCTR_RTS_12DELAY 0x12
  287. #define UART_17158_FCTR_RTS_16DELAY 0x05
  288. #define UART_17158_FCTR_RTS_20DELAY 0x13
  289. #define UART_17158_FCTR_RTS_24DELAY 0x06
  290. #define UART_17158_FCTR_RTS_28DELAY 0x14
  291. #define UART_17158_FCTR_RTS_32DELAY 0x07
  292. #define UART_17158_FCTR_RTS_36DELAY 0x16
  293. #define UART_17158_FCTR_RTS_40DELAY 0x08
  294. #define UART_17158_FCTR_RTS_44DELAY 0x09
  295. #define UART_17158_FCTR_RTS_48DELAY 0x10
  296. #define UART_17158_FCTR_RTS_52DELAY 0x11
  297. #define UART_17158_FCTR_RTS_IRDA 0x10
  298. #define UART_17158_FCTR_RS485 0x20
  299. #define UART_17158_FCTR_TRGA 0x00
  300. #define UART_17158_FCTR_TRGB 0x40
  301. #define UART_17158_FCTR_TRGC 0x80
  302. #define UART_17158_FCTR_TRGD 0xC0
  303. /* 17158 trigger table selects.. */
  304. #define UART_17158_FCTR_BIT6 0x40
  305. #define UART_17158_FCTR_BIT7 0x80
  306. /* 17158 TX/RX memmapped buffer offsets */
  307. #define UART_17158_RX_FIFOSIZE 64
  308. #define UART_17158_TX_FIFOSIZE 64
  309. /* 17158 Extended IIR's */
  310. #define UART_17158_IIR_RDI_TIMEOUT 0x0C /* Receiver data TIMEOUT */
  311. #define UART_17158_IIR_XONXOFF 0x10 /* Received an XON/XOFF char */
  312. #define UART_17158_IIR_HWFLOW_STATE_CHANGE 0x20 /* CTS/DSR or RTS/DTR state change */
  313. #define UART_17158_IIR_FIFO_ENABLED 0xC0 /* 16550 FIFOs are Enabled */
  314. /*
  315. * These are the extended interrupts that get sent
  316. * back to us from the UART's 32bit interrupt register
  317. */
  318. #define UART_17158_RX_LINE_STATUS 0x1 /* RX Ready */
  319. #define UART_17158_RXRDY_TIMEOUT 0x2 /* RX Ready Timeout */
  320. #define UART_17158_TXRDY 0x3 /* TX Ready */
  321. #define UART_17158_MSR 0x4 /* Modem State Change */
  322. #define UART_17158_TX_AND_FIFO_CLR 0x40 /* Transmitter Holding Reg Empty */
  323. #define UART_17158_RX_FIFO_DATA_ERROR 0x80 /* UART detected an RX FIFO Data error */
  324. /*
  325. * These are the EXTENDED definitions for the 17C158's Interrupt
  326. * Enable Register.
  327. */
  328. #define UART_17158_EFR_ECB 0x10 /* Enhanced control bit */
  329. #define UART_17158_EFR_IXON 0x2 /* Receiver compares Xon1/Xoff1 */
  330. #define UART_17158_EFR_IXOFF 0x8 /* Transmit Xon1/Xoff1 */
  331. #define UART_17158_EFR_RTSDTR 0x40 /* Auto RTS/DTR Flow Control Enable */
  332. #define UART_17158_EFR_CTSDSR 0x80 /* Auto CTS/DSR Flow COntrol Enable */
  333. #define UART_17158_XOFF_DETECT 0x1 /* Indicates whether chip saw an incoming XOFF char */
  334. #define UART_17158_XON_DETECT 0x2 /* Indicates whether chip saw an incoming XON char */
  335. #define UART_17158_IER_RSVD1 0x10 /* Reserved by Exar */
  336. #define UART_17158_IER_XOFF 0x20 /* Xoff Interrupt Enable */
  337. #define UART_17158_IER_RTSDTR 0x40 /* Output Interrupt Enable */
  338. #define UART_17158_IER_CTSDSR 0x80 /* Input Interrupt Enable */
  339. #define PCI_DEVICE_NEO_2DB9_PCI_NAME "Neo 2 - DB9 Universal PCI"
  340. #define PCI_DEVICE_NEO_2DB9PRI_PCI_NAME "Neo 2 - DB9 Universal PCI - Powered Ring Indicator"
  341. #define PCI_DEVICE_NEO_2RJ45_PCI_NAME "Neo 2 - RJ45 Universal PCI"
  342. #define PCI_DEVICE_NEO_2RJ45PRI_PCI_NAME "Neo 2 - RJ45 Universal PCI - Powered Ring Indicator"
  343. #define PCIE_DEVICE_NEO_IBM_PCI_NAME "Neo 4 - PCI Express - IBM"
  344. /*
  345. * Our Global Variables.
  346. */
  347. extern struct uart_driver jsm_uart_driver;
  348. extern struct board_ops jsm_neo_ops;
  349. extern struct board_ops jsm_cls_ops;
  350. extern int jsm_debug;
  351. /*************************************************************************
  352. *
  353. * Prototypes for non-static functions used in more than one module
  354. *
  355. *************************************************************************/
  356. int jsm_tty_init(struct jsm_board *);
  357. int jsm_uart_port_init(struct jsm_board *);
  358. int jsm_remove_uart_port(struct jsm_board *);
  359. void jsm_input(struct jsm_channel *ch);
  360. void jsm_check_queue_flow_control(struct jsm_channel *ch);
  361. #endif