cpm_uart.h 3.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Driver for CPM (SCC/SMC) serial ports
  4. *
  5. * Copyright (C) 2004 Freescale Semiconductor, Inc.
  6. *
  7. * 2006 (c) MontaVista Software, Inc.
  8. * Vitaly Bordug <vbordug@ru.mvista.com>
  9. */
  10. #ifndef CPM_UART_H
  11. #define CPM_UART_H
  12. #include <linux/platform_device.h>
  13. #include <linux/fs_uart_pd.h>
  14. #if defined(CONFIG_CPM2)
  15. #include "cpm_uart_cpm2.h"
  16. #elif defined(CONFIG_CPM1)
  17. #include "cpm_uart_cpm1.h"
  18. #endif
  19. #define SERIAL_CPM_MAJOR 204
  20. #define SERIAL_CPM_MINOR 46
  21. #define IS_SMC(pinfo) (pinfo->flags & FLAG_SMC)
  22. #define IS_DISCARDING(pinfo) (pinfo->flags & FLAG_DISCARDING)
  23. #define FLAG_DISCARDING 0x00000004 /* when set, don't discard */
  24. #define FLAG_SMC 0x00000002
  25. #define FLAG_CONSOLE 0x00000001
  26. #define UART_SMC1 fsid_smc1_uart
  27. #define UART_SMC2 fsid_smc2_uart
  28. #define UART_SCC1 fsid_scc1_uart
  29. #define UART_SCC2 fsid_scc2_uart
  30. #define UART_SCC3 fsid_scc3_uart
  31. #define UART_SCC4 fsid_scc4_uart
  32. #define UART_NR fs_uart_nr
  33. #define RX_NUM_FIFO 4
  34. #define RX_BUF_SIZE 32
  35. #define TX_NUM_FIFO 4
  36. #define TX_BUF_SIZE 32
  37. #define SCC_WAIT_CLOSING 100
  38. #define GPIO_CTS 0
  39. #define GPIO_RTS 1
  40. #define GPIO_DCD 2
  41. #define GPIO_DSR 3
  42. #define GPIO_DTR 4
  43. #define GPIO_RI 5
  44. #define NUM_GPIOS (GPIO_RI+1)
  45. struct uart_cpm_port {
  46. struct uart_port port;
  47. u16 rx_nrfifos;
  48. u16 rx_fifosize;
  49. u16 tx_nrfifos;
  50. u16 tx_fifosize;
  51. smc_t __iomem *smcp;
  52. smc_uart_t __iomem *smcup;
  53. scc_t __iomem *sccp;
  54. scc_uart_t __iomem *sccup;
  55. cbd_t __iomem *rx_bd_base;
  56. cbd_t __iomem *rx_cur;
  57. cbd_t __iomem *tx_bd_base;
  58. cbd_t __iomem *tx_cur;
  59. unsigned char *tx_buf;
  60. unsigned char *rx_buf;
  61. u32 flags;
  62. struct clk *clk;
  63. u8 brg;
  64. uint dp_addr;
  65. void *mem_addr;
  66. dma_addr_t dma_addr;
  67. u32 mem_size;
  68. /* wait on close if needed */
  69. int wait_closing;
  70. /* value to combine with opcode to form cpm command */
  71. u32 command;
  72. int gpios[NUM_GPIOS];
  73. };
  74. extern int cpm_uart_nr;
  75. extern struct uart_cpm_port cpm_uart_ports[UART_NR];
  76. /* these are located in their respective files */
  77. void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd);
  78. void __iomem *cpm_uart_map_pram(struct uart_cpm_port *port,
  79. struct device_node *np);
  80. void cpm_uart_unmap_pram(struct uart_cpm_port *port, void __iomem *pram);
  81. int cpm_uart_init_portdesc(void);
  82. int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con);
  83. void cpm_uart_freebuf(struct uart_cpm_port *pinfo);
  84. void smc1_lineif(struct uart_cpm_port *pinfo);
  85. void smc2_lineif(struct uart_cpm_port *pinfo);
  86. void scc1_lineif(struct uart_cpm_port *pinfo);
  87. void scc2_lineif(struct uart_cpm_port *pinfo);
  88. void scc3_lineif(struct uart_cpm_port *pinfo);
  89. void scc4_lineif(struct uart_cpm_port *pinfo);
  90. /*
  91. virtual to phys transtalion
  92. */
  93. static inline unsigned long cpu2cpm_addr(void *addr,
  94. struct uart_cpm_port *pinfo)
  95. {
  96. int offset;
  97. u32 val = (u32)addr;
  98. u32 mem = (u32)pinfo->mem_addr;
  99. /* sane check */
  100. if (likely(val >= mem && val < mem + pinfo->mem_size)) {
  101. offset = val - mem;
  102. return pinfo->dma_addr + offset;
  103. }
  104. /* something nasty happened */
  105. BUG();
  106. return 0;
  107. }
  108. static inline void *cpm2cpu_addr(unsigned long addr,
  109. struct uart_cpm_port *pinfo)
  110. {
  111. int offset;
  112. u32 val = addr;
  113. u32 dma = (u32)pinfo->dma_addr;
  114. /* sane check */
  115. if (likely(val >= dma && val < dma + pinfo->mem_size)) {
  116. offset = val - dma;
  117. return pinfo->mem_addr + offset;
  118. }
  119. /* something nasty happened */
  120. BUG();
  121. return NULL;
  122. }
  123. #endif /* CPM_UART_H */