arc_uart.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * ARC On-Chip(fpga) UART Driver
  4. *
  5. * Copyright (C) 2010-2012 Synopsys, Inc. (www.synopsys.com)
  6. *
  7. * vineetg: July 10th 2012
  8. * -Decoupled the driver from arch/arc
  9. * +Using platform_get_resource() for irq/membase (thx to bfin_uart.c)
  10. * +Using early_platform_xxx() for early console (thx to mach-shmobile/xxx)
  11. *
  12. * Vineetg: Aug 21st 2010
  13. * -Is uart_tx_stopped() not done in tty write path as it has already been
  14. * taken care of, in serial core
  15. *
  16. * Vineetg: Aug 18th 2010
  17. * -New Serial Core based ARC UART driver
  18. * -Derived largely from blackfin driver albiet with some major tweaks
  19. *
  20. * TODO:
  21. * -check if sysreq works
  22. */
  23. #if defined(CONFIG_SERIAL_ARC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  24. #define SUPPORT_SYSRQ
  25. #endif
  26. #include <linux/module.h>
  27. #include <linux/serial.h>
  28. #include <linux/console.h>
  29. #include <linux/sysrq.h>
  30. #include <linux/platform_device.h>
  31. #include <linux/tty.h>
  32. #include <linux/tty_flip.h>
  33. #include <linux/serial_core.h>
  34. #include <linux/io.h>
  35. #include <linux/of_irq.h>
  36. #include <linux/of_address.h>
  37. /*************************************
  38. * ARC UART Hardware Specs
  39. ************************************/
  40. #define ARC_UART_TX_FIFO_SIZE 1
  41. /*
  42. * UART Register set (this is not a Standards Compliant IP)
  43. * Also each reg is Word aligned, but only 8 bits wide
  44. */
  45. #define R_ID0 0
  46. #define R_ID1 4
  47. #define R_ID2 8
  48. #define R_ID3 12
  49. #define R_DATA 16
  50. #define R_STS 20
  51. #define R_BAUDL 24
  52. #define R_BAUDH 28
  53. /* Bits for UART Status Reg (R/W) */
  54. #define RXIENB 0x04 /* Receive Interrupt Enable */
  55. #define TXIENB 0x40 /* Transmit Interrupt Enable */
  56. #define RXEMPTY 0x20 /* Receive FIFO Empty: No char receivede */
  57. #define TXEMPTY 0x80 /* Transmit FIFO Empty, thus char can be written into */
  58. #define RXFULL 0x08 /* Receive FIFO full */
  59. #define RXFULL1 0x10 /* Receive FIFO has space for 1 char (tot space=4) */
  60. #define RXFERR 0x01 /* Frame Error: Stop Bit not detected */
  61. #define RXOERR 0x02 /* OverFlow Err: Char recv but RXFULL still set */
  62. /* Uart bit fiddling helpers: lowest level */
  63. #define RBASE(port, reg) (port->membase + reg)
  64. #define UART_REG_SET(u, r, v) writeb((v), RBASE(u, r))
  65. #define UART_REG_GET(u, r) readb(RBASE(u, r))
  66. #define UART_REG_OR(u, r, v) UART_REG_SET(u, r, UART_REG_GET(u, r) | (v))
  67. #define UART_REG_CLR(u, r, v) UART_REG_SET(u, r, UART_REG_GET(u, r) & ~(v))
  68. /* Uart bit fiddling helpers: API level */
  69. #define UART_SET_DATA(uart, val) UART_REG_SET(uart, R_DATA, val)
  70. #define UART_GET_DATA(uart) UART_REG_GET(uart, R_DATA)
  71. #define UART_SET_BAUDH(uart, val) UART_REG_SET(uart, R_BAUDH, val)
  72. #define UART_SET_BAUDL(uart, val) UART_REG_SET(uart, R_BAUDL, val)
  73. #define UART_CLR_STATUS(uart, val) UART_REG_CLR(uart, R_STS, val)
  74. #define UART_GET_STATUS(uart) UART_REG_GET(uart, R_STS)
  75. #define UART_ALL_IRQ_DISABLE(uart) UART_REG_CLR(uart, R_STS, RXIENB|TXIENB)
  76. #define UART_RX_IRQ_DISABLE(uart) UART_REG_CLR(uart, R_STS, RXIENB)
  77. #define UART_TX_IRQ_DISABLE(uart) UART_REG_CLR(uart, R_STS, TXIENB)
  78. #define UART_ALL_IRQ_ENABLE(uart) UART_REG_OR(uart, R_STS, RXIENB|TXIENB)
  79. #define UART_RX_IRQ_ENABLE(uart) UART_REG_OR(uart, R_STS, RXIENB)
  80. #define UART_TX_IRQ_ENABLE(uart) UART_REG_OR(uart, R_STS, TXIENB)
  81. #define ARC_SERIAL_DEV_NAME "ttyARC"
  82. struct arc_uart_port {
  83. struct uart_port port;
  84. unsigned long baud;
  85. };
  86. #define to_arc_port(uport) container_of(uport, struct arc_uart_port, port)
  87. static struct arc_uart_port arc_uart_ports[CONFIG_SERIAL_ARC_NR_PORTS];
  88. #ifdef CONFIG_SERIAL_ARC_CONSOLE
  89. static struct console arc_console;
  90. #endif
  91. #define DRIVER_NAME "arc-uart"
  92. static struct uart_driver arc_uart_driver = {
  93. .owner = THIS_MODULE,
  94. .driver_name = DRIVER_NAME,
  95. .dev_name = ARC_SERIAL_DEV_NAME,
  96. .major = 0,
  97. .minor = 0,
  98. .nr = CONFIG_SERIAL_ARC_NR_PORTS,
  99. #ifdef CONFIG_SERIAL_ARC_CONSOLE
  100. .cons = &arc_console,
  101. #endif
  102. };
  103. static void arc_serial_stop_rx(struct uart_port *port)
  104. {
  105. UART_RX_IRQ_DISABLE(port);
  106. }
  107. static void arc_serial_stop_tx(struct uart_port *port)
  108. {
  109. while (!(UART_GET_STATUS(port) & TXEMPTY))
  110. cpu_relax();
  111. UART_TX_IRQ_DISABLE(port);
  112. }
  113. /*
  114. * Return TIOCSER_TEMT when transmitter is not busy.
  115. */
  116. static unsigned int arc_serial_tx_empty(struct uart_port *port)
  117. {
  118. unsigned int stat;
  119. stat = UART_GET_STATUS(port);
  120. if (stat & TXEMPTY)
  121. return TIOCSER_TEMT;
  122. return 0;
  123. }
  124. /*
  125. * Driver internal routine, used by both tty(serial core) as well as tx-isr
  126. * -Called under spinlock in either cases
  127. * -also tty->stopped has already been checked
  128. * = by uart_start( ) before calling us
  129. * = tx_ist checks that too before calling
  130. */
  131. static void arc_serial_tx_chars(struct uart_port *port)
  132. {
  133. struct circ_buf *xmit = &port->state->xmit;
  134. int sent = 0;
  135. unsigned char ch;
  136. if (unlikely(port->x_char)) {
  137. UART_SET_DATA(port, port->x_char);
  138. port->icount.tx++;
  139. port->x_char = 0;
  140. sent = 1;
  141. } else if (!uart_circ_empty(xmit)) {
  142. ch = xmit->buf[xmit->tail];
  143. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  144. port->icount.tx++;
  145. while (!(UART_GET_STATUS(port) & TXEMPTY))
  146. cpu_relax();
  147. UART_SET_DATA(port, ch);
  148. sent = 1;
  149. }
  150. /*
  151. * If num chars in xmit buffer are too few, ask tty layer for more.
  152. * By Hard ISR to schedule processing in software interrupt part
  153. */
  154. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  155. uart_write_wakeup(port);
  156. if (sent)
  157. UART_TX_IRQ_ENABLE(port);
  158. }
  159. /*
  160. * port is locked and interrupts are disabled
  161. * uart_start( ) calls us under the port spinlock irqsave
  162. */
  163. static void arc_serial_start_tx(struct uart_port *port)
  164. {
  165. arc_serial_tx_chars(port);
  166. }
  167. static void arc_serial_rx_chars(struct uart_port *port, unsigned int status)
  168. {
  169. unsigned int ch, flg = 0;
  170. /*
  171. * UART has 4 deep RX-FIFO. Driver's recongnition of this fact
  172. * is very subtle. Here's how ...
  173. * Upon getting a RX-Intr, such that RX-EMPTY=0, meaning data available,
  174. * driver reads the DATA Reg and keeps doing that in a loop, until
  175. * RX-EMPTY=1. Multiple chars being avail, with a single Interrupt,
  176. * before RX-EMPTY=0, implies some sort of buffering going on in the
  177. * controller, which is indeed the Rx-FIFO.
  178. */
  179. do {
  180. /*
  181. * This could be an Rx Intr for err (no data),
  182. * so check err and clear that Intr first
  183. */
  184. if (unlikely(status & (RXOERR | RXFERR))) {
  185. if (status & RXOERR) {
  186. port->icount.overrun++;
  187. flg = TTY_OVERRUN;
  188. UART_CLR_STATUS(port, RXOERR);
  189. }
  190. if (status & RXFERR) {
  191. port->icount.frame++;
  192. flg = TTY_FRAME;
  193. UART_CLR_STATUS(port, RXFERR);
  194. }
  195. } else
  196. flg = TTY_NORMAL;
  197. if (status & RXEMPTY)
  198. continue;
  199. ch = UART_GET_DATA(port);
  200. port->icount.rx++;
  201. if (!(uart_handle_sysrq_char(port, ch)))
  202. uart_insert_char(port, status, RXOERR, ch, flg);
  203. spin_unlock(&port->lock);
  204. tty_flip_buffer_push(&port->state->port);
  205. spin_lock(&port->lock);
  206. } while (!((status = UART_GET_STATUS(port)) & RXEMPTY));
  207. }
  208. /*
  209. * A note on the Interrupt handling state machine of this driver
  210. *
  211. * kernel printk writes funnel thru the console driver framework and in order
  212. * to keep things simple as well as efficient, it writes to UART in polled
  213. * mode, in one shot, and exits.
  214. *
  215. * OTOH, Userland output (via tty layer), uses interrupt based writes as there
  216. * can be undeterministic delay between char writes.
  217. *
  218. * Thus Rx-interrupts are always enabled, while tx-interrupts are by default
  219. * disabled.
  220. *
  221. * When tty has some data to send out, serial core calls driver's start_tx
  222. * which
  223. * -checks-if-tty-buffer-has-char-to-send
  224. * -writes-data-to-uart
  225. * -enable-tx-intr
  226. *
  227. * Once data bits are pushed out, controller raises the Tx-room-avail-Interrupt.
  228. * The first thing Tx ISR does is disable further Tx interrupts (as this could
  229. * be the last char to send, before settling down into the quiet polled mode).
  230. * It then calls the exact routine used by tty layer write to send out any
  231. * more char in tty buffer. In case of sending, it re-enables Tx-intr. In case
  232. * of no data, it remains disabled.
  233. * This is how the transmit state machine is dynamically switched on/off
  234. */
  235. static irqreturn_t arc_serial_isr(int irq, void *dev_id)
  236. {
  237. struct uart_port *port = dev_id;
  238. unsigned int status;
  239. status = UART_GET_STATUS(port);
  240. /*
  241. * Single IRQ for both Rx (data available) Tx (room available) Interrupt
  242. * notifications from the UART Controller.
  243. * To demultiplex between the two, we check the relevant bits
  244. */
  245. if (status & RXIENB) {
  246. /* already in ISR, no need of xx_irqsave */
  247. spin_lock(&port->lock);
  248. arc_serial_rx_chars(port, status);
  249. spin_unlock(&port->lock);
  250. }
  251. if ((status & TXIENB) && (status & TXEMPTY)) {
  252. /* Unconditionally disable further Tx-Interrupts.
  253. * will be enabled by tx_chars() if needed.
  254. */
  255. UART_TX_IRQ_DISABLE(port);
  256. spin_lock(&port->lock);
  257. if (!uart_tx_stopped(port))
  258. arc_serial_tx_chars(port);
  259. spin_unlock(&port->lock);
  260. }
  261. return IRQ_HANDLED;
  262. }
  263. static unsigned int arc_serial_get_mctrl(struct uart_port *port)
  264. {
  265. /*
  266. * Pretend we have a Modem status reg and following bits are
  267. * always set, to satify the serial core state machine
  268. * (DSR) Data Set Ready
  269. * (CTS) Clear To Send
  270. * (CAR) Carrier Detect
  271. */
  272. return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
  273. }
  274. static void arc_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
  275. {
  276. /* MCR not present */
  277. }
  278. static void arc_serial_break_ctl(struct uart_port *port, int break_state)
  279. {
  280. /* ARC UART doesn't support sending Break signal */
  281. }
  282. static int arc_serial_startup(struct uart_port *port)
  283. {
  284. /* Before we hook up the ISR, Disable all UART Interrupts */
  285. UART_ALL_IRQ_DISABLE(port);
  286. if (request_irq(port->irq, arc_serial_isr, 0, "arc uart rx-tx", port)) {
  287. dev_warn(port->dev, "Unable to attach ARC UART intr\n");
  288. return -EBUSY;
  289. }
  290. UART_RX_IRQ_ENABLE(port); /* Only Rx IRQ enabled to begin with */
  291. return 0;
  292. }
  293. /* This is not really needed */
  294. static void arc_serial_shutdown(struct uart_port *port)
  295. {
  296. free_irq(port->irq, port);
  297. }
  298. static void
  299. arc_serial_set_termios(struct uart_port *port, struct ktermios *new,
  300. struct ktermios *old)
  301. {
  302. struct arc_uart_port *uart = to_arc_port(port);
  303. unsigned int baud, uartl, uarth, hw_val;
  304. unsigned long flags;
  305. /*
  306. * Use the generic handler so that any specially encoded baud rates
  307. * such as SPD_xx flags or "%B0" can be handled
  308. * Max Baud I suppose will not be more than current 115K * 4
  309. * Formula for ARC UART is: hw-val = ((CLK/(BAUD*4)) -1)
  310. * spread over two 8-bit registers
  311. */
  312. baud = uart_get_baud_rate(port, new, old, 0, 460800);
  313. hw_val = port->uartclk / (uart->baud * 4) - 1;
  314. uartl = hw_val & 0xFF;
  315. uarth = (hw_val >> 8) & 0xFF;
  316. spin_lock_irqsave(&port->lock, flags);
  317. UART_ALL_IRQ_DISABLE(port);
  318. UART_SET_BAUDL(port, uartl);
  319. UART_SET_BAUDH(port, uarth);
  320. UART_RX_IRQ_ENABLE(port);
  321. /*
  322. * UART doesn't support Parity/Hardware Flow Control;
  323. * Only supports 8N1 character size
  324. */
  325. new->c_cflag &= ~(CMSPAR|CRTSCTS|CSIZE);
  326. new->c_cflag |= CS8;
  327. if (old)
  328. tty_termios_copy_hw(new, old);
  329. /* Don't rewrite B0 */
  330. if (tty_termios_baud_rate(new))
  331. tty_termios_encode_baud_rate(new, baud, baud);
  332. uart_update_timeout(port, new->c_cflag, baud);
  333. spin_unlock_irqrestore(&port->lock, flags);
  334. }
  335. static const char *arc_serial_type(struct uart_port *port)
  336. {
  337. return port->type == PORT_ARC ? DRIVER_NAME : NULL;
  338. }
  339. static void arc_serial_release_port(struct uart_port *port)
  340. {
  341. }
  342. static int arc_serial_request_port(struct uart_port *port)
  343. {
  344. return 0;
  345. }
  346. /*
  347. * Verify the new serial_struct (for TIOCSSERIAL).
  348. */
  349. static int
  350. arc_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
  351. {
  352. if (port->type != PORT_UNKNOWN && ser->type != PORT_ARC)
  353. return -EINVAL;
  354. return 0;
  355. }
  356. /*
  357. * Configure/autoconfigure the port.
  358. */
  359. static void arc_serial_config_port(struct uart_port *port, int flags)
  360. {
  361. if (flags & UART_CONFIG_TYPE)
  362. port->type = PORT_ARC;
  363. }
  364. #ifdef CONFIG_CONSOLE_POLL
  365. static void arc_serial_poll_putchar(struct uart_port *port, unsigned char chr)
  366. {
  367. while (!(UART_GET_STATUS(port) & TXEMPTY))
  368. cpu_relax();
  369. UART_SET_DATA(port, chr);
  370. }
  371. static int arc_serial_poll_getchar(struct uart_port *port)
  372. {
  373. unsigned char chr;
  374. while (!(UART_GET_STATUS(port) & RXEMPTY))
  375. cpu_relax();
  376. chr = UART_GET_DATA(port);
  377. return chr;
  378. }
  379. #endif
  380. static const struct uart_ops arc_serial_pops = {
  381. .tx_empty = arc_serial_tx_empty,
  382. .set_mctrl = arc_serial_set_mctrl,
  383. .get_mctrl = arc_serial_get_mctrl,
  384. .stop_tx = arc_serial_stop_tx,
  385. .start_tx = arc_serial_start_tx,
  386. .stop_rx = arc_serial_stop_rx,
  387. .break_ctl = arc_serial_break_ctl,
  388. .startup = arc_serial_startup,
  389. .shutdown = arc_serial_shutdown,
  390. .set_termios = arc_serial_set_termios,
  391. .type = arc_serial_type,
  392. .release_port = arc_serial_release_port,
  393. .request_port = arc_serial_request_port,
  394. .config_port = arc_serial_config_port,
  395. .verify_port = arc_serial_verify_port,
  396. #ifdef CONFIG_CONSOLE_POLL
  397. .poll_put_char = arc_serial_poll_putchar,
  398. .poll_get_char = arc_serial_poll_getchar,
  399. #endif
  400. };
  401. #ifdef CONFIG_SERIAL_ARC_CONSOLE
  402. static int arc_serial_console_setup(struct console *co, char *options)
  403. {
  404. struct uart_port *port;
  405. int baud = 115200;
  406. int bits = 8;
  407. int parity = 'n';
  408. int flow = 'n';
  409. if (co->index < 0 || co->index >= CONFIG_SERIAL_ARC_NR_PORTS)
  410. return -ENODEV;
  411. /*
  412. * The uart port backing the console (e.g. ttyARC1) might not have been
  413. * init yet. If so, defer the console setup to after the port.
  414. */
  415. port = &arc_uart_ports[co->index].port;
  416. if (!port->membase)
  417. return -ENODEV;
  418. if (options)
  419. uart_parse_options(options, &baud, &parity, &bits, &flow);
  420. /*
  421. * Serial core will call port->ops->set_termios( )
  422. * which will set the baud reg
  423. */
  424. return uart_set_options(port, co, baud, parity, bits, flow);
  425. }
  426. static void arc_serial_console_putchar(struct uart_port *port, int ch)
  427. {
  428. while (!(UART_GET_STATUS(port) & TXEMPTY))
  429. cpu_relax();
  430. UART_SET_DATA(port, (unsigned char)ch);
  431. }
  432. /*
  433. * Interrupts are disabled on entering
  434. */
  435. static void arc_serial_console_write(struct console *co, const char *s,
  436. unsigned int count)
  437. {
  438. struct uart_port *port = &arc_uart_ports[co->index].port;
  439. unsigned long flags;
  440. spin_lock_irqsave(&port->lock, flags);
  441. uart_console_write(port, s, count, arc_serial_console_putchar);
  442. spin_unlock_irqrestore(&port->lock, flags);
  443. }
  444. static struct console arc_console = {
  445. .name = ARC_SERIAL_DEV_NAME,
  446. .write = arc_serial_console_write,
  447. .device = uart_console_device,
  448. .setup = arc_serial_console_setup,
  449. .flags = CON_PRINTBUFFER,
  450. .index = -1,
  451. .data = &arc_uart_driver
  452. };
  453. static void arc_early_serial_write(struct console *con, const char *s,
  454. unsigned int n)
  455. {
  456. struct earlycon_device *dev = con->data;
  457. uart_console_write(&dev->port, s, n, arc_serial_console_putchar);
  458. }
  459. static int __init arc_early_console_setup(struct earlycon_device *dev,
  460. const char *opt)
  461. {
  462. struct uart_port *port = &dev->port;
  463. unsigned int l, h, hw_val;
  464. if (!dev->port.membase)
  465. return -ENODEV;
  466. hw_val = port->uartclk / (dev->baud * 4) - 1;
  467. l = hw_val & 0xFF;
  468. h = (hw_val >> 8) & 0xFF;
  469. UART_SET_BAUDL(port, l);
  470. UART_SET_BAUDH(port, h);
  471. dev->con->write = arc_early_serial_write;
  472. return 0;
  473. }
  474. OF_EARLYCON_DECLARE(arc_uart, "snps,arc-uart", arc_early_console_setup);
  475. #endif /* CONFIG_SERIAL_ARC_CONSOLE */
  476. static int arc_serial_probe(struct platform_device *pdev)
  477. {
  478. struct device_node *np = pdev->dev.of_node;
  479. struct arc_uart_port *uart;
  480. struct uart_port *port;
  481. int dev_id;
  482. u32 val;
  483. /* no device tree device */
  484. if (!np)
  485. return -ENODEV;
  486. dev_id = of_alias_get_id(np, "serial");
  487. if (dev_id < 0)
  488. dev_id = 0;
  489. if (dev_id >= ARRAY_SIZE(arc_uart_ports)) {
  490. dev_err(&pdev->dev, "serial%d out of range\n", dev_id);
  491. return -EINVAL;
  492. }
  493. uart = &arc_uart_ports[dev_id];
  494. port = &uart->port;
  495. if (of_property_read_u32(np, "clock-frequency", &val)) {
  496. dev_err(&pdev->dev, "clock-frequency property NOTset\n");
  497. return -EINVAL;
  498. }
  499. port->uartclk = val;
  500. if (of_property_read_u32(np, "current-speed", &val)) {
  501. dev_err(&pdev->dev, "current-speed property NOT set\n");
  502. return -EINVAL;
  503. }
  504. uart->baud = val;
  505. port->membase = of_iomap(np, 0);
  506. if (!port->membase)
  507. /* No point of dev_err since UART itself is hosed here */
  508. return -ENXIO;
  509. port->irq = irq_of_parse_and_map(np, 0);
  510. port->dev = &pdev->dev;
  511. port->iotype = UPIO_MEM;
  512. port->flags = UPF_BOOT_AUTOCONF;
  513. port->line = dev_id;
  514. port->ops = &arc_serial_pops;
  515. port->fifosize = ARC_UART_TX_FIFO_SIZE;
  516. /*
  517. * uart_insert_char( ) uses it in decideding whether to ignore a
  518. * char or not. Explicitly setting it here, removes the subtelty
  519. */
  520. port->ignore_status_mask = 0;
  521. return uart_add_one_port(&arc_uart_driver, &arc_uart_ports[dev_id].port);
  522. }
  523. static int arc_serial_remove(struct platform_device *pdev)
  524. {
  525. /* This will never be called */
  526. return 0;
  527. }
  528. static const struct of_device_id arc_uart_dt_ids[] = {
  529. { .compatible = "snps,arc-uart" },
  530. { /* Sentinel */ }
  531. };
  532. MODULE_DEVICE_TABLE(of, arc_uart_dt_ids);
  533. static struct platform_driver arc_platform_driver = {
  534. .probe = arc_serial_probe,
  535. .remove = arc_serial_remove,
  536. .driver = {
  537. .name = DRIVER_NAME,
  538. .of_match_table = arc_uart_dt_ids,
  539. },
  540. };
  541. static int __init arc_serial_init(void)
  542. {
  543. int ret;
  544. ret = uart_register_driver(&arc_uart_driver);
  545. if (ret)
  546. return ret;
  547. ret = platform_driver_register(&arc_platform_driver);
  548. if (ret)
  549. uart_unregister_driver(&arc_uart_driver);
  550. return ret;
  551. }
  552. static void __exit arc_serial_exit(void)
  553. {
  554. platform_driver_unregister(&arc_platform_driver);
  555. uart_unregister_driver(&arc_uart_driver);
  556. }
  557. module_init(arc_serial_init);
  558. module_exit(arc_serial_exit);
  559. MODULE_LICENSE("GPL");
  560. MODULE_ALIAS("platform:" DRIVER_NAME);
  561. MODULE_AUTHOR("Vineet Gupta");
  562. MODULE_DESCRIPTION("ARC(Synopsys) On-Chip(fpga) serial driver");