moxa.h 8.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #ifndef MOXA_H_FILE
  3. #define MOXA_H_FILE
  4. #define MOXA 0x400
  5. #define MOXA_GET_IQUEUE (MOXA + 1) /* get input buffered count */
  6. #define MOXA_GET_OQUEUE (MOXA + 2) /* get output buffered count */
  7. #define MOXA_GETDATACOUNT (MOXA + 23)
  8. #define MOXA_GET_IOQUEUE (MOXA + 27)
  9. #define MOXA_FLUSH_QUEUE (MOXA + 28)
  10. #define MOXA_GETMSTATUS (MOXA + 65)
  11. /*
  12. * System Configuration
  13. */
  14. #define Magic_code 0x404
  15. /*
  16. * for C218 BIOS initialization
  17. */
  18. #define C218_ConfBase 0x800
  19. #define C218_status (C218_ConfBase + 0) /* BIOS running status */
  20. #define C218_diag (C218_ConfBase + 2) /* diagnostic status */
  21. #define C218_key (C218_ConfBase + 4) /* WORD (0x218 for C218) */
  22. #define C218DLoad_len (C218_ConfBase + 6) /* WORD */
  23. #define C218check_sum (C218_ConfBase + 8) /* BYTE */
  24. #define C218chksum_ok (C218_ConfBase + 0x0a) /* BYTE (1:ok) */
  25. #define C218_TestRx (C218_ConfBase + 0x10) /* 8 bytes for 8 ports */
  26. #define C218_TestTx (C218_ConfBase + 0x18) /* 8 bytes for 8 ports */
  27. #define C218_RXerr (C218_ConfBase + 0x20) /* 8 bytes for 8 ports */
  28. #define C218_ErrFlag (C218_ConfBase + 0x28) /* 8 bytes for 8 ports */
  29. #define C218_LoadBuf 0x0F00
  30. #define C218_KeyCode 0x218
  31. #define CP204J_KeyCode 0x204
  32. /*
  33. * for C320 BIOS initialization
  34. */
  35. #define C320_ConfBase 0x800
  36. #define C320_LoadBuf 0x0f00
  37. #define STS_init 0x05 /* for C320_status */
  38. #define C320_status C320_ConfBase + 0 /* BIOS running status */
  39. #define C320_diag C320_ConfBase + 2 /* diagnostic status */
  40. #define C320_key C320_ConfBase + 4 /* WORD (0320H for C320) */
  41. #define C320DLoad_len C320_ConfBase + 6 /* WORD */
  42. #define C320check_sum C320_ConfBase + 8 /* WORD */
  43. #define C320chksum_ok C320_ConfBase + 0x0a /* WORD (1:ok) */
  44. #define C320bapi_len C320_ConfBase + 0x0c /* WORD */
  45. #define C320UART_no C320_ConfBase + 0x0e /* WORD */
  46. #define C320_KeyCode 0x320
  47. #define FixPage_addr 0x0000 /* starting addr of static page */
  48. #define DynPage_addr 0x2000 /* starting addr of dynamic page */
  49. #define C218_start 0x3000 /* starting addr of C218 BIOS prg */
  50. #define Control_reg 0x1ff0 /* select page and reset control */
  51. #define HW_reset 0x80
  52. /*
  53. * Function Codes
  54. */
  55. #define FC_CardReset 0x80
  56. #define FC_ChannelReset 1 /* C320 firmware not supported */
  57. #define FC_EnableCH 2
  58. #define FC_DisableCH 3
  59. #define FC_SetParam 4
  60. #define FC_SetMode 5
  61. #define FC_SetRate 6
  62. #define FC_LineControl 7
  63. #define FC_LineStatus 8
  64. #define FC_XmitControl 9
  65. #define FC_FlushQueue 10
  66. #define FC_SendBreak 11
  67. #define FC_StopBreak 12
  68. #define FC_LoopbackON 13
  69. #define FC_LoopbackOFF 14
  70. #define FC_ClrIrqTable 15
  71. #define FC_SendXon 16
  72. #define FC_SetTermIrq 17 /* C320 firmware not supported */
  73. #define FC_SetCntIrq 18 /* C320 firmware not supported */
  74. #define FC_SetBreakIrq 19
  75. #define FC_SetLineIrq 20
  76. #define FC_SetFlowCtl 21
  77. #define FC_GenIrq 22
  78. #define FC_InCD180 23
  79. #define FC_OutCD180 24
  80. #define FC_InUARTreg 23
  81. #define FC_OutUARTreg 24
  82. #define FC_SetXonXoff 25
  83. #define FC_OutCD180CCR 26
  84. #define FC_ExtIQueue 27
  85. #define FC_ExtOQueue 28
  86. #define FC_ClrLineIrq 29
  87. #define FC_HWFlowCtl 30
  88. #define FC_GetClockRate 35
  89. #define FC_SetBaud 36
  90. #define FC_SetDataMode 41
  91. #define FC_GetCCSR 43
  92. #define FC_GetDataError 45
  93. #define FC_RxControl 50
  94. #define FC_ImmSend 51
  95. #define FC_SetXonState 52
  96. #define FC_SetXoffState 53
  97. #define FC_SetRxFIFOTrig 54
  98. #define FC_SetTxFIFOCnt 55
  99. #define FC_UnixRate 56
  100. #define FC_UnixResetTimer 57
  101. #define RxFIFOTrig1 0
  102. #define RxFIFOTrig4 1
  103. #define RxFIFOTrig8 2
  104. #define RxFIFOTrig14 3
  105. /*
  106. * Dual-Ported RAM
  107. */
  108. #define DRAM_global 0
  109. #define INT_data (DRAM_global + 0)
  110. #define Config_base (DRAM_global + 0x108)
  111. #define IRQindex (INT_data + 0)
  112. #define IRQpending (INT_data + 4)
  113. #define IRQtable (INT_data + 8)
  114. /*
  115. * Interrupt Status
  116. */
  117. #define IntrRx 0x01 /* receiver data O.K. */
  118. #define IntrTx 0x02 /* transmit buffer empty */
  119. #define IntrFunc 0x04 /* function complete */
  120. #define IntrBreak 0x08 /* received break */
  121. #define IntrLine 0x10 /* line status change
  122. for transmitter */
  123. #define IntrIntr 0x20 /* received INTR code */
  124. #define IntrQuit 0x40 /* received QUIT code */
  125. #define IntrEOF 0x80 /* received EOF code */
  126. #define IntrRxTrigger 0x100 /* rx data count reach tigger value */
  127. #define IntrTxTrigger 0x200 /* tx data count below trigger value */
  128. #define Magic_no (Config_base + 0)
  129. #define Card_model_no (Config_base + 2)
  130. #define Total_ports (Config_base + 4)
  131. #define Module_cnt (Config_base + 8)
  132. #define Module_no (Config_base + 10)
  133. #define Timer_10ms (Config_base + 14)
  134. #define Disable_IRQ (Config_base + 20)
  135. #define TMS320_PORT1 (Config_base + 22)
  136. #define TMS320_PORT2 (Config_base + 24)
  137. #define TMS320_CLOCK (Config_base + 26)
  138. /*
  139. * DATA BUFFER in DRAM
  140. */
  141. #define Extern_table 0x400 /* Base address of the external table
  142. (24 words * 64) total 3K bytes
  143. (24 words * 128) total 6K bytes */
  144. #define Extern_size 0x60 /* 96 bytes */
  145. #define RXrptr 0x00 /* read pointer for RX buffer */
  146. #define RXwptr 0x02 /* write pointer for RX buffer */
  147. #define TXrptr 0x04 /* read pointer for TX buffer */
  148. #define TXwptr 0x06 /* write pointer for TX buffer */
  149. #define HostStat 0x08 /* IRQ flag and general flag */
  150. #define FlagStat 0x0A
  151. #define FlowControl 0x0C /* B7 B6 B5 B4 B3 B2 B1 B0 */
  152. /* x x x x | | | | */
  153. /* | | | + CTS flow */
  154. /* | | +--- RTS flow */
  155. /* | +------ TX Xon/Xoff */
  156. /* +--------- RX Xon/Xoff */
  157. #define Break_cnt 0x0E /* received break count */
  158. #define CD180TXirq 0x10 /* if non-0: enable TX irq */
  159. #define RX_mask 0x12
  160. #define TX_mask 0x14
  161. #define Ofs_rxb 0x16
  162. #define Ofs_txb 0x18
  163. #define Page_rxb 0x1A
  164. #define Page_txb 0x1C
  165. #define EndPage_rxb 0x1E
  166. #define EndPage_txb 0x20
  167. #define Data_error 0x22
  168. #define RxTrigger 0x28
  169. #define TxTrigger 0x2a
  170. #define rRXwptr 0x34
  171. #define Low_water 0x36
  172. #define FuncCode 0x40
  173. #define FuncArg 0x42
  174. #define FuncArg1 0x44
  175. #define C218rx_size 0x2000 /* 8K bytes */
  176. #define C218tx_size 0x8000 /* 32K bytes */
  177. #define C218rx_mask (C218rx_size - 1)
  178. #define C218tx_mask (C218tx_size - 1)
  179. #define C320p8rx_size 0x2000
  180. #define C320p8tx_size 0x8000
  181. #define C320p8rx_mask (C320p8rx_size - 1)
  182. #define C320p8tx_mask (C320p8tx_size - 1)
  183. #define C320p16rx_size 0x2000
  184. #define C320p16tx_size 0x4000
  185. #define C320p16rx_mask (C320p16rx_size - 1)
  186. #define C320p16tx_mask (C320p16tx_size - 1)
  187. #define C320p24rx_size 0x2000
  188. #define C320p24tx_size 0x2000
  189. #define C320p24rx_mask (C320p24rx_size - 1)
  190. #define C320p24tx_mask (C320p24tx_size - 1)
  191. #define C320p32rx_size 0x1000
  192. #define C320p32tx_size 0x1000
  193. #define C320p32rx_mask (C320p32rx_size - 1)
  194. #define C320p32tx_mask (C320p32tx_size - 1)
  195. #define Page_size 0x2000U
  196. #define Page_mask (Page_size - 1)
  197. #define C218rx_spage 3
  198. #define C218tx_spage 4
  199. #define C218rx_pageno 1
  200. #define C218tx_pageno 4
  201. #define C218buf_pageno 5
  202. #define C320p8rx_spage 3
  203. #define C320p8tx_spage 4
  204. #define C320p8rx_pgno 1
  205. #define C320p8tx_pgno 4
  206. #define C320p8buf_pgno 5
  207. #define C320p16rx_spage 3
  208. #define C320p16tx_spage 4
  209. #define C320p16rx_pgno 1
  210. #define C320p16tx_pgno 2
  211. #define C320p16buf_pgno 3
  212. #define C320p24rx_spage 3
  213. #define C320p24tx_spage 4
  214. #define C320p24rx_pgno 1
  215. #define C320p24tx_pgno 1
  216. #define C320p24buf_pgno 2
  217. #define C320p32rx_spage 3
  218. #define C320p32tx_ofs C320p32rx_size
  219. #define C320p32tx_spage 3
  220. #define C320p32buf_pgno 1
  221. /*
  222. * Host Status
  223. */
  224. #define WakeupRx 0x01
  225. #define WakeupTx 0x02
  226. #define WakeupBreak 0x08
  227. #define WakeupLine 0x10
  228. #define WakeupIntr 0x20
  229. #define WakeupQuit 0x40
  230. #define WakeupEOF 0x80 /* used in VTIME control */
  231. #define WakeupRxTrigger 0x100
  232. #define WakeupTxTrigger 0x200
  233. /*
  234. * Flag status
  235. */
  236. #define Rx_over 0x01
  237. #define Xoff_state 0x02
  238. #define Tx_flowOff 0x04
  239. #define Tx_enable 0x08
  240. #define CTS_state 0x10
  241. #define DSR_state 0x20
  242. #define DCD_state 0x80
  243. /*
  244. * FlowControl
  245. */
  246. #define CTS_FlowCtl 1
  247. #define RTS_FlowCtl 2
  248. #define Tx_FlowCtl 4
  249. #define Rx_FlowCtl 8
  250. #define IXM_IXANY 0x10
  251. #define LowWater 128
  252. #define DTR_ON 1
  253. #define RTS_ON 2
  254. #define CTS_ON 1
  255. #define DSR_ON 2
  256. #define DCD_ON 8
  257. /* mode definition */
  258. #define MX_CS8 0x03
  259. #define MX_CS7 0x02
  260. #define MX_CS6 0x01
  261. #define MX_CS5 0x00
  262. #define MX_STOP1 0x00
  263. #define MX_STOP15 0x04
  264. #define MX_STOP2 0x08
  265. #define MX_PARNONE 0x00
  266. #define MX_PAREVEN 0x40
  267. #define MX_PARODD 0xC0
  268. #define MX_PARMARK 0xA0
  269. #define MX_PARSPACE 0x20
  270. #endif