stm32-pwr.c 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (C) STMicroelectronics 2019
  3. // Authors: Gabriel Fernandez <gabriel.fernandez@st.com>
  4. // Pascal Paillet <p.paillet@st.com>.
  5. #include <linux/io.h>
  6. #include <linux/iopoll.h>
  7. #include <linux/module.h>
  8. #include <linux/of_address.h>
  9. #include <linux/of_device.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/regulator/driver.h>
  12. #include <linux/regulator/of_regulator.h>
  13. /*
  14. * Registers description
  15. */
  16. #define REG_PWR_CR3 0x0C
  17. #define USB_3_3_EN BIT(24)
  18. #define USB_3_3_RDY BIT(26)
  19. #define REG_1_8_EN BIT(28)
  20. #define REG_1_8_RDY BIT(29)
  21. #define REG_1_1_EN BIT(30)
  22. #define REG_1_1_RDY BIT(31)
  23. /* list of supported regulators */
  24. enum {
  25. PWR_REG11,
  26. PWR_REG18,
  27. PWR_USB33,
  28. STM32PWR_REG_NUM_REGS
  29. };
  30. static u32 ready_mask_table[STM32PWR_REG_NUM_REGS] = {
  31. [PWR_REG11] = REG_1_1_RDY,
  32. [PWR_REG18] = REG_1_8_RDY,
  33. [PWR_USB33] = USB_3_3_RDY,
  34. };
  35. struct stm32_pwr_reg {
  36. void __iomem *base;
  37. u32 ready_mask;
  38. };
  39. static int stm32_pwr_reg_is_ready(struct regulator_dev *rdev)
  40. {
  41. struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
  42. u32 val;
  43. val = readl_relaxed(priv->base + REG_PWR_CR3);
  44. return (val & priv->ready_mask);
  45. }
  46. static int stm32_pwr_reg_is_enabled(struct regulator_dev *rdev)
  47. {
  48. struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
  49. u32 val;
  50. val = readl_relaxed(priv->base + REG_PWR_CR3);
  51. return (val & rdev->desc->enable_mask);
  52. }
  53. static int stm32_pwr_reg_enable(struct regulator_dev *rdev)
  54. {
  55. struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
  56. int ret;
  57. u32 val;
  58. val = readl_relaxed(priv->base + REG_PWR_CR3);
  59. val |= rdev->desc->enable_mask;
  60. writel_relaxed(val, priv->base + REG_PWR_CR3);
  61. /* use an arbitrary timeout of 20ms */
  62. ret = readx_poll_timeout(stm32_pwr_reg_is_ready, rdev, val, val,
  63. 100, 20 * 1000);
  64. if (ret)
  65. dev_err(&rdev->dev, "regulator enable timed out!\n");
  66. return ret;
  67. }
  68. static int stm32_pwr_reg_disable(struct regulator_dev *rdev)
  69. {
  70. struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
  71. int ret;
  72. u32 val;
  73. val = readl_relaxed(priv->base + REG_PWR_CR3);
  74. val &= ~rdev->desc->enable_mask;
  75. writel_relaxed(val, priv->base + REG_PWR_CR3);
  76. /* use an arbitrary timeout of 20ms */
  77. ret = readx_poll_timeout(stm32_pwr_reg_is_ready, rdev, val, !val,
  78. 100, 20 * 1000);
  79. if (ret)
  80. dev_err(&rdev->dev, "regulator disable timed out!\n");
  81. return ret;
  82. }
  83. static const struct regulator_ops stm32_pwr_reg_ops = {
  84. .enable = stm32_pwr_reg_enable,
  85. .disable = stm32_pwr_reg_disable,
  86. .is_enabled = stm32_pwr_reg_is_enabled,
  87. };
  88. #define PWR_REG(_id, _name, _volt, _en, _supply) \
  89. [_id] = { \
  90. .id = _id, \
  91. .name = _name, \
  92. .of_match = of_match_ptr(_name), \
  93. .n_voltages = 1, \
  94. .type = REGULATOR_VOLTAGE, \
  95. .fixed_uV = _volt, \
  96. .ops = &stm32_pwr_reg_ops, \
  97. .enable_mask = _en, \
  98. .owner = THIS_MODULE, \
  99. .supply_name = _supply, \
  100. } \
  101. static const struct regulator_desc stm32_pwr_desc[] = {
  102. PWR_REG(PWR_REG11, "reg11", 1100000, REG_1_1_EN, "vdd"),
  103. PWR_REG(PWR_REG18, "reg18", 1800000, REG_1_8_EN, "vdd"),
  104. PWR_REG(PWR_USB33, "usb33", 3300000, USB_3_3_EN, "vdd_3v3_usbfs"),
  105. };
  106. static int stm32_pwr_regulator_probe(struct platform_device *pdev)
  107. {
  108. struct device_node *np = pdev->dev.of_node;
  109. struct stm32_pwr_reg *priv;
  110. void __iomem *base;
  111. struct regulator_dev *rdev;
  112. struct regulator_config config = { };
  113. int i, ret = 0;
  114. base = of_iomap(np, 0);
  115. if (!base) {
  116. dev_err(&pdev->dev, "Unable to map IO memory\n");
  117. return -ENOMEM;
  118. }
  119. config.dev = &pdev->dev;
  120. for (i = 0; i < STM32PWR_REG_NUM_REGS; i++) {
  121. priv = devm_kzalloc(&pdev->dev, sizeof(struct stm32_pwr_reg),
  122. GFP_KERNEL);
  123. if (!priv)
  124. return -ENOMEM;
  125. priv->base = base;
  126. priv->ready_mask = ready_mask_table[i];
  127. config.driver_data = priv;
  128. rdev = devm_regulator_register(&pdev->dev,
  129. &stm32_pwr_desc[i],
  130. &config);
  131. if (IS_ERR(rdev)) {
  132. ret = PTR_ERR(rdev);
  133. dev_err(&pdev->dev,
  134. "Failed to register regulator: %d\n", ret);
  135. break;
  136. }
  137. }
  138. return ret;
  139. }
  140. static const struct of_device_id stm32_pwr_of_match[] = {
  141. { .compatible = "st,stm32mp1,pwr-reg", },
  142. {},
  143. };
  144. MODULE_DEVICE_TABLE(of, stm32_pwr_of_match);
  145. static struct platform_driver stm32_pwr_driver = {
  146. .probe = stm32_pwr_regulator_probe,
  147. .driver = {
  148. .name = "stm32-pwr-regulator",
  149. .of_match_table = of_match_ptr(stm32_pwr_of_match),
  150. },
  151. };
  152. module_platform_driver(stm32_pwr_driver);
  153. MODULE_DESCRIPTION("STM32MP1 PWR voltage regulator driver");
  154. MODULE_AUTHOR("Pascal Paillet <p.paillet@st.com>");
  155. MODULE_LICENSE("GPL v2");