slg51000-regulator.h 23 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * SLG51000 High PSRR, Multi-Output Regulators
  4. * Copyright (C) 2019 Dialog Semiconductor
  5. *
  6. * Author: Eric Jeong <eric.jeong.opensource@diasemi.com>
  7. */
  8. #ifndef __SLG51000_REGISTERS_H__
  9. #define __SLG51000_REGISTERS_H__
  10. /* Registers */
  11. #define SLG51000_SYSCTL_PATN_ID_B0 0x1105
  12. #define SLG51000_SYSCTL_PATN_ID_B1 0x1106
  13. #define SLG51000_SYSCTL_PATN_ID_B2 0x1107
  14. #define SLG51000_SYSCTL_SYS_CONF_A 0x1109
  15. #define SLG51000_SYSCTL_SYS_CONF_D 0x110c
  16. #define SLG51000_SYSCTL_MATRIX_CONF_A 0x110d
  17. #define SLG51000_SYSCTL_MATRIX_CONF_B 0x110e
  18. #define SLG51000_SYSCTL_REFGEN_CONF_C 0x1111
  19. #define SLG51000_SYSCTL_UVLO_CONF_A 0x1112
  20. #define SLG51000_SYSCTL_FAULT_LOG1 0x1115
  21. #define SLG51000_SYSCTL_EVENT 0x1116
  22. #define SLG51000_SYSCTL_STATUS 0x1117
  23. #define SLG51000_SYSCTL_IRQ_MASK 0x1118
  24. #define SLG51000_IO_GPIO1_CONF 0x1500
  25. #define SLG51000_IO_GPIO2_CONF 0x1501
  26. #define SLG51000_IO_GPIO3_CONF 0x1502
  27. #define SLG51000_IO_GPIO4_CONF 0x1503
  28. #define SLG51000_IO_GPIO5_CONF 0x1504
  29. #define SLG51000_IO_GPIO6_CONF 0x1505
  30. #define SLG51000_IO_GPIO_STATUS 0x1506
  31. #define SLG51000_LUTARRAY_LUT_VAL_0 0x1600
  32. #define SLG51000_LUTARRAY_LUT_VAL_1 0x1601
  33. #define SLG51000_LUTARRAY_LUT_VAL_2 0x1602
  34. #define SLG51000_LUTARRAY_LUT_VAL_3 0x1603
  35. #define SLG51000_LUTARRAY_LUT_VAL_4 0x1604
  36. #define SLG51000_LUTARRAY_LUT_VAL_5 0x1605
  37. #define SLG51000_LUTARRAY_LUT_VAL_6 0x1606
  38. #define SLG51000_LUTARRAY_LUT_VAL_7 0x1607
  39. #define SLG51000_LUTARRAY_LUT_VAL_8 0x1608
  40. #define SLG51000_LUTARRAY_LUT_VAL_9 0x1609
  41. #define SLG51000_LUTARRAY_LUT_VAL_10 0x160a
  42. #define SLG51000_LUTARRAY_LUT_VAL_11 0x160b
  43. #define SLG51000_MUXARRAY_INPUT_SEL_0 0x1700
  44. #define SLG51000_MUXARRAY_INPUT_SEL_1 0x1701
  45. #define SLG51000_MUXARRAY_INPUT_SEL_2 0x1702
  46. #define SLG51000_MUXARRAY_INPUT_SEL_3 0x1703
  47. #define SLG51000_MUXARRAY_INPUT_SEL_4 0x1704
  48. #define SLG51000_MUXARRAY_INPUT_SEL_5 0x1705
  49. #define SLG51000_MUXARRAY_INPUT_SEL_6 0x1706
  50. #define SLG51000_MUXARRAY_INPUT_SEL_7 0x1707
  51. #define SLG51000_MUXARRAY_INPUT_SEL_8 0x1708
  52. #define SLG51000_MUXARRAY_INPUT_SEL_9 0x1709
  53. #define SLG51000_MUXARRAY_INPUT_SEL_10 0x170a
  54. #define SLG51000_MUXARRAY_INPUT_SEL_11 0x170b
  55. #define SLG51000_MUXARRAY_INPUT_SEL_12 0x170c
  56. #define SLG51000_MUXARRAY_INPUT_SEL_13 0x170d
  57. #define SLG51000_MUXARRAY_INPUT_SEL_14 0x170e
  58. #define SLG51000_MUXARRAY_INPUT_SEL_15 0x170f
  59. #define SLG51000_MUXARRAY_INPUT_SEL_16 0x1710
  60. #define SLG51000_MUXARRAY_INPUT_SEL_17 0x1711
  61. #define SLG51000_MUXARRAY_INPUT_SEL_18 0x1712
  62. #define SLG51000_MUXARRAY_INPUT_SEL_19 0x1713
  63. #define SLG51000_MUXARRAY_INPUT_SEL_20 0x1714
  64. #define SLG51000_MUXARRAY_INPUT_SEL_21 0x1715
  65. #define SLG51000_MUXARRAY_INPUT_SEL_22 0x1716
  66. #define SLG51000_MUXARRAY_INPUT_SEL_23 0x1717
  67. #define SLG51000_MUXARRAY_INPUT_SEL_24 0x1718
  68. #define SLG51000_MUXARRAY_INPUT_SEL_25 0x1719
  69. #define SLG51000_MUXARRAY_INPUT_SEL_26 0x171a
  70. #define SLG51000_MUXARRAY_INPUT_SEL_27 0x171b
  71. #define SLG51000_MUXARRAY_INPUT_SEL_28 0x171c
  72. #define SLG51000_MUXARRAY_INPUT_SEL_29 0x171d
  73. #define SLG51000_MUXARRAY_INPUT_SEL_30 0x171e
  74. #define SLG51000_MUXARRAY_INPUT_SEL_31 0x171f
  75. #define SLG51000_MUXARRAY_INPUT_SEL_32 0x1720
  76. #define SLG51000_MUXARRAY_INPUT_SEL_33 0x1721
  77. #define SLG51000_MUXARRAY_INPUT_SEL_34 0x1722
  78. #define SLG51000_MUXARRAY_INPUT_SEL_35 0x1723
  79. #define SLG51000_MUXARRAY_INPUT_SEL_36 0x1724
  80. #define SLG51000_MUXARRAY_INPUT_SEL_37 0x1725
  81. #define SLG51000_MUXARRAY_INPUT_SEL_38 0x1726
  82. #define SLG51000_MUXARRAY_INPUT_SEL_39 0x1727
  83. #define SLG51000_MUXARRAY_INPUT_SEL_40 0x1728
  84. #define SLG51000_MUXARRAY_INPUT_SEL_41 0x1729
  85. #define SLG51000_MUXARRAY_INPUT_SEL_42 0x172a
  86. #define SLG51000_MUXARRAY_INPUT_SEL_43 0x172b
  87. #define SLG51000_MUXARRAY_INPUT_SEL_44 0x172c
  88. #define SLG51000_MUXARRAY_INPUT_SEL_45 0x172d
  89. #define SLG51000_MUXARRAY_INPUT_SEL_46 0x172e
  90. #define SLG51000_MUXARRAY_INPUT_SEL_47 0x172f
  91. #define SLG51000_MUXARRAY_INPUT_SEL_48 0x1730
  92. #define SLG51000_MUXARRAY_INPUT_SEL_49 0x1731
  93. #define SLG51000_MUXARRAY_INPUT_SEL_50 0x1732
  94. #define SLG51000_MUXARRAY_INPUT_SEL_51 0x1733
  95. #define SLG51000_MUXARRAY_INPUT_SEL_52 0x1734
  96. #define SLG51000_MUXARRAY_INPUT_SEL_53 0x1735
  97. #define SLG51000_MUXARRAY_INPUT_SEL_54 0x1736
  98. #define SLG51000_MUXARRAY_INPUT_SEL_55 0x1737
  99. #define SLG51000_MUXARRAY_INPUT_SEL_56 0x1738
  100. #define SLG51000_MUXARRAY_INPUT_SEL_57 0x1739
  101. #define SLG51000_MUXARRAY_INPUT_SEL_58 0x173a
  102. #define SLG51000_MUXARRAY_INPUT_SEL_59 0x173b
  103. #define SLG51000_MUXARRAY_INPUT_SEL_60 0x173c
  104. #define SLG51000_MUXARRAY_INPUT_SEL_61 0x173d
  105. #define SLG51000_MUXARRAY_INPUT_SEL_62 0x173e
  106. #define SLG51000_MUXARRAY_INPUT_SEL_63 0x173f
  107. #define SLG51000_PWRSEQ_RESOURCE_EN_0 0x1900
  108. #define SLG51000_PWRSEQ_RESOURCE_EN_1 0x1901
  109. #define SLG51000_PWRSEQ_RESOURCE_EN_2 0x1902
  110. #define SLG51000_PWRSEQ_RESOURCE_EN_3 0x1903
  111. #define SLG51000_PWRSEQ_RESOURCE_EN_4 0x1904
  112. #define SLG51000_PWRSEQ_RESOURCE_EN_5 0x1905
  113. #define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP0 0x1906
  114. #define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN0 0x1907
  115. #define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP1 0x1908
  116. #define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN1 0x1909
  117. #define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP2 0x190a
  118. #define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN2 0x190b
  119. #define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP3 0x190c
  120. #define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN3 0x190d
  121. #define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP4 0x190e
  122. #define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN4 0x190f
  123. #define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP5 0x1910
  124. #define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN5 0x1911
  125. #define SLG51000_PWRSEQ_SLOT_TIME_MAX_CONF_A 0x1912
  126. #define SLG51000_PWRSEQ_SLOT_TIME_MAX_CONF_B 0x1913
  127. #define SLG51000_PWRSEQ_SLOT_TIME_MAX_CONF_C 0x1914
  128. #define SLG51000_PWRSEQ_INPUT_SENSE_CONF_A 0x1915
  129. #define SLG51000_PWRSEQ_INPUT_SENSE_CONF_B 0x1916
  130. #define SLG51000_LDO1_VSEL 0x2000
  131. #define SLG51000_LDO1_MINV 0x2060
  132. #define SLG51000_LDO1_MAXV 0x2061
  133. #define SLG51000_LDO1_MISC1 0x2064
  134. #define SLG51000_LDO1_VSEL_ACTUAL 0x2065
  135. #define SLG51000_LDO1_EVENT 0x20c0
  136. #define SLG51000_LDO1_STATUS 0x20c1
  137. #define SLG51000_LDO1_IRQ_MASK 0x20c2
  138. #define SLG51000_LDO2_VSEL 0x2200
  139. #define SLG51000_LDO2_MINV 0x2260
  140. #define SLG51000_LDO2_MAXV 0x2261
  141. #define SLG51000_LDO2_MISC1 0x2264
  142. #define SLG51000_LDO2_VSEL_ACTUAL 0x2265
  143. #define SLG51000_LDO2_EVENT 0x22c0
  144. #define SLG51000_LDO2_STATUS 0x22c1
  145. #define SLG51000_LDO2_IRQ_MASK 0x22c2
  146. #define SLG51000_LDO3_VSEL 0x2300
  147. #define SLG51000_LDO3_MINV 0x2360
  148. #define SLG51000_LDO3_MAXV 0x2361
  149. #define SLG51000_LDO3_CONF1 0x2364
  150. #define SLG51000_LDO3_CONF2 0x2365
  151. #define SLG51000_LDO3_VSEL_ACTUAL 0x2366
  152. #define SLG51000_LDO3_EVENT 0x23c0
  153. #define SLG51000_LDO3_STATUS 0x23c1
  154. #define SLG51000_LDO3_IRQ_MASK 0x23c2
  155. #define SLG51000_LDO4_VSEL 0x2500
  156. #define SLG51000_LDO4_MINV 0x2560
  157. #define SLG51000_LDO4_MAXV 0x2561
  158. #define SLG51000_LDO4_CONF1 0x2564
  159. #define SLG51000_LDO4_CONF2 0x2565
  160. #define SLG51000_LDO4_VSEL_ACTUAL 0x2566
  161. #define SLG51000_LDO4_EVENT 0x25c0
  162. #define SLG51000_LDO4_STATUS 0x25c1
  163. #define SLG51000_LDO4_IRQ_MASK 0x25c2
  164. #define SLG51000_LDO5_VSEL 0x2700
  165. #define SLG51000_LDO5_MINV 0x2760
  166. #define SLG51000_LDO5_MAXV 0x2761
  167. #define SLG51000_LDO5_TRIM2 0x2763
  168. #define SLG51000_LDO5_CONF1 0x2765
  169. #define SLG51000_LDO5_CONF2 0x2766
  170. #define SLG51000_LDO5_VSEL_ACTUAL 0x2767
  171. #define SLG51000_LDO5_EVENT 0x27c0
  172. #define SLG51000_LDO5_STATUS 0x27c1
  173. #define SLG51000_LDO5_IRQ_MASK 0x27c2
  174. #define SLG51000_LDO6_VSEL 0x2900
  175. #define SLG51000_LDO6_MINV 0x2960
  176. #define SLG51000_LDO6_MAXV 0x2961
  177. #define SLG51000_LDO6_TRIM2 0x2963
  178. #define SLG51000_LDO6_CONF1 0x2965
  179. #define SLG51000_LDO6_CONF2 0x2966
  180. #define SLG51000_LDO6_VSEL_ACTUAL 0x2967
  181. #define SLG51000_LDO6_EVENT 0x29c0
  182. #define SLG51000_LDO6_STATUS 0x29c1
  183. #define SLG51000_LDO6_IRQ_MASK 0x29c2
  184. #define SLG51000_LDO7_VSEL 0x3100
  185. #define SLG51000_LDO7_MINV 0x3160
  186. #define SLG51000_LDO7_MAXV 0x3161
  187. #define SLG51000_LDO7_CONF1 0x3164
  188. #define SLG51000_LDO7_CONF2 0x3165
  189. #define SLG51000_LDO7_VSEL_ACTUAL 0x3166
  190. #define SLG51000_LDO7_EVENT 0x31c0
  191. #define SLG51000_LDO7_STATUS 0x31c1
  192. #define SLG51000_LDO7_IRQ_MASK 0x31c2
  193. #define SLG51000_OTP_EVENT 0x782b
  194. #define SLG51000_OTP_IRQ_MASK 0x782d
  195. #define SLG51000_OTP_LOCK_OTP_PROG 0x78fe
  196. #define SLG51000_OTP_LOCK_CTRL 0x78ff
  197. #define SLG51000_LOCK_GLOBAL_LOCK_CTRL1 0x8000
  198. /* Register Bit Fields */
  199. /* SLG51000_SYSCTL_PATTERN_ID_BYTE0 = 0x1105 */
  200. #define SLG51000_PATTERN_ID_BYTE0_SHIFT 0
  201. #define SLG51000_PATTERN_ID_BYTE0_MASK (0xff << 0)
  202. /* SLG51000_SYSCTL_PATTERN_ID_BYTE1 = 0x1106 */
  203. #define SLG51000_PATTERN_ID_BYTE1_SHIFT 0
  204. #define SLG51000_PATTERN_ID_BYTE1_MASK (0xff << 0)
  205. /* SLG51000_SYSCTL_PATTERN_ID_BYTE2 = 0x1107 */
  206. #define SLG51000_PATTERN_ID_BYTE2_SHIFT 0
  207. #define SLG51000_PATTERN_ID_BYTE2_MASK (0xff << 0)
  208. /* SLG51000_SYSCTL_SYS_CONF_A = 0x1109 */
  209. #define SLG51000_I2C_ADDRESS_SHIFT 0
  210. #define SLG51000_I2C_ADDRESS_MASK (0x7f << 0)
  211. #define SLG51000_I2C_DISABLE_SHIFT 7
  212. #define SLG51000_I2C_DISABLE_MASK (0x01 << 7)
  213. /* SLG51000_SYSCTL_SYS_CONF_D = 0x110c */
  214. #define SLG51000_CS_T_DEB_SHIFT 6
  215. #define SLG51000_CS_T_DEB_MASK (0x03 << 6)
  216. #define SLG51000_I2C_CLR_MODE_SHIFT 5
  217. #define SLG51000_I2C_CLR_MODE_MASK (0x01 << 5)
  218. /* SLG51000_SYSCTL_MATRIX_CTRL_CONF_A = 0x110d */
  219. #define SLG51000_RESOURCE_CTRL_SHIFT 0
  220. #define SLG51000_RESOURCE_CTRL_MASK (0xff << 0)
  221. /* SLG51000_SYSCTL_MATRIX_CTRL_CONF_B = 0x110e */
  222. #define SLG51000_MATRIX_EVENT_SENSE_SHIFT 0
  223. #define SLG51000_MATRIX_EVENT_SENSE_MASK (0x07 << 0)
  224. /* SLG51000_SYSCTL_REFGEN_CONF_C = 0x1111 */
  225. #define SLG51000_REFGEN_SEL_TEMP_WARN_DEBOUNCE_SHIFT 2
  226. #define SLG51000_REFGEN_SEL_TEMP_WARN_DEBOUNCE_MASK (0x03 << 2)
  227. #define SLG51000_REFGEN_SEL_TEMP_WARN_THR_SHIFT 0
  228. #define SLG51000_REFGEN_SEL_TEMP_WARN_THR_MASK (0x03 << 0)
  229. /* SLG51000_SYSCTL_UVLO_CONF_A = 0x1112 */
  230. #define SLG51000_VMON_UVLO_SEL_THR_SHIFT 0
  231. #define SLG51000_VMON_UVLO_SEL_THR_MASK (0x1f << 0)
  232. /* SLG51000_SYSCTL_FAULT_LOG1 = 0x1115 */
  233. #define SLG51000_FLT_POR_SHIFT 5
  234. #define SLG51000_FLT_POR_MASK (0x01 << 5)
  235. #define SLG51000_FLT_RST_SHIFT 4
  236. #define SLG51000_FLT_RST_MASK (0x01 << 4)
  237. #define SLG51000_FLT_POWER_SEQ_CRASH_REQ_SHIFT 2
  238. #define SLG51000_FLT_POWER_SEQ_CRASH_REQ_MASK (0x01 << 2)
  239. #define SLG51000_FLT_OVER_TEMP_SHIFT 1
  240. #define SLG51000_FLT_OVER_TEMP_MASK (0x01 << 1)
  241. /* SLG51000_SYSCTL_EVENT = 0x1116 */
  242. #define SLG51000_EVT_MATRIX_SHIFT 1
  243. #define SLG51000_EVT_MATRIX_MASK (0x01 << 1)
  244. #define SLG51000_EVT_HIGH_TEMP_WARN_SHIFT 0
  245. #define SLG51000_EVT_HIGH_TEMP_WARN_MASK (0x01 << 0)
  246. /* SLG51000_SYSCTL_STATUS = 0x1117 */
  247. #define SLG51000_STA_MATRIX_SHIFT 1
  248. #define SLG51000_STA_MATRIX_MASK (0x01 << 1)
  249. #define SLG51000_STA_HIGH_TEMP_WARN_SHIFT 0
  250. #define SLG51000_STA_HIGH_TEMP_WARN_MASK (0x01 << 0)
  251. /* SLG51000_SYSCTL_IRQ_MASK = 0x1118 */
  252. #define SLG51000_IRQ_MATRIX_SHIFT 1
  253. #define SLG51000_IRQ_MATRIX_MASK (0x01 << 1)
  254. #define SLG51000_IRQ_HIGH_TEMP_WARN_SHIFT 0
  255. #define SLG51000_IRQ_HIGH_TEMP_WARN_MASK (0x01 << 0)
  256. /* SLG51000_IO_GPIO1_CONF ~ SLG51000_IO_GPIO5_CONF =
  257. * 0x1500, 0x1501, 0x1502, 0x1503, 0x1504
  258. */
  259. #define SLG51000_GPIO_DIR_SHIFT 7
  260. #define SLG51000_GPIO_DIR_MASK (0x01 << 7)
  261. #define SLG51000_GPIO_SENS_SHIFT 5
  262. #define SLG51000_GPIO_SENS_MASK (0x03 << 5)
  263. #define SLG51000_GPIO_INVERT_SHIFT 4
  264. #define SLG51000_GPIO_INVERT_MASK (0x01 << 4)
  265. #define SLG51000_GPIO_BYP_SHIFT 3
  266. #define SLG51000_GPIO_BYP_MASK (0x01 << 3)
  267. #define SLG51000_GPIO_T_DEB_SHIFT 1
  268. #define SLG51000_GPIO_T_DEB_MASK (0x03 << 1)
  269. #define SLG51000_GPIO_LEVEL_SHIFT 0
  270. #define SLG51000_GPIO_LEVEL_MASK (0x01 << 0)
  271. /* SLG51000_IO_GPIO6_CONF = 0x1505 */
  272. #define SLG51000_GPIO6_SENS_SHIFT 5
  273. #define SLG51000_GPIO6_SENS_MASK (0x03 << 5)
  274. #define SLG51000_GPIO6_INVERT_SHIFT 4
  275. #define SLG51000_GPIO6_INVERT_MASK (0x01 << 4)
  276. #define SLG51000_GPIO6_T_DEB_SHIFT 1
  277. #define SLG51000_GPIO6_T_DEB_MASK (0x03 << 1)
  278. #define SLG51000_GPIO6_LEVEL_SHIFT 0
  279. #define SLG51000_GPIO6_LEVEL_MASK (0x01 << 0)
  280. /* SLG51000_IO_GPIO_STATUS = 0x1506 */
  281. #define SLG51000_GPIO6_STATUS_SHIFT 5
  282. #define SLG51000_GPIO6_STATUS_MASK (0x01 << 5)
  283. #define SLG51000_GPIO5_STATUS_SHIFT 4
  284. #define SLG51000_GPIO5_STATUS_MASK (0x01 << 4)
  285. #define SLG51000_GPIO4_STATUS_SHIFT 3
  286. #define SLG51000_GPIO4_STATUS_MASK (0x01 << 3)
  287. #define SLG51000_GPIO3_STATUS_SHIFT 2
  288. #define SLG51000_GPIO3_STATUS_MASK (0x01 << 2)
  289. #define SLG51000_GPIO2_STATUS_SHIFT 1
  290. #define SLG51000_GPIO2_STATUS_MASK (0x01 << 1)
  291. #define SLG51000_GPIO1_STATUS_SHIFT 0
  292. #define SLG51000_GPIO1_STATUS_MASK (0x01 << 0)
  293. /* SLG51000_LUTARRAY_LUT_VAL_0 ~ SLG51000_LUTARRAY_LUT_VAL_11
  294. * 0x1600, 0x1601, 0x1602, 0x1603, 0x1604, 0x1605,
  295. * 0x1606, 0x1607, 0x1608, 0x1609, 0x160a, 0x160b
  296. */
  297. #define SLG51000_LUT_VAL_SHIFT 0
  298. #define SLG51000_LUT_VAL_MASK (0xff << 0)
  299. /* SLG51000_MUXARRAY_INPUT_SEL_0 ~ SLG51000_MUXARRAY_INPUT_SEL_63
  300. * 0x1700, 0x1701, 0x1702, 0x1703, 0x1704, 0x1705,
  301. * 0x1706, 0x1707, 0x1708, 0x1709, 0x170a, 0x170b,
  302. * 0x170c, 0x170d, 0x170e, 0x170f, 0x1710, 0x1711,
  303. * 0x1712, 0x1713, 0x1714, 0x1715, 0x1716, 0x1717,
  304. * 0x1718, 0x1719, 0x171a, 0x171b, 0x171c, 0x171d,
  305. * 0x171e, 0x171f, 0x1720, 0x1721, 0x1722, 0x1723,
  306. * 0x1724, 0x1725, 0x1726, 0x1727, 0x1728, 0x1729,
  307. * 0x173a, 0x173b, 0x173c, 0x173d, 0x173e, 0x173f,
  308. */
  309. #define SLG51000_INPUT_SEL_SHIFT 0
  310. #define SLG51000_INPUT_SEL_MASK (0x3f << 0)
  311. /* SLG51000_PWRSEQ_RESOURCE_EN_0 ~ SLG51000_PWRSEQ_RESOURCE_EN_5
  312. * 0x1900, 0x1901, 0x1902, 0x1903, 0x1904, 0x1905
  313. */
  314. #define SLG51000_RESOURCE_EN_DOWN0_SHIFT 4
  315. #define SLG51000_RESOURCE_EN_DOWN0_MASK (0x07 << 4)
  316. #define SLG51000_RESOURCE_EN_UP0_SHIFT 0
  317. #define SLG51000_RESOURCE_EN_UP0_MASK (0x07 << 0)
  318. /* SLG51000_PWRSEQ_SLOT_TIME_MIN_UP0 ~ SLG51000_PWRSEQ_SLOT_TIME_MIN_UP5
  319. * 0x1906, 0x1908, 0x190a, 0x190c, 0x190e, 0x1910
  320. */
  321. #define SLG51000_SLOT_TIME_MIN_UP_SHIFT 0
  322. #define SLG51000_SLOT_TIME_MIN_UP_MASK (0xff << 0)
  323. /* SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN0 ~ SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN5
  324. * 0x1907, 0x1909, 0x190b, 0x190d, 0x190f, 0x1911
  325. */
  326. #define SLG51000_SLOT_TIME_MIN_DOWN_SHIFT 0
  327. #define SLG51000_SLOT_TIME_MIN_DOWN_MASK (0xff << 0)
  328. /* SLG51000_PWRSEQ_SLOT_TIME_MAX_CONF_A ~ SLG51000_PWRSEQ_SLOT_TIME_MAX_CONF_C
  329. * 0x1912, 0x1913, 0x1914
  330. */
  331. #define SLG51000_SLOT_TIME_MAX_DOWN1_SHIFT 6
  332. #define SLG51000_SLOT_TIME_MAX_DOWN1_MASK (0x03 << 6)
  333. #define SLG51000_SLOT_TIME_MAX_UP1_SHIFT 4
  334. #define SLG51000_SLOT_TIME_MAX_UP1_MASK (0x03 << 4)
  335. #define SLG51000_SLOT_TIME_MAX_DOWN0_SHIFT 2
  336. #define SLG51000_SLOT_TIME_MAX_DOWN0_MASK (0x03 << 2)
  337. #define SLG51000_SLOT_TIME_MAX_UP0_SHIFT 0
  338. #define SLG51000_SLOT_TIME_MAX_UP0_MASK (0x03 << 0)
  339. /* SLG51000_PWRSEQ_INPUT_SENSE_CONF_A = 0x1915 */
  340. #define SLG51000_TRIG_UP_SENSE_SHIFT 6
  341. #define SLG51000_TRIG_UP_SENSE_MASK (0x01 << 6)
  342. #define SLG51000_UP_EN_SENSE5_SHIFT 5
  343. #define SLG51000_UP_EN_SENSE5_MASK (0x01 << 5)
  344. #define SLG51000_UP_EN_SENSE4_SHIFT 4
  345. #define SLG51000_UP_EN_SENSE4_MASK (0x01 << 4)
  346. #define SLG51000_UP_EN_SENSE3_SHIFT 3
  347. #define SLG51000_UP_EN_SENSE3_MASK (0x01 << 3)
  348. #define SLG51000_UP_EN_SENSE2_SHIFT 2
  349. #define SLG51000_UP_EN_SENSE2_MASK (0x01 << 2)
  350. #define SLG51000_UP_EN_SENSE1_SHIFT 1
  351. #define SLG51000_UP_EN_SENSE1_MASK (0x01 << 1)
  352. #define SLG51000_UP_EN_SENSE0_SHIFT 0
  353. #define SLG51000_UP_EN_SENSE0_MASK (0x01 << 0)
  354. /* SLG51000_PWRSEQ_INPUT_SENSE_CONF_B = 0x1916 */
  355. #define SLG51000_CRASH_DETECT_SENSE_SHIFT 7
  356. #define SLG51000_CRASH_DETECT_SENSE_MASK (0x01 << 7)
  357. #define SLG51000_TRIG_DOWN_SENSE_SHIFT 6
  358. #define SLG51000_TRIG_DOWN_SENSE_MASK (0x01 << 6)
  359. #define SLG51000_DOWN_EN_SENSE5_SHIFT 5
  360. #define SLG51000_DOWN_EN_SENSE5_MASK (0x01 << 5)
  361. #define SLG51000_DOWN_EN_SENSE4_SHIFT 4
  362. #define SLG51000_DOWN_EN_SENSE4_MASK (0x01 << 4)
  363. #define SLG51000_DOWN_EN_SENSE3_SHIFT 3
  364. #define SLG51000_DOWN_EN_SENSE3_MASK (0x01 << 3)
  365. #define SLG51000_DOWN_EN_SENSE2_SHIFT 2
  366. #define SLG51000_DOWN_EN_SENSE2_MASK (0x01 << 2)
  367. #define SLG51000_DOWN_EN_SENSE1_SHIFT 1
  368. #define SLG51000_DOWN_EN_SENSE1_MASK (0x01 << 1)
  369. #define SLG51000_DOWN_EN_SENSE0_SHIFT 0
  370. #define SLG51000_DOWN_EN_SENSE0_MASK (0x01 << 0)
  371. /* SLG51000_LDO1_VSEL ~ SLG51000_LDO7_VSEL =
  372. * 0x2000, 0x2200, 0x2300, 0x2500, 0x2700, 0x2900, 0x3100
  373. */
  374. #define SLG51000_VSEL_SHIFT 0
  375. #define SLG51000_VSEL_MASK (0xff << 0)
  376. /* SLG51000_LDO1_MINV ~ SLG51000_LDO7_MINV =
  377. * 0x2060, 0x2260, 0x2360, 0x2560, 0x2760, 0x2960, 0x3160
  378. */
  379. #define SLG51000_MINV_SHIFT 0
  380. #define SLG51000_MINV_MASK (0xff << 0)
  381. /* SLG51000_LDO1_MAXV ~ SLG51000_LDO7_MAXV =
  382. * 0x2061, 0x2261, 0x2361, 0x2561, 0x2761, 0x2961, 0x3161
  383. */
  384. #define SLG51000_MAXV_SHIFT 0
  385. #define SLG51000_MAXV_MASK (0xff << 0)
  386. /* SLG51000_LDO1_MISC1 = 0x2064, SLG51000_LDO2_MISC1 = 0x2264 */
  387. #define SLG51000_SEL_VRANGE_SHIFT 0
  388. #define SLG51000_SEL_VRANGE_MASK (0x01 << 0)
  389. /* SLG51000_LDO1_VSEL_ACTUAL ~ SLG51000_LDO7_VSEL_ACTUAL =
  390. * 0x2065, 0x2265, 0x2366, 0x2566, 0x2767, 0x2967, 0x3166
  391. */
  392. #define SLG51000_VSEL_ACTUAL_SHIFT 0
  393. #define SLG51000_VSEL_ACTUAL_MASK (0xff << 0)
  394. /* SLG51000_LDO1_EVENT ~ SLG51000_LDO7_EVENT =
  395. * 0x20c0, 0x22c0, 0x23c0, 0x25c0, 0x27c0, 0x29c0, 0x31c0
  396. */
  397. #define SLG51000_EVT_ILIM_FLAG_SHIFT 0
  398. #define SLG51000_EVT_ILIM_FLAG_MASK (0x01 << 0)
  399. #define SLG51000_EVT_VOUT_OK_FLAG_SHIFT 1
  400. #define SLG51000_EVT_VOUT_OK_FLAG_MASK (0x01 << 1)
  401. /* SLG51000_LDO1_STATUS ~ SLG51000_LDO7_STATUS =
  402. * 0x20c1, 0x22c1, 0x23c1, 0x25c1, 0x27c1, 0x29c1, 0x31c1
  403. */
  404. #define SLG51000_STA_ILIM_FLAG_SHIFT 0
  405. #define SLG51000_STA_ILIM_FLAG_MASK (0x01 << 0)
  406. #define SLG51000_STA_VOUT_OK_FLAG_SHIFT 1
  407. #define SLG51000_STA_VOUT_OK_FLAG_MASK (0x01 << 1)
  408. /* SLG51000_LDO1_IRQ_MASK ~ SLG51000_LDO7_IRQ_MASK =
  409. * 0x20c2, 0x22c2, 0x23c2, 0x25c2, 0x27c2, 0x29c2, 0x31c2
  410. */
  411. #define SLG51000_IRQ_ILIM_FLAG_SHIFT 0
  412. #define SLG51000_IRQ_ILIM_FLAG_MASK (0x01 << 0)
  413. /* SLG51000_LDO3_CONF1 ~ SLG51000_LDO7_CONF1 =
  414. * 0x2364, 0x2564, 0x2765, 0x2965, 0x3164
  415. */
  416. #define SLG51000_SEL_START_ILIM_SHIFT 0
  417. #define SLG51000_SEL_START_ILIM_MASK (0x7f << 0)
  418. /* SLG51000_LDO3_CONF2 ~ SLG51000_LDO7_CONF2 =
  419. * 0x2365, 0x2565, 0x2766, 0x2966, 0x3165
  420. */
  421. #define SLG51000_SEL_FUNC_ILIM_SHIFT 0
  422. #define SLG51000_SEL_FUNC_ILIM_MASK (0x7f << 0)
  423. /* SLG51000_LDO5_TRIM2 = 0x2763, SLG51000_LDO6_TRIM2 = 0x2963 */
  424. #define SLG51000_SEL_BYP_SLEW_RATE_SHIFT 2
  425. #define SLG51000_SEL_BYP_SLEW_RATE_MASK (0x03 << 2)
  426. #define SLG51000_SEL_BYP_VGATE_SHIFT 1
  427. #define SLG51000_SEL_BYP_VGATE_MASK (0x01 << 1)
  428. #define SLG51000_SEL_BYP_MODE_SHIFT 0
  429. #define SLG51000_SEL_BYP_MODE_MASK (0x01 << 0)
  430. /* SLG51000_OTP_EVENT = 0x782b */
  431. #define SLG51000_EVT_CRC_SHIFT 0
  432. #define SLG51000_EVT_CRC_MASK (0x01 << 0)
  433. /* SLG51000_OTP_IRQ_MASK = 0x782d */
  434. #define SLG51000_IRQ_CRC_SHIFT 0
  435. #define SLG51000_IRQ_CRC_MASK (0x01 << 0)
  436. /* SLG51000_OTP_LOCK_OTP_PROG = 0x78fe */
  437. #define SLG51000_LOCK_OTP_PROG_SHIFT 0
  438. #define SLG51000_LOCK_OTP_PROG_MASK (0x01 << 0)
  439. /* SLG51000_OTP_LOCK_CTRL = 0x78ff */
  440. #define SLG51000_LOCK_DFT_SHIFT 1
  441. #define SLG51000_LOCK_DFT_MASK (0x01 << 1)
  442. #define SLG51000_LOCK_RWT_SHIFT 0
  443. #define SLG51000_LOCK_RWT_MASK (0x01 << 0)
  444. /* SLG51000_LOCK_GLOBAL_LOCK_CTRL1 = 0x8000 */
  445. #define SLG51000_LDO7_LOCK_SHIFT 7
  446. #define SLG51000_LDO7_LOCK_MASK (0x01 << 7)
  447. #define SLG51000_LDO6_LOCK_SHIFT 6
  448. #define SLG51000_LDO6_LOCK_MASK (0x01 << 6)
  449. #define SLG51000_LDO5_LOCK_SHIFT 5
  450. #define SLG51000_LDO5_LOCK_MASK (0x01 << 5)
  451. #define SLG51000_LDO4_LOCK_SHIFT 4
  452. #define SLG51000_LDO4_LOCK_MASK (0x01 << 4)
  453. #define SLG51000_LDO3_LOCK_SHIFT 3
  454. #define SLG51000_LDO3_LOCK_MASK (0x01 << 3)
  455. #define SLG51000_LDO2_LOCK_SHIFT 2
  456. #define SLG51000_LDO2_LOCK_MASK (0x01 << 2)
  457. #define SLG51000_LDO1_LOCK_SHIFT 1
  458. #define SLG51000_LDO1_LOCK_MASK (0x01 << 1)
  459. #endif /* __SLG51000_REGISTERS_H__ */