mt6380-regulator.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Copyright (c) 2017 MediaTek Inc.
  4. // Author: Chenglin Xu <chenglin.xu@mediatek.com>
  5. #include <linux/module.h>
  6. #include <linux/of.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/regmap.h>
  9. #include <linux/regulator/driver.h>
  10. #include <linux/regulator/machine.h>
  11. #include <linux/regulator/mt6380-regulator.h>
  12. #include <linux/regulator/of_regulator.h>
  13. /* PMIC Registers */
  14. #define MT6380_ALDO_CON_0 0x0000
  15. #define MT6380_BTLDO_CON_0 0x0004
  16. #define MT6380_COMP_CON_0 0x0008
  17. #define MT6380_CPUBUCK_CON_0 0x000C
  18. #define MT6380_CPUBUCK_CON_1 0x0010
  19. #define MT6380_CPUBUCK_CON_2 0x0014
  20. #define MT6380_DDRLDO_CON_0 0x0018
  21. #define MT6380_MLDO_CON_0 0x001C
  22. #define MT6380_PALDO_CON_0 0x0020
  23. #define MT6380_PHYLDO_CON_0 0x0024
  24. #define MT6380_SIDO_CON_0 0x0028
  25. #define MT6380_SIDO_CON_1 0x002C
  26. #define MT6380_SIDO_CON_2 0x0030
  27. #define MT6380_SLDO_CON_0 0x0034
  28. #define MT6380_TLDO_CON_0 0x0038
  29. #define MT6380_STARTUP_CON_0 0x003C
  30. #define MT6380_STARTUP_CON_1 0x0040
  31. #define MT6380_SMPS_TOP_CON_0 0x0044
  32. #define MT6380_SMPS_TOP_CON_1 0x0048
  33. #define MT6380_ANA_CTRL_0 0x0050
  34. #define MT6380_ANA_CTRL_1 0x0054
  35. #define MT6380_ANA_CTRL_2 0x0058
  36. #define MT6380_ANA_CTRL_3 0x005C
  37. #define MT6380_ANA_CTRL_4 0x0060
  38. #define MT6380_SPK_CON9 0x0064
  39. #define MT6380_SPK_CON11 0x0068
  40. #define MT6380_SPK_CON12 0x006A
  41. #define MT6380_CLK_CTRL 0x0070
  42. #define MT6380_PINMUX_CTRL 0x0074
  43. #define MT6380_IO_CTRL 0x0078
  44. #define MT6380_SLP_MODE_CTRL_0 0x007C
  45. #define MT6380_SLP_MODE_CTRL_1 0x0080
  46. #define MT6380_SLP_MODE_CTRL_2 0x0084
  47. #define MT6380_SLP_MODE_CTRL_3 0x0088
  48. #define MT6380_SLP_MODE_CTRL_4 0x008C
  49. #define MT6380_SLP_MODE_CTRL_5 0x0090
  50. #define MT6380_SLP_MODE_CTRL_6 0x0094
  51. #define MT6380_SLP_MODE_CTRL_7 0x0098
  52. #define MT6380_SLP_MODE_CTRL_8 0x009C
  53. #define MT6380_FCAL_CTRL_0 0x00A0
  54. #define MT6380_FCAL_CTRL_1 0x00A4
  55. #define MT6380_LDO_CTRL_0 0x00A8
  56. #define MT6380_LDO_CTRL_1 0x00AC
  57. #define MT6380_LDO_CTRL_2 0x00B0
  58. #define MT6380_LDO_CTRL_3 0x00B4
  59. #define MT6380_LDO_CTRL_4 0x00B8
  60. #define MT6380_DEBUG_CTRL_0 0x00BC
  61. #define MT6380_EFU_CTRL_0 0x0200
  62. #define MT6380_EFU_CTRL_1 0x0201
  63. #define MT6380_EFU_CTRL_2 0x0202
  64. #define MT6380_EFU_CTRL_3 0x0203
  65. #define MT6380_EFU_CTRL_4 0x0204
  66. #define MT6380_EFU_CTRL_5 0x0205
  67. #define MT6380_EFU_CTRL_6 0x0206
  68. #define MT6380_EFU_CTRL_7 0x0207
  69. #define MT6380_EFU_CTRL_8 0x0208
  70. #define MT6380_REGULATOR_MODE_AUTO 0
  71. #define MT6380_REGULATOR_MODE_FORCE_PWM 1
  72. /*
  73. * mt6380 regulators' information
  74. *
  75. * @desc: standard fields of regulator description
  76. * @vselon_reg: Register sections for hardware control mode of bucks
  77. * @modeset_reg: Register for controlling the buck/LDO control mode
  78. * @modeset_mask: Mask for controlling the buck/LDO control mode
  79. */
  80. struct mt6380_regulator_info {
  81. struct regulator_desc desc;
  82. u32 vselon_reg;
  83. u32 modeset_reg;
  84. u32 modeset_mask;
  85. };
  86. #define MT6380_BUCK(match, vreg, min, max, step, volt_ranges, enreg, \
  87. vosel, vosel_mask, enbit, voselon, _modeset_reg, \
  88. _modeset_mask) \
  89. [MT6380_ID_##vreg] = { \
  90. .desc = { \
  91. .name = #vreg, \
  92. .of_match = of_match_ptr(match), \
  93. .ops = &mt6380_volt_range_ops, \
  94. .type = REGULATOR_VOLTAGE, \
  95. .id = MT6380_ID_##vreg, \
  96. .owner = THIS_MODULE, \
  97. .n_voltages = ((max) - (min)) / (step) + 1, \
  98. .linear_ranges = volt_ranges, \
  99. .n_linear_ranges = ARRAY_SIZE(volt_ranges), \
  100. .vsel_reg = vosel, \
  101. .vsel_mask = vosel_mask, \
  102. .enable_reg = enreg, \
  103. .enable_mask = BIT(enbit), \
  104. }, \
  105. .vselon_reg = voselon, \
  106. .modeset_reg = _modeset_reg, \
  107. .modeset_mask = _modeset_mask, \
  108. }
  109. #define MT6380_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel, \
  110. vosel_mask, _modeset_reg, _modeset_mask) \
  111. [MT6380_ID_##vreg] = { \
  112. .desc = { \
  113. .name = #vreg, \
  114. .of_match = of_match_ptr(match), \
  115. .ops = &mt6380_volt_table_ops, \
  116. .type = REGULATOR_VOLTAGE, \
  117. .id = MT6380_ID_##vreg, \
  118. .owner = THIS_MODULE, \
  119. .n_voltages = ARRAY_SIZE(ldo_volt_table), \
  120. .volt_table = ldo_volt_table, \
  121. .vsel_reg = vosel, \
  122. .vsel_mask = vosel_mask, \
  123. .enable_reg = enreg, \
  124. .enable_mask = BIT(enbit), \
  125. }, \
  126. .modeset_reg = _modeset_reg, \
  127. .modeset_mask = _modeset_mask, \
  128. }
  129. #define MT6380_REG_FIXED(match, vreg, enreg, enbit, volt, \
  130. _modeset_reg, _modeset_mask) \
  131. [MT6380_ID_##vreg] = { \
  132. .desc = { \
  133. .name = #vreg, \
  134. .of_match = of_match_ptr(match), \
  135. .ops = &mt6380_volt_fixed_ops, \
  136. .type = REGULATOR_VOLTAGE, \
  137. .id = MT6380_ID_##vreg, \
  138. .owner = THIS_MODULE, \
  139. .n_voltages = 1, \
  140. .enable_reg = enreg, \
  141. .enable_mask = BIT(enbit), \
  142. .min_uV = volt, \
  143. }, \
  144. .modeset_reg = _modeset_reg, \
  145. .modeset_mask = _modeset_mask, \
  146. }
  147. static const struct regulator_linear_range buck_volt_range1[] = {
  148. REGULATOR_LINEAR_RANGE(600000, 0, 0xfe, 6250),
  149. };
  150. static const struct regulator_linear_range buck_volt_range2[] = {
  151. REGULATOR_LINEAR_RANGE(600000, 0, 0xfe, 6250),
  152. };
  153. static const struct regulator_linear_range buck_volt_range3[] = {
  154. REGULATOR_LINEAR_RANGE(1200000, 0, 0x3c, 25000),
  155. };
  156. static const unsigned int ldo_volt_table1[] = {
  157. 1400000, 1350000, 1300000, 1250000, 1200000, 1150000, 1100000, 1050000,
  158. };
  159. static const unsigned int ldo_volt_table2[] = {
  160. 2200000, 3300000,
  161. };
  162. static const unsigned int ldo_volt_table3[] = {
  163. 1240000, 1390000, 1540000, 1840000,
  164. };
  165. static const unsigned int ldo_volt_table4[] = {
  166. 2200000, 3300000,
  167. };
  168. static int mt6380_regulator_set_mode(struct regulator_dev *rdev,
  169. unsigned int mode)
  170. {
  171. int ret, val = 0;
  172. struct mt6380_regulator_info *info = rdev_get_drvdata(rdev);
  173. switch (mode) {
  174. case REGULATOR_MODE_NORMAL:
  175. val = MT6380_REGULATOR_MODE_AUTO;
  176. break;
  177. case REGULATOR_MODE_FAST:
  178. val = MT6380_REGULATOR_MODE_FORCE_PWM;
  179. break;
  180. default:
  181. return -EINVAL;
  182. }
  183. val <<= ffs(info->modeset_mask) - 1;
  184. ret = regmap_update_bits(rdev->regmap, info->modeset_reg,
  185. info->modeset_mask, val);
  186. return ret;
  187. }
  188. static unsigned int mt6380_regulator_get_mode(struct regulator_dev *rdev)
  189. {
  190. unsigned int val;
  191. unsigned int mode;
  192. int ret;
  193. struct mt6380_regulator_info *info = rdev_get_drvdata(rdev);
  194. ret = regmap_read(rdev->regmap, info->modeset_reg, &val);
  195. if (ret < 0)
  196. return ret;
  197. val &= info->modeset_mask;
  198. val >>= ffs(info->modeset_mask) - 1;
  199. switch (val) {
  200. case MT6380_REGULATOR_MODE_AUTO:
  201. mode = REGULATOR_MODE_NORMAL;
  202. break;
  203. case MT6380_REGULATOR_MODE_FORCE_PWM:
  204. mode = REGULATOR_MODE_FAST;
  205. break;
  206. default:
  207. return -EINVAL;
  208. }
  209. return mode;
  210. }
  211. static const struct regulator_ops mt6380_volt_range_ops = {
  212. .list_voltage = regulator_list_voltage_linear_range,
  213. .map_voltage = regulator_map_voltage_linear_range,
  214. .set_voltage_sel = regulator_set_voltage_sel_regmap,
  215. .get_voltage_sel = regulator_get_voltage_sel_regmap,
  216. .set_voltage_time_sel = regulator_set_voltage_time_sel,
  217. .enable = regulator_enable_regmap,
  218. .disable = regulator_disable_regmap,
  219. .is_enabled = regulator_is_enabled_regmap,
  220. .set_mode = mt6380_regulator_set_mode,
  221. .get_mode = mt6380_regulator_get_mode,
  222. };
  223. static const struct regulator_ops mt6380_volt_table_ops = {
  224. .list_voltage = regulator_list_voltage_table,
  225. .map_voltage = regulator_map_voltage_iterate,
  226. .set_voltage_sel = regulator_set_voltage_sel_regmap,
  227. .get_voltage_sel = regulator_get_voltage_sel_regmap,
  228. .set_voltage_time_sel = regulator_set_voltage_time_sel,
  229. .enable = regulator_enable_regmap,
  230. .disable = regulator_disable_regmap,
  231. .is_enabled = regulator_is_enabled_regmap,
  232. .set_mode = mt6380_regulator_set_mode,
  233. .get_mode = mt6380_regulator_get_mode,
  234. };
  235. static const struct regulator_ops mt6380_volt_fixed_ops = {
  236. .list_voltage = regulator_list_voltage_linear,
  237. .enable = regulator_enable_regmap,
  238. .disable = regulator_disable_regmap,
  239. .is_enabled = regulator_is_enabled_regmap,
  240. .set_mode = mt6380_regulator_set_mode,
  241. .get_mode = mt6380_regulator_get_mode,
  242. };
  243. /* The array is indexed by id(MT6380_ID_XXX) */
  244. static struct mt6380_regulator_info mt6380_regulators[] = {
  245. MT6380_BUCK("buck-vcore1", VCPU, 600000, 1393750, 6250,
  246. buck_volt_range1, MT6380_ANA_CTRL_3, MT6380_ANA_CTRL_1,
  247. 0xfe, 3, MT6380_ANA_CTRL_1,
  248. MT6380_CPUBUCK_CON_0, 0x8000000),
  249. MT6380_BUCK("buck-vcore", VCORE, 600000, 1393750, 6250,
  250. buck_volt_range2, MT6380_ANA_CTRL_3, MT6380_ANA_CTRL_2,
  251. 0xfe, 2, MT6380_ANA_CTRL_2, MT6380_SIDO_CON_0, 0x1000000),
  252. MT6380_BUCK("buck-vrf", VRF, 1200000, 1575000, 25000,
  253. buck_volt_range3, MT6380_ANA_CTRL_3, MT6380_SIDO_CON_0,
  254. 0x78, 1, MT6380_SIDO_CON_0, MT6380_SIDO_CON_0, 0x8000),
  255. MT6380_LDO("ldo-vm", VMLDO, ldo_volt_table1, MT6380_LDO_CTRL_0,
  256. 1, MT6380_MLDO_CON_0, 0xE000, MT6380_ANA_CTRL_1, 0x4000000),
  257. MT6380_LDO("ldo-va", VALDO, ldo_volt_table2, MT6380_LDO_CTRL_0,
  258. 2, MT6380_ALDO_CON_0, 0x400, MT6380_ALDO_CON_0, 0x20),
  259. MT6380_REG_FIXED("ldo-vphy", VPHYLDO, MT6380_LDO_CTRL_0, 7, 1800000,
  260. MT6380_PHYLDO_CON_0, 0x80),
  261. MT6380_LDO("ldo-vddr", VDDRLDO, ldo_volt_table3, MT6380_LDO_CTRL_0,
  262. 8, MT6380_DDRLDO_CON_0, 0x3000, MT6380_DDRLDO_CON_0, 0x80),
  263. MT6380_LDO("ldo-vt", VTLDO, ldo_volt_table4, MT6380_LDO_CTRL_0, 3,
  264. MT6380_TLDO_CON_0, 0x400, MT6380_TLDO_CON_0, 0x20),
  265. };
  266. static int mt6380_regulator_probe(struct platform_device *pdev)
  267. {
  268. struct regmap *regmap = dev_get_regmap(pdev->dev.parent, NULL);
  269. struct regulator_config config = {};
  270. struct regulator_dev *rdev;
  271. int i;
  272. for (i = 0; i < MT6380_MAX_REGULATOR; i++) {
  273. config.dev = &pdev->dev;
  274. config.driver_data = &mt6380_regulators[i];
  275. config.regmap = regmap;
  276. rdev = devm_regulator_register(&pdev->dev,
  277. &mt6380_regulators[i].desc,
  278. &config);
  279. if (IS_ERR(rdev)) {
  280. dev_err(&pdev->dev, "failed to register %s\n",
  281. mt6380_regulators[i].desc.name);
  282. return PTR_ERR(rdev);
  283. }
  284. }
  285. return 0;
  286. }
  287. static const struct platform_device_id mt6380_platform_ids[] = {
  288. {"mt6380-regulator", 0},
  289. { /* sentinel */ },
  290. };
  291. MODULE_DEVICE_TABLE(platform, mt6380_platform_ids);
  292. static const struct of_device_id mt6380_of_match[] = {
  293. { .compatible = "mediatek,mt6380-regulator", },
  294. { /* sentinel */ },
  295. };
  296. MODULE_DEVICE_TABLE(of, mt6380_of_match);
  297. static struct platform_driver mt6380_regulator_driver = {
  298. .driver = {
  299. .name = "mt6380-regulator",
  300. .of_match_table = of_match_ptr(mt6380_of_match),
  301. },
  302. .probe = mt6380_regulator_probe,
  303. .id_table = mt6380_platform_ids,
  304. };
  305. module_platform_driver(mt6380_regulator_driver);
  306. MODULE_AUTHOR("Chenglin Xu <chenglin.xu@mediatek.com>");
  307. MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6380 PMIC");
  308. MODULE_LICENSE("GPL v2");