mc13892-regulator.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Regulator Driver for Freescale MC13892 PMIC
  4. //
  5. // Copyright 2010 Yong Shen <yong.shen@linaro.org>
  6. //
  7. // Based on draft driver from Arnaud Patard <arnaud.patard@rtp-net.org>
  8. #include <linux/mfd/mc13892.h>
  9. #include <linux/regulator/machine.h>
  10. #include <linux/regulator/driver.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/kernel.h>
  13. #include <linux/slab.h>
  14. #include <linux/init.h>
  15. #include <linux/err.h>
  16. #include <linux/module.h>
  17. #include "mc13xxx.h"
  18. #define MC13892_REVISION 7
  19. #define MC13892_POWERCTL0 13
  20. #define MC13892_POWERCTL0_USEROFFSPI 3
  21. #define MC13892_POWERCTL0_VCOINCELLVSEL 20
  22. #define MC13892_POWERCTL0_VCOINCELLVSEL_M (7<<20)
  23. #define MC13892_POWERCTL0_VCOINCELLEN (1<<23)
  24. #define MC13892_SWITCHERS0_SWxHI (1<<23)
  25. #define MC13892_SWITCHERS0 24
  26. #define MC13892_SWITCHERS0_SW1VSEL 0
  27. #define MC13892_SWITCHERS0_SW1VSEL_M (0x1f<<0)
  28. #define MC13892_SWITCHERS0_SW1HI (1<<23)
  29. #define MC13892_SWITCHERS0_SW1EN 0
  30. #define MC13892_SWITCHERS1 25
  31. #define MC13892_SWITCHERS1_SW2VSEL 0
  32. #define MC13892_SWITCHERS1_SW2VSEL_M (0x1f<<0)
  33. #define MC13892_SWITCHERS1_SW2HI (1<<23)
  34. #define MC13892_SWITCHERS1_SW2EN 0
  35. #define MC13892_SWITCHERS2 26
  36. #define MC13892_SWITCHERS2_SW3VSEL 0
  37. #define MC13892_SWITCHERS2_SW3VSEL_M (0x1f<<0)
  38. #define MC13892_SWITCHERS2_SW3HI (1<<23)
  39. #define MC13892_SWITCHERS2_SW3EN 0
  40. #define MC13892_SWITCHERS3 27
  41. #define MC13892_SWITCHERS3_SW4VSEL 0
  42. #define MC13892_SWITCHERS3_SW4VSEL_M (0x1f<<0)
  43. #define MC13892_SWITCHERS3_SW4HI (1<<23)
  44. #define MC13892_SWITCHERS3_SW4EN 0
  45. #define MC13892_SWITCHERS4 28
  46. #define MC13892_SWITCHERS4_SW1MODE 0
  47. #define MC13892_SWITCHERS4_SW1MODE_AUTO (8<<0)
  48. #define MC13892_SWITCHERS4_SW1MODE_M (0xf<<0)
  49. #define MC13892_SWITCHERS4_SW2MODE 10
  50. #define MC13892_SWITCHERS4_SW2MODE_AUTO (8<<10)
  51. #define MC13892_SWITCHERS4_SW2MODE_M (0xf<<10)
  52. #define MC13892_SWITCHERS5 29
  53. #define MC13892_SWITCHERS5_SW3MODE 0
  54. #define MC13892_SWITCHERS5_SW3MODE_AUTO (8<<0)
  55. #define MC13892_SWITCHERS5_SW3MODE_M (0xf<<0)
  56. #define MC13892_SWITCHERS5_SW4MODE 8
  57. #define MC13892_SWITCHERS5_SW4MODE_AUTO (8<<8)
  58. #define MC13892_SWITCHERS5_SW4MODE_M (0xf<<8)
  59. #define MC13892_SWITCHERS5_SWBSTEN (1<<20)
  60. #define MC13892_REGULATORSETTING0 30
  61. #define MC13892_REGULATORSETTING0_VGEN1VSEL 0
  62. #define MC13892_REGULATORSETTING0_VDIGVSEL 4
  63. #define MC13892_REGULATORSETTING0_VGEN2VSEL 6
  64. #define MC13892_REGULATORSETTING0_VPLLVSEL 9
  65. #define MC13892_REGULATORSETTING0_VUSB2VSEL 11
  66. #define MC13892_REGULATORSETTING0_VGEN3VSEL 14
  67. #define MC13892_REGULATORSETTING0_VCAMVSEL 16
  68. #define MC13892_REGULATORSETTING0_VGEN1VSEL_M (3<<0)
  69. #define MC13892_REGULATORSETTING0_VDIGVSEL_M (3<<4)
  70. #define MC13892_REGULATORSETTING0_VGEN2VSEL_M (7<<6)
  71. #define MC13892_REGULATORSETTING0_VPLLVSEL_M (3<<9)
  72. #define MC13892_REGULATORSETTING0_VUSB2VSEL_M (3<<11)
  73. #define MC13892_REGULATORSETTING0_VGEN3VSEL_M (1<<14)
  74. #define MC13892_REGULATORSETTING0_VCAMVSEL_M (3<<16)
  75. #define MC13892_REGULATORSETTING1 31
  76. #define MC13892_REGULATORSETTING1_VVIDEOVSEL 2
  77. #define MC13892_REGULATORSETTING1_VAUDIOVSEL 4
  78. #define MC13892_REGULATORSETTING1_VSDVSEL 6
  79. #define MC13892_REGULATORSETTING1_VVIDEOVSEL_M (3<<2)
  80. #define MC13892_REGULATORSETTING1_VAUDIOVSEL_M (3<<4)
  81. #define MC13892_REGULATORSETTING1_VSDVSEL_M (7<<6)
  82. #define MC13892_REGULATORMODE0 32
  83. #define MC13892_REGULATORMODE0_VGEN1EN (1<<0)
  84. #define MC13892_REGULATORMODE0_VGEN1STDBY (1<<1)
  85. #define MC13892_REGULATORMODE0_VGEN1MODE (1<<2)
  86. #define MC13892_REGULATORMODE0_VIOHIEN (1<<3)
  87. #define MC13892_REGULATORMODE0_VIOHISTDBY (1<<4)
  88. #define MC13892_REGULATORMODE0_VIOHIMODE (1<<5)
  89. #define MC13892_REGULATORMODE0_VDIGEN (1<<9)
  90. #define MC13892_REGULATORMODE0_VDIGSTDBY (1<<10)
  91. #define MC13892_REGULATORMODE0_VDIGMODE (1<<11)
  92. #define MC13892_REGULATORMODE0_VGEN2EN (1<<12)
  93. #define MC13892_REGULATORMODE0_VGEN2STDBY (1<<13)
  94. #define MC13892_REGULATORMODE0_VGEN2MODE (1<<14)
  95. #define MC13892_REGULATORMODE0_VPLLEN (1<<15)
  96. #define MC13892_REGULATORMODE0_VPLLSTDBY (1<<16)
  97. #define MC13892_REGULATORMODE0_VPLLMODE (1<<17)
  98. #define MC13892_REGULATORMODE0_VUSB2EN (1<<18)
  99. #define MC13892_REGULATORMODE0_VUSB2STDBY (1<<19)
  100. #define MC13892_REGULATORMODE0_VUSB2MODE (1<<20)
  101. #define MC13892_REGULATORMODE1 33
  102. #define MC13892_REGULATORMODE1_VGEN3EN (1<<0)
  103. #define MC13892_REGULATORMODE1_VGEN3STDBY (1<<1)
  104. #define MC13892_REGULATORMODE1_VGEN3MODE (1<<2)
  105. #define MC13892_REGULATORMODE1_VCAMEN (1<<6)
  106. #define MC13892_REGULATORMODE1_VCAMSTDBY (1<<7)
  107. #define MC13892_REGULATORMODE1_VCAMMODE (1<<8)
  108. #define MC13892_REGULATORMODE1_VCAMCONFIGEN (1<<9)
  109. #define MC13892_REGULATORMODE1_VVIDEOEN (1<<12)
  110. #define MC13892_REGULATORMODE1_VVIDEOSTDBY (1<<13)
  111. #define MC13892_REGULATORMODE1_VVIDEOMODE (1<<14)
  112. #define MC13892_REGULATORMODE1_VAUDIOEN (1<<15)
  113. #define MC13892_REGULATORMODE1_VAUDIOSTDBY (1<<16)
  114. #define MC13892_REGULATORMODE1_VAUDIOMODE (1<<17)
  115. #define MC13892_REGULATORMODE1_VSDEN (1<<18)
  116. #define MC13892_REGULATORMODE1_VSDSTDBY (1<<19)
  117. #define MC13892_REGULATORMODE1_VSDMODE (1<<20)
  118. #define MC13892_POWERMISC 34
  119. #define MC13892_POWERMISC_GPO1EN (1<<6)
  120. #define MC13892_POWERMISC_GPO2EN (1<<8)
  121. #define MC13892_POWERMISC_GPO3EN (1<<10)
  122. #define MC13892_POWERMISC_GPO4EN (1<<12)
  123. #define MC13892_POWERMISC_PWGT1SPIEN (1<<15)
  124. #define MC13892_POWERMISC_PWGT2SPIEN (1<<16)
  125. #define MC13892_POWERMISC_GPO4ADINEN (1<<21)
  126. #define MC13892_POWERMISC_PWGTSPI_M (3 << 15)
  127. #define MC13892_USB1 50
  128. #define MC13892_USB1_VUSBEN (1<<3)
  129. static const unsigned int mc13892_vcoincell[] = {
  130. 2500000, 2700000, 2800000, 2900000, 3000000, 3100000,
  131. 3200000, 3300000,
  132. };
  133. static const unsigned int mc13892_sw1[] = {
  134. 600000, 625000, 650000, 675000, 700000, 725000,
  135. 750000, 775000, 800000, 825000, 850000, 875000,
  136. 900000, 925000, 950000, 975000, 1000000, 1025000,
  137. 1050000, 1075000, 1100000, 1125000, 1150000, 1175000,
  138. 1200000, 1225000, 1250000, 1275000, 1300000, 1325000,
  139. 1350000, 1375000
  140. };
  141. /*
  142. * Note: this table is used to derive SWxVSEL by index into
  143. * the array. Offset the values by the index of 1100000uV
  144. * to get the actual register value for that voltage selector
  145. * if the HI bit is to be set as well.
  146. */
  147. #define MC13892_SWxHI_SEL_OFFSET 20
  148. static const unsigned int mc13892_sw[] = {
  149. 600000, 625000, 650000, 675000, 700000, 725000,
  150. 750000, 775000, 800000, 825000, 850000, 875000,
  151. 900000, 925000, 950000, 975000, 1000000, 1025000,
  152. 1050000, 1075000, 1100000, 1125000, 1150000, 1175000,
  153. 1200000, 1225000, 1250000, 1275000, 1300000, 1325000,
  154. 1350000, 1375000, 1400000, 1425000, 1450000, 1475000,
  155. 1500000, 1525000, 1550000, 1575000, 1600000, 1625000,
  156. 1650000, 1675000, 1700000, 1725000, 1750000, 1775000,
  157. 1800000, 1825000, 1850000, 1875000
  158. };
  159. static const unsigned int mc13892_swbst[] = {
  160. 5000000,
  161. };
  162. static const unsigned int mc13892_viohi[] = {
  163. 2775000,
  164. };
  165. static const unsigned int mc13892_vpll[] = {
  166. 1050000, 1250000, 1650000, 1800000,
  167. };
  168. static const unsigned int mc13892_vdig[] = {
  169. 1050000, 1250000, 1650000, 1800000,
  170. };
  171. static const unsigned int mc13892_vsd[] = {
  172. 1800000, 2000000, 2600000, 2700000,
  173. 2800000, 2900000, 3000000, 3150000,
  174. };
  175. static const unsigned int mc13892_vusb2[] = {
  176. 2400000, 2600000, 2700000, 2775000,
  177. };
  178. static const unsigned int mc13892_vvideo[] = {
  179. 2700000, 2775000, 2500000, 2600000,
  180. };
  181. static const unsigned int mc13892_vaudio[] = {
  182. 2300000, 2500000, 2775000, 3000000,
  183. };
  184. static const unsigned int mc13892_vcam[] = {
  185. 2500000, 2600000, 2750000, 3000000,
  186. };
  187. static const unsigned int mc13892_vgen1[] = {
  188. 1200000, 1500000, 2775000, 3150000,
  189. };
  190. static const unsigned int mc13892_vgen2[] = {
  191. 1200000, 1500000, 1600000, 1800000,
  192. 2700000, 2800000, 3000000, 3150000,
  193. };
  194. static const unsigned int mc13892_vgen3[] = {
  195. 1800000, 2900000,
  196. };
  197. static const unsigned int mc13892_vusb[] = {
  198. 3300000,
  199. };
  200. static const unsigned int mc13892_gpo[] = {
  201. 2750000,
  202. };
  203. static const unsigned int mc13892_pwgtdrv[] = {
  204. 5000000,
  205. };
  206. static const struct regulator_ops mc13892_gpo_regulator_ops;
  207. static const struct regulator_ops mc13892_sw_regulator_ops;
  208. #define MC13892_FIXED_DEFINE(name, node, reg, voltages) \
  209. MC13xxx_FIXED_DEFINE(MC13892_, name, node, reg, voltages, \
  210. mc13xxx_fixed_regulator_ops)
  211. #define MC13892_GPO_DEFINE(name, node, reg, voltages) \
  212. MC13xxx_GPO_DEFINE(MC13892_, name, node, reg, voltages, \
  213. mc13892_gpo_regulator_ops)
  214. #define MC13892_SW_DEFINE(name, node, reg, vsel_reg, voltages) \
  215. MC13xxx_DEFINE(MC13892_, name, node, reg, vsel_reg, voltages, \
  216. mc13892_sw_regulator_ops)
  217. #define MC13892_DEFINE_REGU(name, node, reg, vsel_reg, voltages) \
  218. MC13xxx_DEFINE(MC13892_, name, node, reg, vsel_reg, voltages, \
  219. mc13xxx_regulator_ops)
  220. static struct mc13xxx_regulator mc13892_regulators[] = {
  221. MC13892_DEFINE_REGU(VCOINCELL, vcoincell, POWERCTL0, POWERCTL0, mc13892_vcoincell),
  222. MC13892_SW_DEFINE(SW1, sw1, SWITCHERS0, SWITCHERS0, mc13892_sw1),
  223. MC13892_SW_DEFINE(SW2, sw2, SWITCHERS1, SWITCHERS1, mc13892_sw),
  224. MC13892_SW_DEFINE(SW3, sw3, SWITCHERS2, SWITCHERS2, mc13892_sw),
  225. MC13892_SW_DEFINE(SW4, sw4, SWITCHERS3, SWITCHERS3, mc13892_sw),
  226. MC13892_FIXED_DEFINE(SWBST, swbst, SWITCHERS5, mc13892_swbst),
  227. MC13892_FIXED_DEFINE(VIOHI, viohi, REGULATORMODE0, mc13892_viohi),
  228. MC13892_DEFINE_REGU(VPLL, vpll, REGULATORMODE0, REGULATORSETTING0,
  229. mc13892_vpll),
  230. MC13892_DEFINE_REGU(VDIG, vdig, REGULATORMODE0, REGULATORSETTING0,
  231. mc13892_vdig),
  232. MC13892_DEFINE_REGU(VSD, vsd, REGULATORMODE1, REGULATORSETTING1,
  233. mc13892_vsd),
  234. MC13892_DEFINE_REGU(VUSB2, vusb2, REGULATORMODE0, REGULATORSETTING0,
  235. mc13892_vusb2),
  236. MC13892_DEFINE_REGU(VVIDEO, vvideo, REGULATORMODE1, REGULATORSETTING1,
  237. mc13892_vvideo),
  238. MC13892_DEFINE_REGU(VAUDIO, vaudio, REGULATORMODE1, REGULATORSETTING1,
  239. mc13892_vaudio),
  240. MC13892_DEFINE_REGU(VCAM, vcam, REGULATORMODE1, REGULATORSETTING0,
  241. mc13892_vcam),
  242. MC13892_DEFINE_REGU(VGEN1, vgen1, REGULATORMODE0, REGULATORSETTING0,
  243. mc13892_vgen1),
  244. MC13892_DEFINE_REGU(VGEN2, vgen2, REGULATORMODE0, REGULATORSETTING0,
  245. mc13892_vgen2),
  246. MC13892_DEFINE_REGU(VGEN3, vgen3, REGULATORMODE1, REGULATORSETTING0,
  247. mc13892_vgen3),
  248. MC13892_FIXED_DEFINE(VUSB, vusb, USB1, mc13892_vusb),
  249. MC13892_GPO_DEFINE(GPO1, gpo1, POWERMISC, mc13892_gpo),
  250. MC13892_GPO_DEFINE(GPO2, gpo2, POWERMISC, mc13892_gpo),
  251. MC13892_GPO_DEFINE(GPO3, gpo3, POWERMISC, mc13892_gpo),
  252. MC13892_GPO_DEFINE(GPO4, gpo4, POWERMISC, mc13892_gpo),
  253. MC13892_GPO_DEFINE(PWGT1SPI, pwgt1spi, POWERMISC, mc13892_pwgtdrv),
  254. MC13892_GPO_DEFINE(PWGT2SPI, pwgt2spi, POWERMISC, mc13892_pwgtdrv),
  255. };
  256. static int mc13892_powermisc_rmw(struct mc13xxx_regulator_priv *priv, u32 mask,
  257. u32 val)
  258. {
  259. struct mc13xxx *mc13892 = priv->mc13xxx;
  260. int ret;
  261. u32 valread;
  262. BUG_ON(val & ~mask);
  263. mc13xxx_lock(priv->mc13xxx);
  264. ret = mc13xxx_reg_read(mc13892, MC13892_POWERMISC, &valread);
  265. if (ret)
  266. goto out;
  267. /* Update the stored state for Power Gates. */
  268. priv->powermisc_pwgt_state =
  269. (priv->powermisc_pwgt_state & ~mask) | val;
  270. priv->powermisc_pwgt_state &= MC13892_POWERMISC_PWGTSPI_M;
  271. /* Construct the new register value */
  272. valread = (valread & ~mask) | val;
  273. /* Overwrite the PWGTxEN with the stored version */
  274. valread = (valread & ~MC13892_POWERMISC_PWGTSPI_M) |
  275. priv->powermisc_pwgt_state;
  276. ret = mc13xxx_reg_write(mc13892, MC13892_POWERMISC, valread);
  277. out:
  278. mc13xxx_unlock(priv->mc13xxx);
  279. return ret;
  280. }
  281. static int mc13892_gpo_regulator_enable(struct regulator_dev *rdev)
  282. {
  283. struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
  284. int id = rdev_get_id(rdev);
  285. u32 en_val = mc13892_regulators[id].enable_bit;
  286. u32 mask = mc13892_regulators[id].enable_bit;
  287. dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
  288. /* Power Gate enable value is 0 */
  289. if (id == MC13892_PWGT1SPI || id == MC13892_PWGT2SPI)
  290. en_val = 0;
  291. if (id == MC13892_GPO4)
  292. mask |= MC13892_POWERMISC_GPO4ADINEN;
  293. return mc13892_powermisc_rmw(priv, mask, en_val);
  294. }
  295. static int mc13892_gpo_regulator_disable(struct regulator_dev *rdev)
  296. {
  297. struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
  298. int id = rdev_get_id(rdev);
  299. u32 dis_val = 0;
  300. dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
  301. /* Power Gate disable value is 1 */
  302. if (id == MC13892_PWGT1SPI || id == MC13892_PWGT2SPI)
  303. dis_val = mc13892_regulators[id].enable_bit;
  304. return mc13892_powermisc_rmw(priv, mc13892_regulators[id].enable_bit,
  305. dis_val);
  306. }
  307. static int mc13892_gpo_regulator_is_enabled(struct regulator_dev *rdev)
  308. {
  309. struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
  310. int ret, id = rdev_get_id(rdev);
  311. unsigned int val;
  312. mc13xxx_lock(priv->mc13xxx);
  313. ret = mc13xxx_reg_read(priv->mc13xxx, mc13892_regulators[id].reg, &val);
  314. mc13xxx_unlock(priv->mc13xxx);
  315. if (ret)
  316. return ret;
  317. /* Power Gates state is stored in powermisc_pwgt_state
  318. * where the meaning of bits is negated */
  319. val = (val & ~MC13892_POWERMISC_PWGTSPI_M) |
  320. (priv->powermisc_pwgt_state ^ MC13892_POWERMISC_PWGTSPI_M);
  321. return (val & mc13892_regulators[id].enable_bit) != 0;
  322. }
  323. static const struct regulator_ops mc13892_gpo_regulator_ops = {
  324. .enable = mc13892_gpo_regulator_enable,
  325. .disable = mc13892_gpo_regulator_disable,
  326. .is_enabled = mc13892_gpo_regulator_is_enabled,
  327. .list_voltage = regulator_list_voltage_table,
  328. .set_voltage = mc13xxx_fixed_regulator_set_voltage,
  329. };
  330. static int mc13892_sw_regulator_get_voltage_sel(struct regulator_dev *rdev)
  331. {
  332. struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
  333. int ret, id = rdev_get_id(rdev);
  334. unsigned int val, selector;
  335. dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
  336. mc13xxx_lock(priv->mc13xxx);
  337. ret = mc13xxx_reg_read(priv->mc13xxx,
  338. mc13892_regulators[id].vsel_reg, &val);
  339. mc13xxx_unlock(priv->mc13xxx);
  340. if (ret)
  341. return ret;
  342. /*
  343. * Figure out if the HI bit is set inside the switcher mode register
  344. * since this means the selector value we return is at a different
  345. * offset into the selector table.
  346. *
  347. * According to the MC13892 documentation note 59 (Table 47) the SW1
  348. * buck switcher does not support output range programming therefore
  349. * the HI bit must always remain 0. So do not do anything strange if
  350. * our register is MC13892_SWITCHERS0.
  351. */
  352. selector = val & mc13892_regulators[id].vsel_mask;
  353. if ((mc13892_regulators[id].vsel_reg != MC13892_SWITCHERS0) &&
  354. (val & MC13892_SWITCHERS0_SWxHI)) {
  355. selector += MC13892_SWxHI_SEL_OFFSET;
  356. }
  357. dev_dbg(rdev_get_dev(rdev), "%s id: %d val: 0x%08x selector: %d\n",
  358. __func__, id, val, selector);
  359. return selector;
  360. }
  361. static int mc13892_sw_regulator_set_voltage_sel(struct regulator_dev *rdev,
  362. unsigned selector)
  363. {
  364. struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
  365. int volt, mask, id = rdev_get_id(rdev);
  366. u32 reg_value;
  367. int ret;
  368. volt = rdev->desc->volt_table[selector];
  369. mask = mc13892_regulators[id].vsel_mask;
  370. reg_value = selector;
  371. /*
  372. * Don't mess with the HI bit or support HI voltage offsets for SW1.
  373. *
  374. * Since the get_voltage_sel callback has given a fudged value for
  375. * the selector offset, we need to back out that offset if HI is
  376. * to be set so we write the correct value to the register.
  377. *
  378. * The HI bit addition and selector offset handling COULD be more
  379. * complicated by shifting and masking off the voltage selector part
  380. * of the register then logical OR it back in, but since the selector
  381. * is at bits 4:0 there is very little point. This makes the whole
  382. * thing more readable and we do far less work.
  383. */
  384. if (mc13892_regulators[id].vsel_reg != MC13892_SWITCHERS0) {
  385. mask |= MC13892_SWITCHERS0_SWxHI;
  386. if (volt > 1375000) {
  387. reg_value -= MC13892_SWxHI_SEL_OFFSET;
  388. reg_value |= MC13892_SWITCHERS0_SWxHI;
  389. } else {
  390. reg_value &= ~MC13892_SWITCHERS0_SWxHI;
  391. }
  392. }
  393. mc13xxx_lock(priv->mc13xxx);
  394. ret = mc13xxx_reg_rmw(priv->mc13xxx, mc13892_regulators[id].vsel_reg,
  395. mask, reg_value);
  396. mc13xxx_unlock(priv->mc13xxx);
  397. return ret;
  398. }
  399. static const struct regulator_ops mc13892_sw_regulator_ops = {
  400. .list_voltage = regulator_list_voltage_table,
  401. .map_voltage = regulator_map_voltage_ascend,
  402. .set_voltage_sel = mc13892_sw_regulator_set_voltage_sel,
  403. .get_voltage_sel = mc13892_sw_regulator_get_voltage_sel,
  404. };
  405. static int mc13892_vcam_set_mode(struct regulator_dev *rdev, unsigned int mode)
  406. {
  407. unsigned int en_val = 0;
  408. struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
  409. int ret, id = rdev_get_id(rdev);
  410. if (mode == REGULATOR_MODE_FAST)
  411. en_val = MC13892_REGULATORMODE1_VCAMCONFIGEN;
  412. mc13xxx_lock(priv->mc13xxx);
  413. ret = mc13xxx_reg_rmw(priv->mc13xxx, mc13892_regulators[id].reg,
  414. MC13892_REGULATORMODE1_VCAMCONFIGEN, en_val);
  415. mc13xxx_unlock(priv->mc13xxx);
  416. return ret;
  417. }
  418. static unsigned int mc13892_vcam_get_mode(struct regulator_dev *rdev)
  419. {
  420. struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
  421. int ret, id = rdev_get_id(rdev);
  422. unsigned int val;
  423. mc13xxx_lock(priv->mc13xxx);
  424. ret = mc13xxx_reg_read(priv->mc13xxx, mc13892_regulators[id].reg, &val);
  425. mc13xxx_unlock(priv->mc13xxx);
  426. if (ret)
  427. return ret;
  428. if (val & MC13892_REGULATORMODE1_VCAMCONFIGEN)
  429. return REGULATOR_MODE_FAST;
  430. return REGULATOR_MODE_NORMAL;
  431. }
  432. static struct regulator_ops mc13892_vcam_ops;
  433. static int mc13892_regulator_probe(struct platform_device *pdev)
  434. {
  435. struct mc13xxx_regulator_priv *priv;
  436. struct mc13xxx *mc13892 = dev_get_drvdata(pdev->dev.parent);
  437. struct mc13xxx_regulator_platform_data *pdata =
  438. dev_get_platdata(&pdev->dev);
  439. struct mc13xxx_regulator_init_data *mc13xxx_data;
  440. struct regulator_config config = { };
  441. int i, ret;
  442. int num_regulators = 0;
  443. u32 val;
  444. num_regulators = mc13xxx_get_num_regulators_dt(pdev);
  445. if (num_regulators <= 0 && pdata)
  446. num_regulators = pdata->num_regulators;
  447. if (num_regulators <= 0)
  448. return -EINVAL;
  449. priv = devm_kzalloc(&pdev->dev,
  450. struct_size(priv, regulators, num_regulators),
  451. GFP_KERNEL);
  452. if (!priv)
  453. return -ENOMEM;
  454. priv->num_regulators = num_regulators;
  455. priv->mc13xxx_regulators = mc13892_regulators;
  456. priv->mc13xxx = mc13892;
  457. platform_set_drvdata(pdev, priv);
  458. mc13xxx_lock(mc13892);
  459. ret = mc13xxx_reg_read(mc13892, MC13892_REVISION, &val);
  460. if (ret)
  461. goto err_unlock;
  462. /* enable switch auto mode (on 2.0A silicon only) */
  463. if ((val & 0x0000FFFF) == 0x45d0) {
  464. ret = mc13xxx_reg_rmw(mc13892, MC13892_SWITCHERS4,
  465. MC13892_SWITCHERS4_SW1MODE_M |
  466. MC13892_SWITCHERS4_SW2MODE_M,
  467. MC13892_SWITCHERS4_SW1MODE_AUTO |
  468. MC13892_SWITCHERS4_SW2MODE_AUTO);
  469. if (ret)
  470. goto err_unlock;
  471. ret = mc13xxx_reg_rmw(mc13892, MC13892_SWITCHERS5,
  472. MC13892_SWITCHERS5_SW3MODE_M |
  473. MC13892_SWITCHERS5_SW4MODE_M,
  474. MC13892_SWITCHERS5_SW3MODE_AUTO |
  475. MC13892_SWITCHERS5_SW4MODE_AUTO);
  476. if (ret)
  477. goto err_unlock;
  478. }
  479. mc13xxx_unlock(mc13892);
  480. /* update mc13892_vcam ops */
  481. memcpy(&mc13892_vcam_ops, mc13892_regulators[MC13892_VCAM].desc.ops,
  482. sizeof(struct regulator_ops));
  483. mc13892_vcam_ops.set_mode = mc13892_vcam_set_mode,
  484. mc13892_vcam_ops.get_mode = mc13892_vcam_get_mode,
  485. mc13892_regulators[MC13892_VCAM].desc.ops = &mc13892_vcam_ops;
  486. mc13xxx_data = mc13xxx_parse_regulators_dt(pdev, mc13892_regulators,
  487. ARRAY_SIZE(mc13892_regulators));
  488. for (i = 0; i < priv->num_regulators; i++) {
  489. struct regulator_init_data *init_data;
  490. struct regulator_desc *desc;
  491. struct device_node *node = NULL;
  492. int id;
  493. if (mc13xxx_data) {
  494. id = mc13xxx_data[i].id;
  495. init_data = mc13xxx_data[i].init_data;
  496. node = mc13xxx_data[i].node;
  497. } else {
  498. id = pdata->regulators[i].id;
  499. init_data = pdata->regulators[i].init_data;
  500. }
  501. desc = &mc13892_regulators[id].desc;
  502. config.dev = &pdev->dev;
  503. config.init_data = init_data;
  504. config.driver_data = priv;
  505. config.of_node = node;
  506. priv->regulators[i] = devm_regulator_register(&pdev->dev, desc,
  507. &config);
  508. if (IS_ERR(priv->regulators[i])) {
  509. dev_err(&pdev->dev, "failed to register regulator %s\n",
  510. mc13892_regulators[i].desc.name);
  511. return PTR_ERR(priv->regulators[i]);
  512. }
  513. }
  514. return 0;
  515. err_unlock:
  516. mc13xxx_unlock(mc13892);
  517. return ret;
  518. }
  519. static struct platform_driver mc13892_regulator_driver = {
  520. .driver = {
  521. .name = "mc13892-regulator",
  522. },
  523. .probe = mc13892_regulator_probe,
  524. };
  525. static int __init mc13892_regulator_init(void)
  526. {
  527. return platform_driver_register(&mc13892_regulator_driver);
  528. }
  529. subsys_initcall(mc13892_regulator_init);
  530. static void __exit mc13892_regulator_exit(void)
  531. {
  532. platform_driver_unregister(&mc13892_regulator_driver);
  533. }
  534. module_exit(mc13892_regulator_exit);
  535. MODULE_LICENSE("GPL v2");
  536. MODULE_AUTHOR("Yong Shen <yong.shen@linaro.org>");
  537. MODULE_DESCRIPTION("Regulator Driver for Freescale MC13892 PMIC");
  538. MODULE_ALIAS("platform:mc13892-regulator");