mc13783-regulator.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Regulator Driver for Freescale MC13783 PMIC
  4. //
  5. // Copyright 2010 Yong Shen <yong.shen@linaro.org>
  6. // Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
  7. // Copyright 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
  8. #include <linux/mfd/mc13783.h>
  9. #include <linux/regulator/machine.h>
  10. #include <linux/regulator/driver.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/kernel.h>
  13. #include <linux/slab.h>
  14. #include <linux/init.h>
  15. #include <linux/err.h>
  16. #include <linux/module.h>
  17. #include "mc13xxx.h"
  18. #define MC13783_REG_SWITCHERS0 24
  19. /* Enable does not exist for SW1A */
  20. #define MC13783_REG_SWITCHERS0_SW1AEN 0
  21. #define MC13783_REG_SWITCHERS0_SW1AVSEL 0
  22. #define MC13783_REG_SWITCHERS0_SW1AVSEL_M (63 << 0)
  23. #define MC13783_REG_SWITCHERS1 25
  24. /* Enable does not exist for SW1B */
  25. #define MC13783_REG_SWITCHERS1_SW1BEN 0
  26. #define MC13783_REG_SWITCHERS1_SW1BVSEL 0
  27. #define MC13783_REG_SWITCHERS1_SW1BVSEL_M (63 << 0)
  28. #define MC13783_REG_SWITCHERS2 26
  29. /* Enable does not exist for SW2A */
  30. #define MC13783_REG_SWITCHERS2_SW2AEN 0
  31. #define MC13783_REG_SWITCHERS2_SW2AVSEL 0
  32. #define MC13783_REG_SWITCHERS2_SW2AVSEL_M (63 << 0)
  33. #define MC13783_REG_SWITCHERS3 27
  34. /* Enable does not exist for SW2B */
  35. #define MC13783_REG_SWITCHERS3_SW2BEN 0
  36. #define MC13783_REG_SWITCHERS3_SW2BVSEL 0
  37. #define MC13783_REG_SWITCHERS3_SW2BVSEL_M (63 << 0)
  38. #define MC13783_REG_SWITCHERS5 29
  39. #define MC13783_REG_SWITCHERS5_SW3EN (1 << 20)
  40. #define MC13783_REG_SWITCHERS5_SW3VSEL 18
  41. #define MC13783_REG_SWITCHERS5_SW3VSEL_M (3 << 18)
  42. #define MC13783_REG_REGULATORSETTING0 30
  43. #define MC13783_REG_REGULATORSETTING0_VIOLOVSEL 2
  44. #define MC13783_REG_REGULATORSETTING0_VDIGVSEL 4
  45. #define MC13783_REG_REGULATORSETTING0_VGENVSEL 6
  46. #define MC13783_REG_REGULATORSETTING0_VRFDIGVSEL 9
  47. #define MC13783_REG_REGULATORSETTING0_VRFREFVSEL 11
  48. #define MC13783_REG_REGULATORSETTING0_VRFCPVSEL 13
  49. #define MC13783_REG_REGULATORSETTING0_VSIMVSEL 14
  50. #define MC13783_REG_REGULATORSETTING0_VESIMVSEL 15
  51. #define MC13783_REG_REGULATORSETTING0_VCAMVSEL 16
  52. #define MC13783_REG_REGULATORSETTING0_VIOLOVSEL_M (3 << 2)
  53. #define MC13783_REG_REGULATORSETTING0_VDIGVSEL_M (3 << 4)
  54. #define MC13783_REG_REGULATORSETTING0_VGENVSEL_M (7 << 6)
  55. #define MC13783_REG_REGULATORSETTING0_VRFDIGVSEL_M (3 << 9)
  56. #define MC13783_REG_REGULATORSETTING0_VRFREFVSEL_M (3 << 11)
  57. #define MC13783_REG_REGULATORSETTING0_VRFCPVSEL_M (1 << 13)
  58. #define MC13783_REG_REGULATORSETTING0_VSIMVSEL_M (1 << 14)
  59. #define MC13783_REG_REGULATORSETTING0_VESIMVSEL_M (1 << 15)
  60. #define MC13783_REG_REGULATORSETTING0_VCAMVSEL_M (7 << 16)
  61. #define MC13783_REG_REGULATORSETTING1 31
  62. #define MC13783_REG_REGULATORSETTING1_VVIBVSEL 0
  63. #define MC13783_REG_REGULATORSETTING1_VRF1VSEL 2
  64. #define MC13783_REG_REGULATORSETTING1_VRF2VSEL 4
  65. #define MC13783_REG_REGULATORSETTING1_VMMC1VSEL 6
  66. #define MC13783_REG_REGULATORSETTING1_VMMC2VSEL 9
  67. #define MC13783_REG_REGULATORSETTING1_VVIBVSEL_M (3 << 0)
  68. #define MC13783_REG_REGULATORSETTING1_VRF1VSEL_M (3 << 2)
  69. #define MC13783_REG_REGULATORSETTING1_VRF2VSEL_M (3 << 4)
  70. #define MC13783_REG_REGULATORSETTING1_VMMC1VSEL_M (7 << 6)
  71. #define MC13783_REG_REGULATORSETTING1_VMMC2VSEL_M (7 << 9)
  72. #define MC13783_REG_REGULATORMODE0 32
  73. #define MC13783_REG_REGULATORMODE0_VAUDIOEN (1 << 0)
  74. #define MC13783_REG_REGULATORMODE0_VIOHIEN (1 << 3)
  75. #define MC13783_REG_REGULATORMODE0_VIOLOEN (1 << 6)
  76. #define MC13783_REG_REGULATORMODE0_VDIGEN (1 << 9)
  77. #define MC13783_REG_REGULATORMODE0_VGENEN (1 << 12)
  78. #define MC13783_REG_REGULATORMODE0_VRFDIGEN (1 << 15)
  79. #define MC13783_REG_REGULATORMODE0_VRFREFEN (1 << 18)
  80. #define MC13783_REG_REGULATORMODE0_VRFCPEN (1 << 21)
  81. #define MC13783_REG_REGULATORMODE1 33
  82. #define MC13783_REG_REGULATORMODE1_VSIMEN (1 << 0)
  83. #define MC13783_REG_REGULATORMODE1_VESIMEN (1 << 3)
  84. #define MC13783_REG_REGULATORMODE1_VCAMEN (1 << 6)
  85. #define MC13783_REG_REGULATORMODE1_VRFBGEN (1 << 9)
  86. #define MC13783_REG_REGULATORMODE1_VVIBEN (1 << 11)
  87. #define MC13783_REG_REGULATORMODE1_VRF1EN (1 << 12)
  88. #define MC13783_REG_REGULATORMODE1_VRF2EN (1 << 15)
  89. #define MC13783_REG_REGULATORMODE1_VMMC1EN (1 << 18)
  90. #define MC13783_REG_REGULATORMODE1_VMMC2EN (1 << 21)
  91. #define MC13783_REG_POWERMISC 34
  92. #define MC13783_REG_POWERMISC_GPO1EN (1 << 6)
  93. #define MC13783_REG_POWERMISC_GPO2EN (1 << 8)
  94. #define MC13783_REG_POWERMISC_GPO3EN (1 << 10)
  95. #define MC13783_REG_POWERMISC_GPO4EN (1 << 12)
  96. #define MC13783_REG_POWERMISC_PWGT1SPIEN (1 << 15)
  97. #define MC13783_REG_POWERMISC_PWGT2SPIEN (1 << 16)
  98. #define MC13783_REG_POWERMISC_PWGTSPI_M (3 << 15)
  99. /* Voltage Values */
  100. static const int mc13783_sw1x_val[] = {
  101. 900000, 925000, 950000, 975000,
  102. 1000000, 1025000, 1050000, 1075000,
  103. 1100000, 1125000, 1150000, 1175000,
  104. 1200000, 1225000, 1250000, 1275000,
  105. 1300000, 1325000, 1350000, 1375000,
  106. 1400000, 1425000, 1450000, 1475000,
  107. 1500000, 1525000, 1550000, 1575000,
  108. 1600000, 1625000, 1650000, 1675000,
  109. 1700000, 1700000, 1700000, 1700000,
  110. 1800000, 1800000, 1800000, 1800000,
  111. 1850000, 1850000, 1850000, 1850000,
  112. 2000000, 2000000, 2000000, 2000000,
  113. 2100000, 2100000, 2100000, 2100000,
  114. 2200000, 2200000, 2200000, 2200000,
  115. 2200000, 2200000, 2200000, 2200000,
  116. 2200000, 2200000, 2200000, 2200000,
  117. };
  118. static const int mc13783_sw2x_val[] = {
  119. 900000, 925000, 950000, 975000,
  120. 1000000, 1025000, 1050000, 1075000,
  121. 1100000, 1125000, 1150000, 1175000,
  122. 1200000, 1225000, 1250000, 1275000,
  123. 1300000, 1325000, 1350000, 1375000,
  124. 1400000, 1425000, 1450000, 1475000,
  125. 1500000, 1525000, 1550000, 1575000,
  126. 1600000, 1625000, 1650000, 1675000,
  127. 1700000, 1700000, 1700000, 1700000,
  128. 1800000, 1800000, 1800000, 1800000,
  129. 1900000, 1900000, 1900000, 1900000,
  130. 2000000, 2000000, 2000000, 2000000,
  131. 2100000, 2100000, 2100000, 2100000,
  132. 2200000, 2200000, 2200000, 2200000,
  133. 2200000, 2200000, 2200000, 2200000,
  134. 2200000, 2200000, 2200000, 2200000,
  135. };
  136. static const unsigned int mc13783_sw3_val[] = {
  137. 5000000, 5000000, 5000000, 5500000,
  138. };
  139. static const unsigned int mc13783_vaudio_val[] = {
  140. 2775000,
  141. };
  142. static const unsigned int mc13783_viohi_val[] = {
  143. 2775000,
  144. };
  145. static const unsigned int mc13783_violo_val[] = {
  146. 1200000, 1300000, 1500000, 1800000,
  147. };
  148. static const unsigned int mc13783_vdig_val[] = {
  149. 1200000, 1300000, 1500000, 1800000,
  150. };
  151. static const unsigned int mc13783_vgen_val[] = {
  152. 1200000, 1300000, 1500000, 1800000,
  153. 1100000, 2000000, 2775000, 2400000,
  154. };
  155. static const unsigned int mc13783_vrfdig_val[] = {
  156. 1200000, 1500000, 1800000, 1875000,
  157. };
  158. static const unsigned int mc13783_vrfref_val[] = {
  159. 2475000, 2600000, 2700000, 2775000,
  160. };
  161. static const unsigned int mc13783_vrfcp_val[] = {
  162. 2700000, 2775000,
  163. };
  164. static const unsigned int mc13783_vsim_val[] = {
  165. 1800000, 2900000, 3000000,
  166. };
  167. static const unsigned int mc13783_vesim_val[] = {
  168. 1800000, 2900000,
  169. };
  170. static const unsigned int mc13783_vcam_val[] = {
  171. 1500000, 1800000, 2500000, 2550000,
  172. 2600000, 2750000, 2800000, 3000000,
  173. };
  174. static const unsigned int mc13783_vrfbg_val[] = {
  175. 1250000,
  176. };
  177. static const unsigned int mc13783_vvib_val[] = {
  178. 1300000, 1800000, 2000000, 3000000,
  179. };
  180. static const unsigned int mc13783_vmmc_val[] = {
  181. 1600000, 1800000, 2000000, 2600000,
  182. 2700000, 2800000, 2900000, 3000000,
  183. };
  184. static const unsigned int mc13783_vrf_val[] = {
  185. 1500000, 1875000, 2700000, 2775000,
  186. };
  187. static const unsigned int mc13783_gpo_val[] = {
  188. 3100000,
  189. };
  190. static const unsigned int mc13783_pwgtdrv_val[] = {
  191. 5500000,
  192. };
  193. static const struct regulator_ops mc13783_gpo_regulator_ops;
  194. #define MC13783_DEFINE(prefix, name, node, reg, vsel_reg, voltages) \
  195. MC13xxx_DEFINE(MC13783_REG_, name, node, reg, vsel_reg, voltages, \
  196. mc13xxx_regulator_ops)
  197. #define MC13783_FIXED_DEFINE(prefix, name, node, reg, voltages) \
  198. MC13xxx_FIXED_DEFINE(MC13783_REG_, name, node, reg, voltages, \
  199. mc13xxx_fixed_regulator_ops)
  200. #define MC13783_GPO_DEFINE(prefix, name, node, reg, voltages) \
  201. MC13xxx_GPO_DEFINE(MC13783_REG_, name, node, reg, voltages, \
  202. mc13783_gpo_regulator_ops)
  203. #define MC13783_DEFINE_SW(_name, _node, _reg, _vsel_reg, _voltages) \
  204. MC13783_DEFINE(REG, _name, _node, _reg, _vsel_reg, _voltages)
  205. #define MC13783_DEFINE_REGU(_name, _node, _reg, _vsel_reg, _voltages) \
  206. MC13783_DEFINE(REG, _name, _node, _reg, _vsel_reg, _voltages)
  207. static struct mc13xxx_regulator mc13783_regulators[] = {
  208. MC13783_DEFINE_SW(SW1A, sw1a, SWITCHERS0, SWITCHERS0, mc13783_sw1x_val),
  209. MC13783_DEFINE_SW(SW1B, sw1b, SWITCHERS1, SWITCHERS1, mc13783_sw1x_val),
  210. MC13783_DEFINE_SW(SW2A, sw2a, SWITCHERS2, SWITCHERS2, mc13783_sw2x_val),
  211. MC13783_DEFINE_SW(SW2B, sw2b, SWITCHERS3, SWITCHERS3, mc13783_sw2x_val),
  212. MC13783_DEFINE_SW(SW3, sw3, SWITCHERS5, SWITCHERS5, mc13783_sw3_val),
  213. MC13783_FIXED_DEFINE(REG, VAUDIO, vaudio, REGULATORMODE0, mc13783_vaudio_val),
  214. MC13783_FIXED_DEFINE(REG, VIOHI, viohi, REGULATORMODE0, mc13783_viohi_val),
  215. MC13783_DEFINE_REGU(VIOLO, violo, REGULATORMODE0, REGULATORSETTING0,
  216. mc13783_violo_val),
  217. MC13783_DEFINE_REGU(VDIG, vdig, REGULATORMODE0, REGULATORSETTING0,
  218. mc13783_vdig_val),
  219. MC13783_DEFINE_REGU(VGEN, vgen, REGULATORMODE0, REGULATORSETTING0,
  220. mc13783_vgen_val),
  221. MC13783_DEFINE_REGU(VRFDIG, vrfdig, REGULATORMODE0, REGULATORSETTING0,
  222. mc13783_vrfdig_val),
  223. MC13783_DEFINE_REGU(VRFREF, vrfref, REGULATORMODE0, REGULATORSETTING0,
  224. mc13783_vrfref_val),
  225. MC13783_DEFINE_REGU(VRFCP, vrfcp, REGULATORMODE0, REGULATORSETTING0,
  226. mc13783_vrfcp_val),
  227. MC13783_DEFINE_REGU(VSIM, vsim, REGULATORMODE1, REGULATORSETTING0,
  228. mc13783_vsim_val),
  229. MC13783_DEFINE_REGU(VESIM, vesim, REGULATORMODE1, REGULATORSETTING0,
  230. mc13783_vesim_val),
  231. MC13783_DEFINE_REGU(VCAM, vcam, REGULATORMODE1, REGULATORSETTING0,
  232. mc13783_vcam_val),
  233. MC13783_FIXED_DEFINE(REG, VRFBG, vrfbg, REGULATORMODE1, mc13783_vrfbg_val),
  234. MC13783_DEFINE_REGU(VVIB, vvib, REGULATORMODE1, REGULATORSETTING1,
  235. mc13783_vvib_val),
  236. MC13783_DEFINE_REGU(VRF1, vrf1, REGULATORMODE1, REGULATORSETTING1,
  237. mc13783_vrf_val),
  238. MC13783_DEFINE_REGU(VRF2, vrf2, REGULATORMODE1, REGULATORSETTING1,
  239. mc13783_vrf_val),
  240. MC13783_DEFINE_REGU(VMMC1, vmmc1, REGULATORMODE1, REGULATORSETTING1,
  241. mc13783_vmmc_val),
  242. MC13783_DEFINE_REGU(VMMC2, vmmc2, REGULATORMODE1, REGULATORSETTING1,
  243. mc13783_vmmc_val),
  244. MC13783_GPO_DEFINE(REG, GPO1, gpo1, POWERMISC, mc13783_gpo_val),
  245. MC13783_GPO_DEFINE(REG, GPO2, gpo1, POWERMISC, mc13783_gpo_val),
  246. MC13783_GPO_DEFINE(REG, GPO3, gpo1, POWERMISC, mc13783_gpo_val),
  247. MC13783_GPO_DEFINE(REG, GPO4, gpo1, POWERMISC, mc13783_gpo_val),
  248. MC13783_GPO_DEFINE(REG, PWGT1SPI, pwgt1spi, POWERMISC, mc13783_pwgtdrv_val),
  249. MC13783_GPO_DEFINE(REG, PWGT2SPI, pwgt2spi, POWERMISC, mc13783_pwgtdrv_val),
  250. };
  251. static int mc13783_powermisc_rmw(struct mc13xxx_regulator_priv *priv, u32 mask,
  252. u32 val)
  253. {
  254. struct mc13xxx *mc13783 = priv->mc13xxx;
  255. int ret;
  256. u32 valread;
  257. BUG_ON(val & ~mask);
  258. mc13xxx_lock(priv->mc13xxx);
  259. ret = mc13xxx_reg_read(mc13783, MC13783_REG_POWERMISC, &valread);
  260. if (ret)
  261. goto out;
  262. /* Update the stored state for Power Gates. */
  263. priv->powermisc_pwgt_state =
  264. (priv->powermisc_pwgt_state & ~mask) | val;
  265. priv->powermisc_pwgt_state &= MC13783_REG_POWERMISC_PWGTSPI_M;
  266. /* Construct the new register value */
  267. valread = (valread & ~mask) | val;
  268. /* Overwrite the PWGTxEN with the stored version */
  269. valread = (valread & ~MC13783_REG_POWERMISC_PWGTSPI_M) |
  270. priv->powermisc_pwgt_state;
  271. ret = mc13xxx_reg_write(mc13783, MC13783_REG_POWERMISC, valread);
  272. out:
  273. mc13xxx_unlock(priv->mc13xxx);
  274. return ret;
  275. }
  276. static int mc13783_gpo_regulator_enable(struct regulator_dev *rdev)
  277. {
  278. struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
  279. struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators;
  280. int id = rdev_get_id(rdev);
  281. u32 en_val = mc13xxx_regulators[id].enable_bit;
  282. dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
  283. /* Power Gate enable value is 0 */
  284. if (id == MC13783_REG_PWGT1SPI ||
  285. id == MC13783_REG_PWGT2SPI)
  286. en_val = 0;
  287. return mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit,
  288. en_val);
  289. }
  290. static int mc13783_gpo_regulator_disable(struct regulator_dev *rdev)
  291. {
  292. struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
  293. struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators;
  294. int id = rdev_get_id(rdev);
  295. u32 dis_val = 0;
  296. dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
  297. /* Power Gate disable value is 1 */
  298. if (id == MC13783_REG_PWGT1SPI ||
  299. id == MC13783_REG_PWGT2SPI)
  300. dis_val = mc13xxx_regulators[id].enable_bit;
  301. return mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit,
  302. dis_val);
  303. }
  304. static int mc13783_gpo_regulator_is_enabled(struct regulator_dev *rdev)
  305. {
  306. struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
  307. struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators;
  308. int ret, id = rdev_get_id(rdev);
  309. unsigned int val;
  310. mc13xxx_lock(priv->mc13xxx);
  311. ret = mc13xxx_reg_read(priv->mc13xxx, mc13xxx_regulators[id].reg, &val);
  312. mc13xxx_unlock(priv->mc13xxx);
  313. if (ret)
  314. return ret;
  315. /* Power Gates state is stored in powermisc_pwgt_state
  316. * where the meaning of bits is negated */
  317. val = (val & ~MC13783_REG_POWERMISC_PWGTSPI_M) |
  318. (priv->powermisc_pwgt_state ^ MC13783_REG_POWERMISC_PWGTSPI_M);
  319. return (val & mc13xxx_regulators[id].enable_bit) != 0;
  320. }
  321. static const struct regulator_ops mc13783_gpo_regulator_ops = {
  322. .enable = mc13783_gpo_regulator_enable,
  323. .disable = mc13783_gpo_regulator_disable,
  324. .is_enabled = mc13783_gpo_regulator_is_enabled,
  325. .list_voltage = regulator_list_voltage_table,
  326. .set_voltage = mc13xxx_fixed_regulator_set_voltage,
  327. };
  328. static int mc13783_regulator_probe(struct platform_device *pdev)
  329. {
  330. struct mc13xxx_regulator_priv *priv;
  331. struct mc13xxx *mc13783 = dev_get_drvdata(pdev->dev.parent);
  332. struct mc13xxx_regulator_platform_data *pdata =
  333. dev_get_platdata(&pdev->dev);
  334. struct mc13xxx_regulator_init_data *mc13xxx_data;
  335. struct regulator_config config = { };
  336. int i, num_regulators;
  337. num_regulators = mc13xxx_get_num_regulators_dt(pdev);
  338. if (num_regulators <= 0 && pdata)
  339. num_regulators = pdata->num_regulators;
  340. if (num_regulators <= 0)
  341. return -EINVAL;
  342. priv = devm_kzalloc(&pdev->dev,
  343. struct_size(priv, regulators, num_regulators),
  344. GFP_KERNEL);
  345. if (!priv)
  346. return -ENOMEM;
  347. priv->num_regulators = num_regulators;
  348. priv->mc13xxx_regulators = mc13783_regulators;
  349. priv->mc13xxx = mc13783;
  350. platform_set_drvdata(pdev, priv);
  351. mc13xxx_data = mc13xxx_parse_regulators_dt(pdev, mc13783_regulators,
  352. ARRAY_SIZE(mc13783_regulators));
  353. for (i = 0; i < priv->num_regulators; i++) {
  354. struct regulator_init_data *init_data;
  355. struct regulator_desc *desc;
  356. struct device_node *node = NULL;
  357. int id;
  358. if (mc13xxx_data) {
  359. id = mc13xxx_data[i].id;
  360. init_data = mc13xxx_data[i].init_data;
  361. node = mc13xxx_data[i].node;
  362. } else {
  363. id = pdata->regulators[i].id;
  364. init_data = pdata->regulators[i].init_data;
  365. }
  366. desc = &mc13783_regulators[id].desc;
  367. config.dev = &pdev->dev;
  368. config.init_data = init_data;
  369. config.driver_data = priv;
  370. config.of_node = node;
  371. priv->regulators[i] = devm_regulator_register(&pdev->dev, desc,
  372. &config);
  373. if (IS_ERR(priv->regulators[i])) {
  374. dev_err(&pdev->dev, "failed to register regulator %s\n",
  375. mc13783_regulators[i].desc.name);
  376. return PTR_ERR(priv->regulators[i]);
  377. }
  378. }
  379. return 0;
  380. }
  381. static struct platform_driver mc13783_regulator_driver = {
  382. .driver = {
  383. .name = "mc13783-regulator",
  384. },
  385. .probe = mc13783_regulator_probe,
  386. };
  387. static int __init mc13783_regulator_init(void)
  388. {
  389. return platform_driver_register(&mc13783_regulator_driver);
  390. }
  391. subsys_initcall(mc13783_regulator_init);
  392. static void __exit mc13783_regulator_exit(void)
  393. {
  394. platform_driver_unregister(&mc13783_regulator_driver);
  395. }
  396. module_exit(mc13783_regulator_exit);
  397. MODULE_LICENSE("GPL v2");
  398. MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
  399. MODULE_DESCRIPTION("Regulator Driver for Freescale MC13783 PMIC");
  400. MODULE_ALIAS("platform:mc13783-regulator");