mcp251x.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* CAN bus driver for Microchip 251x/25625 CAN Controller with SPI Interface
  3. *
  4. * MCP2510 support and bug fixes by Christian Pellegrin
  5. * <chripell@evolware.org>
  6. *
  7. * Copyright 2009 Christian Pellegrin EVOL S.r.l.
  8. *
  9. * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
  10. * Written under contract by:
  11. * Chris Elston, Katalix Systems, Ltd.
  12. *
  13. * Based on Microchip MCP251x CAN controller driver written by
  14. * David Vrabel, Copyright 2006 Arcom Control Systems Ltd.
  15. *
  16. * Based on CAN bus driver for the CCAN controller written by
  17. * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
  18. * - Simon Kallweit, intefo AG
  19. * Copyright 2007
  20. */
  21. #include <linux/can/core.h>
  22. #include <linux/can/dev.h>
  23. #include <linux/can/led.h>
  24. #include <linux/can/platform/mcp251x.h>
  25. #include <linux/clk.h>
  26. #include <linux/completion.h>
  27. #include <linux/delay.h>
  28. #include <linux/device.h>
  29. #include <linux/freezer.h>
  30. #include <linux/interrupt.h>
  31. #include <linux/io.h>
  32. #include <linux/kernel.h>
  33. #include <linux/module.h>
  34. #include <linux/netdevice.h>
  35. #include <linux/property.h>
  36. #include <linux/platform_device.h>
  37. #include <linux/slab.h>
  38. #include <linux/spi/spi.h>
  39. #include <linux/uaccess.h>
  40. #include <linux/regulator/consumer.h>
  41. /* SPI interface instruction set */
  42. #define INSTRUCTION_WRITE 0x02
  43. #define INSTRUCTION_READ 0x03
  44. #define INSTRUCTION_BIT_MODIFY 0x05
  45. #define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n))
  46. #define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94)
  47. #define INSTRUCTION_RESET 0xC0
  48. #define RTS_TXB0 0x01
  49. #define RTS_TXB1 0x02
  50. #define RTS_TXB2 0x04
  51. #define INSTRUCTION_RTS(n) (0x80 | ((n) & 0x07))
  52. /* MPC251x registers */
  53. #define CANSTAT 0x0e
  54. #define CANCTRL 0x0f
  55. # define CANCTRL_REQOP_MASK 0xe0
  56. # define CANCTRL_REQOP_CONF 0x80
  57. # define CANCTRL_REQOP_LISTEN_ONLY 0x60
  58. # define CANCTRL_REQOP_LOOPBACK 0x40
  59. # define CANCTRL_REQOP_SLEEP 0x20
  60. # define CANCTRL_REQOP_NORMAL 0x00
  61. # define CANCTRL_OSM 0x08
  62. # define CANCTRL_ABAT 0x10
  63. #define TEC 0x1c
  64. #define REC 0x1d
  65. #define CNF1 0x2a
  66. # define CNF1_SJW_SHIFT 6
  67. #define CNF2 0x29
  68. # define CNF2_BTLMODE 0x80
  69. # define CNF2_SAM 0x40
  70. # define CNF2_PS1_SHIFT 3
  71. #define CNF3 0x28
  72. # define CNF3_SOF 0x08
  73. # define CNF3_WAKFIL 0x04
  74. # define CNF3_PHSEG2_MASK 0x07
  75. #define CANINTE 0x2b
  76. # define CANINTE_MERRE 0x80
  77. # define CANINTE_WAKIE 0x40
  78. # define CANINTE_ERRIE 0x20
  79. # define CANINTE_TX2IE 0x10
  80. # define CANINTE_TX1IE 0x08
  81. # define CANINTE_TX0IE 0x04
  82. # define CANINTE_RX1IE 0x02
  83. # define CANINTE_RX0IE 0x01
  84. #define CANINTF 0x2c
  85. # define CANINTF_MERRF 0x80
  86. # define CANINTF_WAKIF 0x40
  87. # define CANINTF_ERRIF 0x20
  88. # define CANINTF_TX2IF 0x10
  89. # define CANINTF_TX1IF 0x08
  90. # define CANINTF_TX0IF 0x04
  91. # define CANINTF_RX1IF 0x02
  92. # define CANINTF_RX0IF 0x01
  93. # define CANINTF_RX (CANINTF_RX0IF | CANINTF_RX1IF)
  94. # define CANINTF_TX (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)
  95. # define CANINTF_ERR (CANINTF_ERRIF)
  96. #define EFLG 0x2d
  97. # define EFLG_EWARN 0x01
  98. # define EFLG_RXWAR 0x02
  99. # define EFLG_TXWAR 0x04
  100. # define EFLG_RXEP 0x08
  101. # define EFLG_TXEP 0x10
  102. # define EFLG_TXBO 0x20
  103. # define EFLG_RX0OVR 0x40
  104. # define EFLG_RX1OVR 0x80
  105. #define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF)
  106. # define TXBCTRL_ABTF 0x40
  107. # define TXBCTRL_MLOA 0x20
  108. # define TXBCTRL_TXERR 0x10
  109. # define TXBCTRL_TXREQ 0x08
  110. #define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF)
  111. # define SIDH_SHIFT 3
  112. #define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF)
  113. # define SIDL_SID_MASK 7
  114. # define SIDL_SID_SHIFT 5
  115. # define SIDL_EXIDE_SHIFT 3
  116. # define SIDL_EID_SHIFT 16
  117. # define SIDL_EID_MASK 3
  118. #define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF)
  119. #define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF)
  120. #define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF)
  121. # define DLC_RTR_SHIFT 6
  122. #define TXBCTRL_OFF 0
  123. #define TXBSIDH_OFF 1
  124. #define TXBSIDL_OFF 2
  125. #define TXBEID8_OFF 3
  126. #define TXBEID0_OFF 4
  127. #define TXBDLC_OFF 5
  128. #define TXBDAT_OFF 6
  129. #define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF)
  130. # define RXBCTRL_BUKT 0x04
  131. # define RXBCTRL_RXM0 0x20
  132. # define RXBCTRL_RXM1 0x40
  133. #define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF)
  134. # define RXBSIDH_SHIFT 3
  135. #define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF)
  136. # define RXBSIDL_IDE 0x08
  137. # define RXBSIDL_SRR 0x10
  138. # define RXBSIDL_EID 3
  139. # define RXBSIDL_SHIFT 5
  140. #define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF)
  141. #define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF)
  142. #define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF)
  143. # define RXBDLC_LEN_MASK 0x0f
  144. # define RXBDLC_RTR 0x40
  145. #define RXBCTRL_OFF 0
  146. #define RXBSIDH_OFF 1
  147. #define RXBSIDL_OFF 2
  148. #define RXBEID8_OFF 3
  149. #define RXBEID0_OFF 4
  150. #define RXBDLC_OFF 5
  151. #define RXBDAT_OFF 6
  152. #define RXFSID(n) ((n < 3) ? 0 : 4)
  153. #define RXFSIDH(n) ((n) * 4 + RXFSID(n))
  154. #define RXFSIDL(n) ((n) * 4 + 1 + RXFSID(n))
  155. #define RXFEID8(n) ((n) * 4 + 2 + RXFSID(n))
  156. #define RXFEID0(n) ((n) * 4 + 3 + RXFSID(n))
  157. #define RXMSIDH(n) ((n) * 4 + 0x20)
  158. #define RXMSIDL(n) ((n) * 4 + 0x21)
  159. #define RXMEID8(n) ((n) * 4 + 0x22)
  160. #define RXMEID0(n) ((n) * 4 + 0x23)
  161. #define GET_BYTE(val, byte) \
  162. (((val) >> ((byte) * 8)) & 0xff)
  163. #define SET_BYTE(val, byte) \
  164. (((val) & 0xff) << ((byte) * 8))
  165. /* Buffer size required for the largest SPI transfer (i.e., reading a
  166. * frame)
  167. */
  168. #define CAN_FRAME_MAX_DATA_LEN 8
  169. #define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN)
  170. #define CAN_FRAME_MAX_BITS 128
  171. #define TX_ECHO_SKB_MAX 1
  172. #define MCP251X_OST_DELAY_MS (5)
  173. #define DEVICE_NAME "mcp251x"
  174. static const struct can_bittiming_const mcp251x_bittiming_const = {
  175. .name = DEVICE_NAME,
  176. .tseg1_min = 3,
  177. .tseg1_max = 16,
  178. .tseg2_min = 2,
  179. .tseg2_max = 8,
  180. .sjw_max = 4,
  181. .brp_min = 1,
  182. .brp_max = 64,
  183. .brp_inc = 1,
  184. };
  185. enum mcp251x_model {
  186. CAN_MCP251X_MCP2510 = 0x2510,
  187. CAN_MCP251X_MCP2515 = 0x2515,
  188. CAN_MCP251X_MCP25625 = 0x25625,
  189. };
  190. struct mcp251x_priv {
  191. struct can_priv can;
  192. struct net_device *net;
  193. struct spi_device *spi;
  194. enum mcp251x_model model;
  195. struct mutex mcp_lock; /* SPI device lock */
  196. u8 *spi_tx_buf;
  197. u8 *spi_rx_buf;
  198. struct sk_buff *tx_skb;
  199. int tx_len;
  200. struct workqueue_struct *wq;
  201. struct work_struct tx_work;
  202. struct work_struct restart_work;
  203. int force_quit;
  204. int after_suspend;
  205. #define AFTER_SUSPEND_UP 1
  206. #define AFTER_SUSPEND_DOWN 2
  207. #define AFTER_SUSPEND_POWER 4
  208. #define AFTER_SUSPEND_RESTART 8
  209. int restart_tx;
  210. struct regulator *power;
  211. struct regulator *transceiver;
  212. struct clk *clk;
  213. };
  214. #define MCP251X_IS(_model) \
  215. static inline int mcp251x_is_##_model(struct spi_device *spi) \
  216. { \
  217. struct mcp251x_priv *priv = spi_get_drvdata(spi); \
  218. return priv->model == CAN_MCP251X_MCP##_model; \
  219. }
  220. MCP251X_IS(2510);
  221. static void mcp251x_clean(struct net_device *net)
  222. {
  223. struct mcp251x_priv *priv = netdev_priv(net);
  224. if (priv->tx_skb || priv->tx_len)
  225. net->stats.tx_errors++;
  226. dev_kfree_skb(priv->tx_skb);
  227. if (priv->tx_len)
  228. can_free_echo_skb(priv->net, 0);
  229. priv->tx_skb = NULL;
  230. priv->tx_len = 0;
  231. }
  232. /* Note about handling of error return of mcp251x_spi_trans: accessing
  233. * registers via SPI is not really different conceptually than using
  234. * normal I/O assembler instructions, although it's much more
  235. * complicated from a practical POV. So it's not advisable to always
  236. * check the return value of this function. Imagine that every
  237. * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
  238. * error();", it would be a great mess (well there are some situation
  239. * when exception handling C++ like could be useful after all). So we
  240. * just check that transfers are OK at the beginning of our
  241. * conversation with the chip and to avoid doing really nasty things
  242. * (like injecting bogus packets in the network stack).
  243. */
  244. static int mcp251x_spi_trans(struct spi_device *spi, int len)
  245. {
  246. struct mcp251x_priv *priv = spi_get_drvdata(spi);
  247. struct spi_transfer t = {
  248. .tx_buf = priv->spi_tx_buf,
  249. .rx_buf = priv->spi_rx_buf,
  250. .len = len,
  251. .cs_change = 0,
  252. };
  253. struct spi_message m;
  254. int ret;
  255. spi_message_init(&m);
  256. spi_message_add_tail(&t, &m);
  257. ret = spi_sync(spi, &m);
  258. if (ret)
  259. dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
  260. return ret;
  261. }
  262. static u8 mcp251x_read_reg(struct spi_device *spi, u8 reg)
  263. {
  264. struct mcp251x_priv *priv = spi_get_drvdata(spi);
  265. u8 val = 0;
  266. priv->spi_tx_buf[0] = INSTRUCTION_READ;
  267. priv->spi_tx_buf[1] = reg;
  268. mcp251x_spi_trans(spi, 3);
  269. val = priv->spi_rx_buf[2];
  270. return val;
  271. }
  272. static void mcp251x_read_2regs(struct spi_device *spi, u8 reg, u8 *v1, u8 *v2)
  273. {
  274. struct mcp251x_priv *priv = spi_get_drvdata(spi);
  275. priv->spi_tx_buf[0] = INSTRUCTION_READ;
  276. priv->spi_tx_buf[1] = reg;
  277. mcp251x_spi_trans(spi, 4);
  278. *v1 = priv->spi_rx_buf[2];
  279. *v2 = priv->spi_rx_buf[3];
  280. }
  281. static void mcp251x_write_reg(struct spi_device *spi, u8 reg, u8 val)
  282. {
  283. struct mcp251x_priv *priv = spi_get_drvdata(spi);
  284. priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
  285. priv->spi_tx_buf[1] = reg;
  286. priv->spi_tx_buf[2] = val;
  287. mcp251x_spi_trans(spi, 3);
  288. }
  289. static void mcp251x_write_bits(struct spi_device *spi, u8 reg,
  290. u8 mask, u8 val)
  291. {
  292. struct mcp251x_priv *priv = spi_get_drvdata(spi);
  293. priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY;
  294. priv->spi_tx_buf[1] = reg;
  295. priv->spi_tx_buf[2] = mask;
  296. priv->spi_tx_buf[3] = val;
  297. mcp251x_spi_trans(spi, 4);
  298. }
  299. static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf,
  300. int len, int tx_buf_idx)
  301. {
  302. struct mcp251x_priv *priv = spi_get_drvdata(spi);
  303. if (mcp251x_is_2510(spi)) {
  304. int i;
  305. for (i = 1; i < TXBDAT_OFF + len; i++)
  306. mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i,
  307. buf[i]);
  308. } else {
  309. memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len);
  310. mcp251x_spi_trans(spi, TXBDAT_OFF + len);
  311. }
  312. }
  313. static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame,
  314. int tx_buf_idx)
  315. {
  316. struct mcp251x_priv *priv = spi_get_drvdata(spi);
  317. u32 sid, eid, exide, rtr;
  318. u8 buf[SPI_TRANSFER_BUF_LEN];
  319. exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */
  320. if (exide)
  321. sid = (frame->can_id & CAN_EFF_MASK) >> 18;
  322. else
  323. sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */
  324. eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */
  325. rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */
  326. buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx);
  327. buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT;
  328. buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) |
  329. (exide << SIDL_EXIDE_SHIFT) |
  330. ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK);
  331. buf[TXBEID8_OFF] = GET_BYTE(eid, 1);
  332. buf[TXBEID0_OFF] = GET_BYTE(eid, 0);
  333. buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->can_dlc;
  334. memcpy(buf + TXBDAT_OFF, frame->data, frame->can_dlc);
  335. mcp251x_hw_tx_frame(spi, buf, frame->can_dlc, tx_buf_idx);
  336. /* use INSTRUCTION_RTS, to avoid "repeated frame problem" */
  337. priv->spi_tx_buf[0] = INSTRUCTION_RTS(1 << tx_buf_idx);
  338. mcp251x_spi_trans(priv->spi, 1);
  339. }
  340. static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf,
  341. int buf_idx)
  342. {
  343. struct mcp251x_priv *priv = spi_get_drvdata(spi);
  344. if (mcp251x_is_2510(spi)) {
  345. int i, len;
  346. for (i = 1; i < RXBDAT_OFF; i++)
  347. buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
  348. len = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
  349. for (; i < (RXBDAT_OFF + len); i++)
  350. buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
  351. } else {
  352. priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx);
  353. mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN);
  354. memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN);
  355. }
  356. }
  357. static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx)
  358. {
  359. struct mcp251x_priv *priv = spi_get_drvdata(spi);
  360. struct sk_buff *skb;
  361. struct can_frame *frame;
  362. u8 buf[SPI_TRANSFER_BUF_LEN];
  363. skb = alloc_can_skb(priv->net, &frame);
  364. if (!skb) {
  365. dev_err(&spi->dev, "cannot allocate RX skb\n");
  366. priv->net->stats.rx_dropped++;
  367. return;
  368. }
  369. mcp251x_hw_rx_frame(spi, buf, buf_idx);
  370. if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) {
  371. /* Extended ID format */
  372. frame->can_id = CAN_EFF_FLAG;
  373. frame->can_id |=
  374. /* Extended ID part */
  375. SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) |
  376. SET_BYTE(buf[RXBEID8_OFF], 1) |
  377. SET_BYTE(buf[RXBEID0_OFF], 0) |
  378. /* Standard ID part */
  379. (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
  380. (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18);
  381. /* Remote transmission request */
  382. if (buf[RXBDLC_OFF] & RXBDLC_RTR)
  383. frame->can_id |= CAN_RTR_FLAG;
  384. } else {
  385. /* Standard ID format */
  386. frame->can_id =
  387. (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
  388. (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT);
  389. if (buf[RXBSIDL_OFF] & RXBSIDL_SRR)
  390. frame->can_id |= CAN_RTR_FLAG;
  391. }
  392. /* Data length */
  393. frame->can_dlc = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
  394. memcpy(frame->data, buf + RXBDAT_OFF, frame->can_dlc);
  395. priv->net->stats.rx_packets++;
  396. priv->net->stats.rx_bytes += frame->can_dlc;
  397. can_led_event(priv->net, CAN_LED_EVENT_RX);
  398. netif_rx_ni(skb);
  399. }
  400. static void mcp251x_hw_sleep(struct spi_device *spi)
  401. {
  402. mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP);
  403. }
  404. static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb,
  405. struct net_device *net)
  406. {
  407. struct mcp251x_priv *priv = netdev_priv(net);
  408. struct spi_device *spi = priv->spi;
  409. if (priv->tx_skb || priv->tx_len) {
  410. dev_warn(&spi->dev, "hard_xmit called while tx busy\n");
  411. return NETDEV_TX_BUSY;
  412. }
  413. if (can_dropped_invalid_skb(net, skb))
  414. return NETDEV_TX_OK;
  415. netif_stop_queue(net);
  416. priv->tx_skb = skb;
  417. queue_work(priv->wq, &priv->tx_work);
  418. return NETDEV_TX_OK;
  419. }
  420. static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode)
  421. {
  422. struct mcp251x_priv *priv = netdev_priv(net);
  423. switch (mode) {
  424. case CAN_MODE_START:
  425. mcp251x_clean(net);
  426. /* We have to delay work since SPI I/O may sleep */
  427. priv->can.state = CAN_STATE_ERROR_ACTIVE;
  428. priv->restart_tx = 1;
  429. if (priv->can.restart_ms == 0)
  430. priv->after_suspend = AFTER_SUSPEND_RESTART;
  431. queue_work(priv->wq, &priv->restart_work);
  432. break;
  433. default:
  434. return -EOPNOTSUPP;
  435. }
  436. return 0;
  437. }
  438. static int mcp251x_set_normal_mode(struct spi_device *spi)
  439. {
  440. struct mcp251x_priv *priv = spi_get_drvdata(spi);
  441. unsigned long timeout;
  442. /* Enable interrupts */
  443. mcp251x_write_reg(spi, CANINTE,
  444. CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE |
  445. CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE);
  446. if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
  447. /* Put device into loopback mode */
  448. mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK);
  449. } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
  450. /* Put device into listen-only mode */
  451. mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY);
  452. } else {
  453. /* Put device into normal mode */
  454. mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL);
  455. /* Wait for the device to enter normal mode */
  456. timeout = jiffies + HZ;
  457. while (mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) {
  458. schedule();
  459. if (time_after(jiffies, timeout)) {
  460. dev_err(&spi->dev, "MCP251x didn't enter in normal mode\n");
  461. return -EBUSY;
  462. }
  463. }
  464. }
  465. priv->can.state = CAN_STATE_ERROR_ACTIVE;
  466. return 0;
  467. }
  468. static int mcp251x_do_set_bittiming(struct net_device *net)
  469. {
  470. struct mcp251x_priv *priv = netdev_priv(net);
  471. struct can_bittiming *bt = &priv->can.bittiming;
  472. struct spi_device *spi = priv->spi;
  473. mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) |
  474. (bt->brp - 1));
  475. mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE |
  476. (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
  477. CNF2_SAM : 0) |
  478. ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) |
  479. (bt->prop_seg - 1));
  480. mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK,
  481. (bt->phase_seg2 - 1));
  482. dev_dbg(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n",
  483. mcp251x_read_reg(spi, CNF1),
  484. mcp251x_read_reg(spi, CNF2),
  485. mcp251x_read_reg(spi, CNF3));
  486. return 0;
  487. }
  488. static int mcp251x_setup(struct net_device *net, struct spi_device *spi)
  489. {
  490. mcp251x_do_set_bittiming(net);
  491. mcp251x_write_reg(spi, RXBCTRL(0),
  492. RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1);
  493. mcp251x_write_reg(spi, RXBCTRL(1),
  494. RXBCTRL_RXM0 | RXBCTRL_RXM1);
  495. return 0;
  496. }
  497. static int mcp251x_hw_reset(struct spi_device *spi)
  498. {
  499. struct mcp251x_priv *priv = spi_get_drvdata(spi);
  500. unsigned long timeout;
  501. int ret;
  502. /* Wait for oscillator startup timer after power up */
  503. mdelay(MCP251X_OST_DELAY_MS);
  504. priv->spi_tx_buf[0] = INSTRUCTION_RESET;
  505. ret = mcp251x_spi_trans(spi, 1);
  506. if (ret)
  507. return ret;
  508. /* Wait for oscillator startup timer after reset */
  509. mdelay(MCP251X_OST_DELAY_MS);
  510. /* Wait for reset to finish */
  511. timeout = jiffies + HZ;
  512. while ((mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) !=
  513. CANCTRL_REQOP_CONF) {
  514. usleep_range(MCP251X_OST_DELAY_MS * 1000,
  515. MCP251X_OST_DELAY_MS * 1000 * 2);
  516. if (time_after(jiffies, timeout)) {
  517. dev_err(&spi->dev,
  518. "MCP251x didn't enter in conf mode after reset\n");
  519. return -EBUSY;
  520. }
  521. }
  522. return 0;
  523. }
  524. static int mcp251x_hw_probe(struct spi_device *spi)
  525. {
  526. u8 ctrl;
  527. int ret;
  528. ret = mcp251x_hw_reset(spi);
  529. if (ret)
  530. return ret;
  531. ctrl = mcp251x_read_reg(spi, CANCTRL);
  532. dev_dbg(&spi->dev, "CANCTRL 0x%02x\n", ctrl);
  533. /* Check for power up default value */
  534. if ((ctrl & 0x17) != 0x07)
  535. return -ENODEV;
  536. return 0;
  537. }
  538. static int mcp251x_power_enable(struct regulator *reg, int enable)
  539. {
  540. if (IS_ERR_OR_NULL(reg))
  541. return 0;
  542. if (enable)
  543. return regulator_enable(reg);
  544. else
  545. return regulator_disable(reg);
  546. }
  547. static int mcp251x_stop(struct net_device *net)
  548. {
  549. struct mcp251x_priv *priv = netdev_priv(net);
  550. struct spi_device *spi = priv->spi;
  551. close_candev(net);
  552. priv->force_quit = 1;
  553. free_irq(spi->irq, priv);
  554. destroy_workqueue(priv->wq);
  555. priv->wq = NULL;
  556. mutex_lock(&priv->mcp_lock);
  557. /* Disable and clear pending interrupts */
  558. mcp251x_write_reg(spi, CANINTE, 0x00);
  559. mcp251x_write_reg(spi, CANINTF, 0x00);
  560. mcp251x_write_reg(spi, TXBCTRL(0), 0);
  561. mcp251x_clean(net);
  562. mcp251x_hw_sleep(spi);
  563. mcp251x_power_enable(priv->transceiver, 0);
  564. priv->can.state = CAN_STATE_STOPPED;
  565. mutex_unlock(&priv->mcp_lock);
  566. can_led_event(net, CAN_LED_EVENT_STOP);
  567. return 0;
  568. }
  569. static void mcp251x_error_skb(struct net_device *net, int can_id, int data1)
  570. {
  571. struct sk_buff *skb;
  572. struct can_frame *frame;
  573. skb = alloc_can_err_skb(net, &frame);
  574. if (skb) {
  575. frame->can_id |= can_id;
  576. frame->data[1] = data1;
  577. netif_rx_ni(skb);
  578. } else {
  579. netdev_err(net, "cannot allocate error skb\n");
  580. }
  581. }
  582. static void mcp251x_tx_work_handler(struct work_struct *ws)
  583. {
  584. struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
  585. tx_work);
  586. struct spi_device *spi = priv->spi;
  587. struct net_device *net = priv->net;
  588. struct can_frame *frame;
  589. mutex_lock(&priv->mcp_lock);
  590. if (priv->tx_skb) {
  591. if (priv->can.state == CAN_STATE_BUS_OFF) {
  592. mcp251x_clean(net);
  593. } else {
  594. frame = (struct can_frame *)priv->tx_skb->data;
  595. if (frame->can_dlc > CAN_FRAME_MAX_DATA_LEN)
  596. frame->can_dlc = CAN_FRAME_MAX_DATA_LEN;
  597. mcp251x_hw_tx(spi, frame, 0);
  598. priv->tx_len = 1 + frame->can_dlc;
  599. can_put_echo_skb(priv->tx_skb, net, 0);
  600. priv->tx_skb = NULL;
  601. }
  602. }
  603. mutex_unlock(&priv->mcp_lock);
  604. }
  605. static void mcp251x_restart_work_handler(struct work_struct *ws)
  606. {
  607. struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
  608. restart_work);
  609. struct spi_device *spi = priv->spi;
  610. struct net_device *net = priv->net;
  611. mutex_lock(&priv->mcp_lock);
  612. if (priv->after_suspend) {
  613. mcp251x_hw_reset(spi);
  614. mcp251x_setup(net, spi);
  615. priv->force_quit = 0;
  616. if (priv->after_suspend & AFTER_SUSPEND_RESTART) {
  617. mcp251x_set_normal_mode(spi);
  618. } else if (priv->after_suspend & AFTER_SUSPEND_UP) {
  619. netif_device_attach(net);
  620. mcp251x_clean(net);
  621. mcp251x_set_normal_mode(spi);
  622. netif_wake_queue(net);
  623. } else {
  624. mcp251x_hw_sleep(spi);
  625. }
  626. priv->after_suspend = 0;
  627. }
  628. if (priv->restart_tx) {
  629. priv->restart_tx = 0;
  630. mcp251x_write_reg(spi, TXBCTRL(0), 0);
  631. mcp251x_clean(net);
  632. netif_wake_queue(net);
  633. mcp251x_error_skb(net, CAN_ERR_RESTARTED, 0);
  634. }
  635. mutex_unlock(&priv->mcp_lock);
  636. }
  637. static irqreturn_t mcp251x_can_ist(int irq, void *dev_id)
  638. {
  639. struct mcp251x_priv *priv = dev_id;
  640. struct spi_device *spi = priv->spi;
  641. struct net_device *net = priv->net;
  642. mutex_lock(&priv->mcp_lock);
  643. while (!priv->force_quit) {
  644. enum can_state new_state;
  645. u8 intf, eflag;
  646. u8 clear_intf = 0;
  647. int can_id = 0, data1 = 0;
  648. mcp251x_read_2regs(spi, CANINTF, &intf, &eflag);
  649. /* mask out flags we don't care about */
  650. intf &= CANINTF_RX | CANINTF_TX | CANINTF_ERR;
  651. /* receive buffer 0 */
  652. if (intf & CANINTF_RX0IF) {
  653. mcp251x_hw_rx(spi, 0);
  654. /* Free one buffer ASAP
  655. * (The MCP2515/25625 does this automatically.)
  656. */
  657. if (mcp251x_is_2510(spi))
  658. mcp251x_write_bits(spi, CANINTF,
  659. CANINTF_RX0IF, 0x00);
  660. }
  661. /* receive buffer 1 */
  662. if (intf & CANINTF_RX1IF) {
  663. mcp251x_hw_rx(spi, 1);
  664. /* The MCP2515/25625 does this automatically. */
  665. if (mcp251x_is_2510(spi))
  666. clear_intf |= CANINTF_RX1IF;
  667. }
  668. /* any error or tx interrupt we need to clear? */
  669. if (intf & (CANINTF_ERR | CANINTF_TX))
  670. clear_intf |= intf & (CANINTF_ERR | CANINTF_TX);
  671. if (clear_intf)
  672. mcp251x_write_bits(spi, CANINTF, clear_intf, 0x00);
  673. if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR))
  674. mcp251x_write_bits(spi, EFLG, eflag, 0x00);
  675. /* Update can state */
  676. if (eflag & EFLG_TXBO) {
  677. new_state = CAN_STATE_BUS_OFF;
  678. can_id |= CAN_ERR_BUSOFF;
  679. } else if (eflag & EFLG_TXEP) {
  680. new_state = CAN_STATE_ERROR_PASSIVE;
  681. can_id |= CAN_ERR_CRTL;
  682. data1 |= CAN_ERR_CRTL_TX_PASSIVE;
  683. } else if (eflag & EFLG_RXEP) {
  684. new_state = CAN_STATE_ERROR_PASSIVE;
  685. can_id |= CAN_ERR_CRTL;
  686. data1 |= CAN_ERR_CRTL_RX_PASSIVE;
  687. } else if (eflag & EFLG_TXWAR) {
  688. new_state = CAN_STATE_ERROR_WARNING;
  689. can_id |= CAN_ERR_CRTL;
  690. data1 |= CAN_ERR_CRTL_TX_WARNING;
  691. } else if (eflag & EFLG_RXWAR) {
  692. new_state = CAN_STATE_ERROR_WARNING;
  693. can_id |= CAN_ERR_CRTL;
  694. data1 |= CAN_ERR_CRTL_RX_WARNING;
  695. } else {
  696. new_state = CAN_STATE_ERROR_ACTIVE;
  697. }
  698. /* Update can state statistics */
  699. switch (priv->can.state) {
  700. case CAN_STATE_ERROR_ACTIVE:
  701. if (new_state >= CAN_STATE_ERROR_WARNING &&
  702. new_state <= CAN_STATE_BUS_OFF)
  703. priv->can.can_stats.error_warning++;
  704. /* fall through */
  705. case CAN_STATE_ERROR_WARNING:
  706. if (new_state >= CAN_STATE_ERROR_PASSIVE &&
  707. new_state <= CAN_STATE_BUS_OFF)
  708. priv->can.can_stats.error_passive++;
  709. break;
  710. default:
  711. break;
  712. }
  713. priv->can.state = new_state;
  714. if (intf & CANINTF_ERRIF) {
  715. /* Handle overflow counters */
  716. if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) {
  717. if (eflag & EFLG_RX0OVR) {
  718. net->stats.rx_over_errors++;
  719. net->stats.rx_errors++;
  720. }
  721. if (eflag & EFLG_RX1OVR) {
  722. net->stats.rx_over_errors++;
  723. net->stats.rx_errors++;
  724. }
  725. can_id |= CAN_ERR_CRTL;
  726. data1 |= CAN_ERR_CRTL_RX_OVERFLOW;
  727. }
  728. mcp251x_error_skb(net, can_id, data1);
  729. }
  730. if (priv->can.state == CAN_STATE_BUS_OFF) {
  731. if (priv->can.restart_ms == 0) {
  732. priv->force_quit = 1;
  733. priv->can.can_stats.bus_off++;
  734. can_bus_off(net);
  735. mcp251x_hw_sleep(spi);
  736. break;
  737. }
  738. }
  739. if (intf == 0)
  740. break;
  741. if (intf & CANINTF_TX) {
  742. net->stats.tx_packets++;
  743. net->stats.tx_bytes += priv->tx_len - 1;
  744. can_led_event(net, CAN_LED_EVENT_TX);
  745. if (priv->tx_len) {
  746. can_get_echo_skb(net, 0);
  747. priv->tx_len = 0;
  748. }
  749. netif_wake_queue(net);
  750. }
  751. }
  752. mutex_unlock(&priv->mcp_lock);
  753. return IRQ_HANDLED;
  754. }
  755. static int mcp251x_open(struct net_device *net)
  756. {
  757. struct mcp251x_priv *priv = netdev_priv(net);
  758. struct spi_device *spi = priv->spi;
  759. unsigned long flags = 0;
  760. int ret;
  761. ret = open_candev(net);
  762. if (ret) {
  763. dev_err(&spi->dev, "unable to set initial baudrate!\n");
  764. return ret;
  765. }
  766. mutex_lock(&priv->mcp_lock);
  767. mcp251x_power_enable(priv->transceiver, 1);
  768. priv->force_quit = 0;
  769. priv->tx_skb = NULL;
  770. priv->tx_len = 0;
  771. if (!dev_fwnode(&spi->dev))
  772. flags = IRQF_TRIGGER_FALLING;
  773. ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist,
  774. flags | IRQF_ONESHOT, dev_name(&spi->dev),
  775. priv);
  776. if (ret) {
  777. dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
  778. goto out_close;
  779. }
  780. priv->wq = alloc_workqueue("mcp251x_wq", WQ_FREEZABLE | WQ_MEM_RECLAIM,
  781. 0);
  782. if (!priv->wq) {
  783. ret = -ENOMEM;
  784. goto out_clean;
  785. }
  786. INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler);
  787. INIT_WORK(&priv->restart_work, mcp251x_restart_work_handler);
  788. ret = mcp251x_hw_reset(spi);
  789. if (ret)
  790. goto out_free_wq;
  791. ret = mcp251x_setup(net, spi);
  792. if (ret)
  793. goto out_free_wq;
  794. ret = mcp251x_set_normal_mode(spi);
  795. if (ret)
  796. goto out_free_wq;
  797. can_led_event(net, CAN_LED_EVENT_OPEN);
  798. netif_wake_queue(net);
  799. mutex_unlock(&priv->mcp_lock);
  800. return 0;
  801. out_free_wq:
  802. destroy_workqueue(priv->wq);
  803. out_clean:
  804. free_irq(spi->irq, priv);
  805. mcp251x_hw_sleep(spi);
  806. out_close:
  807. mcp251x_power_enable(priv->transceiver, 0);
  808. close_candev(net);
  809. mutex_unlock(&priv->mcp_lock);
  810. return ret;
  811. }
  812. static const struct net_device_ops mcp251x_netdev_ops = {
  813. .ndo_open = mcp251x_open,
  814. .ndo_stop = mcp251x_stop,
  815. .ndo_start_xmit = mcp251x_hard_start_xmit,
  816. .ndo_change_mtu = can_change_mtu,
  817. };
  818. static const struct of_device_id mcp251x_of_match[] = {
  819. {
  820. .compatible = "microchip,mcp2510",
  821. .data = (void *)CAN_MCP251X_MCP2510,
  822. },
  823. {
  824. .compatible = "microchip,mcp2515",
  825. .data = (void *)CAN_MCP251X_MCP2515,
  826. },
  827. {
  828. .compatible = "microchip,mcp25625",
  829. .data = (void *)CAN_MCP251X_MCP25625,
  830. },
  831. { }
  832. };
  833. MODULE_DEVICE_TABLE(of, mcp251x_of_match);
  834. static const struct spi_device_id mcp251x_id_table[] = {
  835. {
  836. .name = "mcp2510",
  837. .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2510,
  838. },
  839. {
  840. .name = "mcp2515",
  841. .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2515,
  842. },
  843. {
  844. .name = "mcp25625",
  845. .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP25625,
  846. },
  847. { }
  848. };
  849. MODULE_DEVICE_TABLE(spi, mcp251x_id_table);
  850. static int mcp251x_can_probe(struct spi_device *spi)
  851. {
  852. const void *match = device_get_match_data(&spi->dev);
  853. struct mcp251x_platform_data *pdata = dev_get_platdata(&spi->dev);
  854. struct net_device *net;
  855. struct mcp251x_priv *priv;
  856. struct clk *clk;
  857. int freq, ret;
  858. clk = devm_clk_get_optional(&spi->dev, NULL);
  859. if (IS_ERR(clk))
  860. return PTR_ERR(clk);
  861. freq = clk_get_rate(clk);
  862. if (freq == 0 && pdata)
  863. freq = pdata->oscillator_frequency;
  864. /* Sanity check */
  865. if (freq < 1000000 || freq > 25000000)
  866. return -ERANGE;
  867. /* Allocate can/net device */
  868. net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX);
  869. if (!net)
  870. return -ENOMEM;
  871. ret = clk_prepare_enable(clk);
  872. if (ret)
  873. goto out_free;
  874. net->netdev_ops = &mcp251x_netdev_ops;
  875. net->flags |= IFF_ECHO;
  876. priv = netdev_priv(net);
  877. priv->can.bittiming_const = &mcp251x_bittiming_const;
  878. priv->can.do_set_mode = mcp251x_do_set_mode;
  879. priv->can.clock.freq = freq / 2;
  880. priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
  881. CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY;
  882. if (match)
  883. priv->model = (enum mcp251x_model)match;
  884. else
  885. priv->model = spi_get_device_id(spi)->driver_data;
  886. priv->net = net;
  887. priv->clk = clk;
  888. spi_set_drvdata(spi, priv);
  889. /* Configure the SPI bus */
  890. spi->bits_per_word = 8;
  891. if (mcp251x_is_2510(spi))
  892. spi->max_speed_hz = spi->max_speed_hz ? : 5 * 1000 * 1000;
  893. else
  894. spi->max_speed_hz = spi->max_speed_hz ? : 10 * 1000 * 1000;
  895. ret = spi_setup(spi);
  896. if (ret)
  897. goto out_clk;
  898. priv->power = devm_regulator_get_optional(&spi->dev, "vdd");
  899. priv->transceiver = devm_regulator_get_optional(&spi->dev, "xceiver");
  900. if ((PTR_ERR(priv->power) == -EPROBE_DEFER) ||
  901. (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) {
  902. ret = -EPROBE_DEFER;
  903. goto out_clk;
  904. }
  905. ret = mcp251x_power_enable(priv->power, 1);
  906. if (ret)
  907. goto out_clk;
  908. priv->spi = spi;
  909. mutex_init(&priv->mcp_lock);
  910. priv->spi_tx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
  911. GFP_KERNEL);
  912. if (!priv->spi_tx_buf) {
  913. ret = -ENOMEM;
  914. goto error_probe;
  915. }
  916. priv->spi_rx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
  917. GFP_KERNEL);
  918. if (!priv->spi_rx_buf) {
  919. ret = -ENOMEM;
  920. goto error_probe;
  921. }
  922. SET_NETDEV_DEV(net, &spi->dev);
  923. /* Here is OK to not lock the MCP, no one knows about it yet */
  924. ret = mcp251x_hw_probe(spi);
  925. if (ret) {
  926. if (ret == -ENODEV)
  927. dev_err(&spi->dev, "Cannot initialize MCP%x. Wrong wiring?\n",
  928. priv->model);
  929. goto error_probe;
  930. }
  931. mcp251x_hw_sleep(spi);
  932. ret = register_candev(net);
  933. if (ret)
  934. goto error_probe;
  935. devm_can_led_init(net);
  936. netdev_info(net, "MCP%x successfully initialized.\n", priv->model);
  937. return 0;
  938. error_probe:
  939. mcp251x_power_enable(priv->power, 0);
  940. out_clk:
  941. clk_disable_unprepare(clk);
  942. out_free:
  943. free_candev(net);
  944. dev_err(&spi->dev, "Probe failed, err=%d\n", -ret);
  945. return ret;
  946. }
  947. static int mcp251x_can_remove(struct spi_device *spi)
  948. {
  949. struct mcp251x_priv *priv = spi_get_drvdata(spi);
  950. struct net_device *net = priv->net;
  951. unregister_candev(net);
  952. mcp251x_power_enable(priv->power, 0);
  953. clk_disable_unprepare(priv->clk);
  954. free_candev(net);
  955. return 0;
  956. }
  957. static int __maybe_unused mcp251x_can_suspend(struct device *dev)
  958. {
  959. struct spi_device *spi = to_spi_device(dev);
  960. struct mcp251x_priv *priv = spi_get_drvdata(spi);
  961. struct net_device *net = priv->net;
  962. priv->force_quit = 1;
  963. disable_irq(spi->irq);
  964. /* Note: at this point neither IST nor workqueues are running.
  965. * open/stop cannot be called anyway so locking is not needed
  966. */
  967. if (netif_running(net)) {
  968. netif_device_detach(net);
  969. mcp251x_hw_sleep(spi);
  970. mcp251x_power_enable(priv->transceiver, 0);
  971. priv->after_suspend = AFTER_SUSPEND_UP;
  972. } else {
  973. priv->after_suspend = AFTER_SUSPEND_DOWN;
  974. }
  975. mcp251x_power_enable(priv->power, 0);
  976. priv->after_suspend |= AFTER_SUSPEND_POWER;
  977. return 0;
  978. }
  979. static int __maybe_unused mcp251x_can_resume(struct device *dev)
  980. {
  981. struct spi_device *spi = to_spi_device(dev);
  982. struct mcp251x_priv *priv = spi_get_drvdata(spi);
  983. if (priv->after_suspend & AFTER_SUSPEND_POWER)
  984. mcp251x_power_enable(priv->power, 1);
  985. if (priv->after_suspend & AFTER_SUSPEND_UP) {
  986. mcp251x_power_enable(priv->transceiver, 1);
  987. queue_work(priv->wq, &priv->restart_work);
  988. } else {
  989. priv->after_suspend = 0;
  990. }
  991. priv->force_quit = 0;
  992. enable_irq(spi->irq);
  993. return 0;
  994. }
  995. static SIMPLE_DEV_PM_OPS(mcp251x_can_pm_ops, mcp251x_can_suspend,
  996. mcp251x_can_resume);
  997. static struct spi_driver mcp251x_can_driver = {
  998. .driver = {
  999. .name = DEVICE_NAME,
  1000. .of_match_table = mcp251x_of_match,
  1001. .pm = &mcp251x_can_pm_ops,
  1002. },
  1003. .id_table = mcp251x_id_table,
  1004. .probe = mcp251x_can_probe,
  1005. .remove = mcp251x_can_remove,
  1006. };
  1007. module_spi_driver(mcp251x_can_driver);
  1008. MODULE_AUTHOR("Chris Elston <celston@katalix.com>, "
  1009. "Christian Pellegrin <chripell@evolware.org>");
  1010. MODULE_DESCRIPTION("Microchip 251x/25625 CAN driver");
  1011. MODULE_LICENSE("GPL v2");