pch_can.c 32 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 1999 - 2010 Intel Corporation.
  4. * Copyright (C) 2010 LAPIS SEMICONDUCTOR CO., LTD.
  5. */
  6. #include <linux/interrupt.h>
  7. #include <linux/delay.h>
  8. #include <linux/io.h>
  9. #include <linux/module.h>
  10. #include <linux/sched.h>
  11. #include <linux/pci.h>
  12. #include <linux/kernel.h>
  13. #include <linux/types.h>
  14. #include <linux/errno.h>
  15. #include <linux/netdevice.h>
  16. #include <linux/skbuff.h>
  17. #include <linux/can.h>
  18. #include <linux/can/dev.h>
  19. #include <linux/can/error.h>
  20. #define PCH_CTRL_INIT BIT(0) /* The INIT bit of CANCONT register. */
  21. #define PCH_CTRL_IE BIT(1) /* The IE bit of CAN control register */
  22. #define PCH_CTRL_IE_SIE_EIE (BIT(3) | BIT(2) | BIT(1))
  23. #define PCH_CTRL_CCE BIT(6)
  24. #define PCH_CTRL_OPT BIT(7) /* The OPT bit of CANCONT register. */
  25. #define PCH_OPT_SILENT BIT(3) /* The Silent bit of CANOPT reg. */
  26. #define PCH_OPT_LBACK BIT(4) /* The LoopBack bit of CANOPT reg. */
  27. #define PCH_CMASK_RX_TX_SET 0x00f3
  28. #define PCH_CMASK_RX_TX_GET 0x0073
  29. #define PCH_CMASK_ALL 0xff
  30. #define PCH_CMASK_NEWDAT BIT(2)
  31. #define PCH_CMASK_CLRINTPND BIT(3)
  32. #define PCH_CMASK_CTRL BIT(4)
  33. #define PCH_CMASK_ARB BIT(5)
  34. #define PCH_CMASK_MASK BIT(6)
  35. #define PCH_CMASK_RDWR BIT(7)
  36. #define PCH_IF_MCONT_NEWDAT BIT(15)
  37. #define PCH_IF_MCONT_MSGLOST BIT(14)
  38. #define PCH_IF_MCONT_INTPND BIT(13)
  39. #define PCH_IF_MCONT_UMASK BIT(12)
  40. #define PCH_IF_MCONT_TXIE BIT(11)
  41. #define PCH_IF_MCONT_RXIE BIT(10)
  42. #define PCH_IF_MCONT_RMTEN BIT(9)
  43. #define PCH_IF_MCONT_TXRQXT BIT(8)
  44. #define PCH_IF_MCONT_EOB BIT(7)
  45. #define PCH_IF_MCONT_DLC (BIT(0) | BIT(1) | BIT(2) | BIT(3))
  46. #define PCH_MASK2_MDIR_MXTD (BIT(14) | BIT(15))
  47. #define PCH_ID2_DIR BIT(13)
  48. #define PCH_ID2_XTD BIT(14)
  49. #define PCH_ID_MSGVAL BIT(15)
  50. #define PCH_IF_CREQ_BUSY BIT(15)
  51. #define PCH_STATUS_INT 0x8000
  52. #define PCH_RP 0x00008000
  53. #define PCH_REC 0x00007f00
  54. #define PCH_TEC 0x000000ff
  55. #define PCH_TX_OK BIT(3)
  56. #define PCH_RX_OK BIT(4)
  57. #define PCH_EPASSIV BIT(5)
  58. #define PCH_EWARN BIT(6)
  59. #define PCH_BUS_OFF BIT(7)
  60. /* bit position of certain controller bits. */
  61. #define PCH_BIT_BRP_SHIFT 0
  62. #define PCH_BIT_SJW_SHIFT 6
  63. #define PCH_BIT_TSEG1_SHIFT 8
  64. #define PCH_BIT_TSEG2_SHIFT 12
  65. #define PCH_BIT_BRPE_BRPE_SHIFT 6
  66. #define PCH_MSK_BITT_BRP 0x3f
  67. #define PCH_MSK_BRPE_BRPE 0x3c0
  68. #define PCH_MSK_CTRL_IE_SIE_EIE 0x07
  69. #define PCH_COUNTER_LIMIT 10
  70. #define PCH_CAN_CLK 50000000 /* 50MHz */
  71. /*
  72. * Define the number of message object.
  73. * PCH CAN communications are done via Message RAM.
  74. * The Message RAM consists of 32 message objects.
  75. */
  76. #define PCH_RX_OBJ_NUM 26
  77. #define PCH_TX_OBJ_NUM 6
  78. #define PCH_RX_OBJ_START 1
  79. #define PCH_RX_OBJ_END PCH_RX_OBJ_NUM
  80. #define PCH_TX_OBJ_START (PCH_RX_OBJ_END + 1)
  81. #define PCH_TX_OBJ_END (PCH_RX_OBJ_NUM + PCH_TX_OBJ_NUM)
  82. #define PCH_FIFO_THRESH 16
  83. /* TxRqst2 show status of MsgObjNo.17~32 */
  84. #define PCH_TREQ2_TX_MASK (((1 << PCH_TX_OBJ_NUM) - 1) <<\
  85. (PCH_RX_OBJ_END - 16))
  86. enum pch_ifreg {
  87. PCH_RX_IFREG,
  88. PCH_TX_IFREG,
  89. };
  90. enum pch_can_err {
  91. PCH_STUF_ERR = 1,
  92. PCH_FORM_ERR,
  93. PCH_ACK_ERR,
  94. PCH_BIT1_ERR,
  95. PCH_BIT0_ERR,
  96. PCH_CRC_ERR,
  97. PCH_LEC_ALL,
  98. };
  99. enum pch_can_mode {
  100. PCH_CAN_ENABLE,
  101. PCH_CAN_DISABLE,
  102. PCH_CAN_ALL,
  103. PCH_CAN_NONE,
  104. PCH_CAN_STOP,
  105. PCH_CAN_RUN,
  106. };
  107. struct pch_can_if_regs {
  108. u32 creq;
  109. u32 cmask;
  110. u32 mask1;
  111. u32 mask2;
  112. u32 id1;
  113. u32 id2;
  114. u32 mcont;
  115. u32 data[4];
  116. u32 rsv[13];
  117. };
  118. struct pch_can_regs {
  119. u32 cont;
  120. u32 stat;
  121. u32 errc;
  122. u32 bitt;
  123. u32 intr;
  124. u32 opt;
  125. u32 brpe;
  126. u32 reserve;
  127. struct pch_can_if_regs ifregs[2]; /* [0]=if1 [1]=if2 */
  128. u32 reserve1[8];
  129. u32 treq1;
  130. u32 treq2;
  131. u32 reserve2[6];
  132. u32 data1;
  133. u32 data2;
  134. u32 reserve3[6];
  135. u32 canipend1;
  136. u32 canipend2;
  137. u32 reserve4[6];
  138. u32 canmval1;
  139. u32 canmval2;
  140. u32 reserve5[37];
  141. u32 srst;
  142. };
  143. struct pch_can_priv {
  144. struct can_priv can;
  145. struct pci_dev *dev;
  146. u32 tx_enable[PCH_TX_OBJ_END];
  147. u32 rx_enable[PCH_TX_OBJ_END];
  148. u32 rx_link[PCH_TX_OBJ_END];
  149. u32 int_enables;
  150. struct net_device *ndev;
  151. struct pch_can_regs __iomem *regs;
  152. struct napi_struct napi;
  153. int tx_obj; /* Point next Tx Obj index */
  154. int use_msi;
  155. };
  156. static const struct can_bittiming_const pch_can_bittiming_const = {
  157. .name = KBUILD_MODNAME,
  158. .tseg1_min = 2,
  159. .tseg1_max = 16,
  160. .tseg2_min = 1,
  161. .tseg2_max = 8,
  162. .sjw_max = 4,
  163. .brp_min = 1,
  164. .brp_max = 1024, /* 6bit + extended 4bit */
  165. .brp_inc = 1,
  166. };
  167. static const struct pci_device_id pch_pci_tbl[] = {
  168. {PCI_VENDOR_ID_INTEL, 0x8818, PCI_ANY_ID, PCI_ANY_ID,},
  169. {0,}
  170. };
  171. MODULE_DEVICE_TABLE(pci, pch_pci_tbl);
  172. static inline void pch_can_bit_set(void __iomem *addr, u32 mask)
  173. {
  174. iowrite32(ioread32(addr) | mask, addr);
  175. }
  176. static inline void pch_can_bit_clear(void __iomem *addr, u32 mask)
  177. {
  178. iowrite32(ioread32(addr) & ~mask, addr);
  179. }
  180. static void pch_can_set_run_mode(struct pch_can_priv *priv,
  181. enum pch_can_mode mode)
  182. {
  183. switch (mode) {
  184. case PCH_CAN_RUN:
  185. pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_INIT);
  186. break;
  187. case PCH_CAN_STOP:
  188. pch_can_bit_set(&priv->regs->cont, PCH_CTRL_INIT);
  189. break;
  190. default:
  191. netdev_err(priv->ndev, "%s -> Invalid Mode.\n", __func__);
  192. break;
  193. }
  194. }
  195. static void pch_can_set_optmode(struct pch_can_priv *priv)
  196. {
  197. u32 reg_val = ioread32(&priv->regs->opt);
  198. if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
  199. reg_val |= PCH_OPT_SILENT;
  200. if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
  201. reg_val |= PCH_OPT_LBACK;
  202. pch_can_bit_set(&priv->regs->cont, PCH_CTRL_OPT);
  203. iowrite32(reg_val, &priv->regs->opt);
  204. }
  205. static void pch_can_rw_msg_obj(void __iomem *creq_addr, u32 num)
  206. {
  207. int counter = PCH_COUNTER_LIMIT;
  208. u32 ifx_creq;
  209. iowrite32(num, creq_addr);
  210. while (counter) {
  211. ifx_creq = ioread32(creq_addr) & PCH_IF_CREQ_BUSY;
  212. if (!ifx_creq)
  213. break;
  214. counter--;
  215. udelay(1);
  216. }
  217. if (!counter)
  218. pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__);
  219. }
  220. static void pch_can_set_int_enables(struct pch_can_priv *priv,
  221. enum pch_can_mode interrupt_no)
  222. {
  223. switch (interrupt_no) {
  224. case PCH_CAN_DISABLE:
  225. pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE);
  226. break;
  227. case PCH_CAN_ALL:
  228. pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
  229. break;
  230. case PCH_CAN_NONE:
  231. pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
  232. break;
  233. default:
  234. netdev_err(priv->ndev, "Invalid interrupt number.\n");
  235. break;
  236. }
  237. }
  238. static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num,
  239. int set, enum pch_ifreg dir)
  240. {
  241. u32 ie;
  242. if (dir)
  243. ie = PCH_IF_MCONT_TXIE;
  244. else
  245. ie = PCH_IF_MCONT_RXIE;
  246. /* Reading the Msg buffer from Message RAM to IF1/2 registers. */
  247. iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
  248. pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
  249. /* Setting the IF1/2MASK1 register to access MsgVal and RxIE bits */
  250. iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL,
  251. &priv->regs->ifregs[dir].cmask);
  252. if (set) {
  253. /* Setting the MsgVal and RxIE/TxIE bits */
  254. pch_can_bit_set(&priv->regs->ifregs[dir].mcont, ie);
  255. pch_can_bit_set(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL);
  256. } else {
  257. /* Clearing the MsgVal and RxIE/TxIE bits */
  258. pch_can_bit_clear(&priv->regs->ifregs[dir].mcont, ie);
  259. pch_can_bit_clear(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL);
  260. }
  261. pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
  262. }
  263. static void pch_can_set_rx_all(struct pch_can_priv *priv, int set)
  264. {
  265. int i;
  266. /* Traversing to obtain the object configured as receivers. */
  267. for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++)
  268. pch_can_set_rxtx(priv, i, set, PCH_RX_IFREG);
  269. }
  270. static void pch_can_set_tx_all(struct pch_can_priv *priv, int set)
  271. {
  272. int i;
  273. /* Traversing to obtain the object configured as transmit object. */
  274. for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
  275. pch_can_set_rxtx(priv, i, set, PCH_TX_IFREG);
  276. }
  277. static u32 pch_can_int_pending(struct pch_can_priv *priv)
  278. {
  279. return ioread32(&priv->regs->intr) & 0xffff;
  280. }
  281. static void pch_can_clear_if_buffers(struct pch_can_priv *priv)
  282. {
  283. int i; /* Msg Obj ID (1~32) */
  284. for (i = PCH_RX_OBJ_START; i <= PCH_TX_OBJ_END; i++) {
  285. iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[0].cmask);
  286. iowrite32(0xffff, &priv->regs->ifregs[0].mask1);
  287. iowrite32(0xffff, &priv->regs->ifregs[0].mask2);
  288. iowrite32(0x0, &priv->regs->ifregs[0].id1);
  289. iowrite32(0x0, &priv->regs->ifregs[0].id2);
  290. iowrite32(0x0, &priv->regs->ifregs[0].mcont);
  291. iowrite32(0x0, &priv->regs->ifregs[0].data[0]);
  292. iowrite32(0x0, &priv->regs->ifregs[0].data[1]);
  293. iowrite32(0x0, &priv->regs->ifregs[0].data[2]);
  294. iowrite32(0x0, &priv->regs->ifregs[0].data[3]);
  295. iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
  296. PCH_CMASK_ARB | PCH_CMASK_CTRL,
  297. &priv->regs->ifregs[0].cmask);
  298. pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
  299. }
  300. }
  301. static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
  302. {
  303. int i;
  304. for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
  305. iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
  306. pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
  307. iowrite32(0x0, &priv->regs->ifregs[0].id1);
  308. iowrite32(0x0, &priv->regs->ifregs[0].id2);
  309. pch_can_bit_set(&priv->regs->ifregs[0].mcont,
  310. PCH_IF_MCONT_UMASK);
  311. /* In case FIFO mode, Last EoB of Rx Obj must be 1 */
  312. if (i == PCH_RX_OBJ_END)
  313. pch_can_bit_set(&priv->regs->ifregs[0].mcont,
  314. PCH_IF_MCONT_EOB);
  315. else
  316. pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
  317. PCH_IF_MCONT_EOB);
  318. iowrite32(0, &priv->regs->ifregs[0].mask1);
  319. pch_can_bit_clear(&priv->regs->ifregs[0].mask2,
  320. 0x1fff | PCH_MASK2_MDIR_MXTD);
  321. /* Setting CMASK for writing */
  322. iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | PCH_CMASK_ARB |
  323. PCH_CMASK_CTRL, &priv->regs->ifregs[0].cmask);
  324. pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
  325. }
  326. for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) {
  327. iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask);
  328. pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i);
  329. /* Resetting DIR bit for reception */
  330. iowrite32(0x0, &priv->regs->ifregs[1].id1);
  331. iowrite32(PCH_ID2_DIR, &priv->regs->ifregs[1].id2);
  332. /* Setting EOB bit for transmitter */
  333. iowrite32(PCH_IF_MCONT_EOB | PCH_IF_MCONT_UMASK,
  334. &priv->regs->ifregs[1].mcont);
  335. iowrite32(0, &priv->regs->ifregs[1].mask1);
  336. pch_can_bit_clear(&priv->regs->ifregs[1].mask2, 0x1fff);
  337. /* Setting CMASK for writing */
  338. iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | PCH_CMASK_ARB |
  339. PCH_CMASK_CTRL, &priv->regs->ifregs[1].cmask);
  340. pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i);
  341. }
  342. }
  343. static void pch_can_init(struct pch_can_priv *priv)
  344. {
  345. /* Stopping the Can device. */
  346. pch_can_set_run_mode(priv, PCH_CAN_STOP);
  347. /* Clearing all the message object buffers. */
  348. pch_can_clear_if_buffers(priv);
  349. /* Configuring the respective message object as either rx/tx object. */
  350. pch_can_config_rx_tx_buffers(priv);
  351. /* Enabling the interrupts. */
  352. pch_can_set_int_enables(priv, PCH_CAN_ALL);
  353. }
  354. static void pch_can_release(struct pch_can_priv *priv)
  355. {
  356. /* Stooping the CAN device. */
  357. pch_can_set_run_mode(priv, PCH_CAN_STOP);
  358. /* Disabling the interrupts. */
  359. pch_can_set_int_enables(priv, PCH_CAN_NONE);
  360. /* Disabling all the receive object. */
  361. pch_can_set_rx_all(priv, 0);
  362. /* Disabling all the transmit object. */
  363. pch_can_set_tx_all(priv, 0);
  364. }
  365. /* This function clears interrupt(s) from the CAN device. */
  366. static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask)
  367. {
  368. /* Clear interrupt for transmit object */
  369. if ((mask >= PCH_RX_OBJ_START) && (mask <= PCH_RX_OBJ_END)) {
  370. /* Setting CMASK for clearing the reception interrupts. */
  371. iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
  372. &priv->regs->ifregs[0].cmask);
  373. /* Clearing the Dir bit. */
  374. pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR);
  375. /* Clearing NewDat & IntPnd */
  376. pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
  377. PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND);
  378. pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, mask);
  379. } else if ((mask >= PCH_TX_OBJ_START) && (mask <= PCH_TX_OBJ_END)) {
  380. /*
  381. * Setting CMASK for clearing interrupts for frame transmission.
  382. */
  383. iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
  384. &priv->regs->ifregs[1].cmask);
  385. /* Resetting the ID registers. */
  386. pch_can_bit_set(&priv->regs->ifregs[1].id2,
  387. PCH_ID2_DIR | (0x7ff << 2));
  388. iowrite32(0x0, &priv->regs->ifregs[1].id1);
  389. /* Claring NewDat, TxRqst & IntPnd */
  390. pch_can_bit_clear(&priv->regs->ifregs[1].mcont,
  391. PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND |
  392. PCH_IF_MCONT_TXRQXT);
  393. pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, mask);
  394. }
  395. }
  396. static void pch_can_reset(struct pch_can_priv *priv)
  397. {
  398. /* write to sw reset register */
  399. iowrite32(1, &priv->regs->srst);
  400. iowrite32(0, &priv->regs->srst);
  401. }
  402. static void pch_can_error(struct net_device *ndev, u32 status)
  403. {
  404. struct sk_buff *skb;
  405. struct pch_can_priv *priv = netdev_priv(ndev);
  406. struct can_frame *cf;
  407. u32 errc, lec;
  408. struct net_device_stats *stats = &(priv->ndev->stats);
  409. enum can_state state = priv->can.state;
  410. skb = alloc_can_err_skb(ndev, &cf);
  411. if (!skb)
  412. return;
  413. if (status & PCH_BUS_OFF) {
  414. pch_can_set_tx_all(priv, 0);
  415. pch_can_set_rx_all(priv, 0);
  416. state = CAN_STATE_BUS_OFF;
  417. cf->can_id |= CAN_ERR_BUSOFF;
  418. priv->can.can_stats.bus_off++;
  419. can_bus_off(ndev);
  420. }
  421. errc = ioread32(&priv->regs->errc);
  422. /* Warning interrupt. */
  423. if (status & PCH_EWARN) {
  424. state = CAN_STATE_ERROR_WARNING;
  425. priv->can.can_stats.error_warning++;
  426. cf->can_id |= CAN_ERR_CRTL;
  427. if (((errc & PCH_REC) >> 8) > 96)
  428. cf->data[1] |= CAN_ERR_CRTL_RX_WARNING;
  429. if ((errc & PCH_TEC) > 96)
  430. cf->data[1] |= CAN_ERR_CRTL_TX_WARNING;
  431. netdev_dbg(ndev,
  432. "%s -> Error Counter is more than 96.\n", __func__);
  433. }
  434. /* Error passive interrupt. */
  435. if (status & PCH_EPASSIV) {
  436. priv->can.can_stats.error_passive++;
  437. state = CAN_STATE_ERROR_PASSIVE;
  438. cf->can_id |= CAN_ERR_CRTL;
  439. if (errc & PCH_RP)
  440. cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
  441. if ((errc & PCH_TEC) > 127)
  442. cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
  443. netdev_dbg(ndev,
  444. "%s -> CAN controller is ERROR PASSIVE .\n", __func__);
  445. }
  446. lec = status & PCH_LEC_ALL;
  447. switch (lec) {
  448. case PCH_STUF_ERR:
  449. cf->data[2] |= CAN_ERR_PROT_STUFF;
  450. priv->can.can_stats.bus_error++;
  451. stats->rx_errors++;
  452. break;
  453. case PCH_FORM_ERR:
  454. cf->data[2] |= CAN_ERR_PROT_FORM;
  455. priv->can.can_stats.bus_error++;
  456. stats->rx_errors++;
  457. break;
  458. case PCH_ACK_ERR:
  459. cf->can_id |= CAN_ERR_ACK;
  460. priv->can.can_stats.bus_error++;
  461. stats->rx_errors++;
  462. break;
  463. case PCH_BIT1_ERR:
  464. case PCH_BIT0_ERR:
  465. cf->data[2] |= CAN_ERR_PROT_BIT;
  466. priv->can.can_stats.bus_error++;
  467. stats->rx_errors++;
  468. break;
  469. case PCH_CRC_ERR:
  470. cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
  471. priv->can.can_stats.bus_error++;
  472. stats->rx_errors++;
  473. break;
  474. case PCH_LEC_ALL: /* Written by CPU. No error status */
  475. break;
  476. }
  477. cf->data[6] = errc & PCH_TEC;
  478. cf->data[7] = (errc & PCH_REC) >> 8;
  479. priv->can.state = state;
  480. netif_receive_skb(skb);
  481. stats->rx_packets++;
  482. stats->rx_bytes += cf->can_dlc;
  483. }
  484. static irqreturn_t pch_can_interrupt(int irq, void *dev_id)
  485. {
  486. struct net_device *ndev = (struct net_device *)dev_id;
  487. struct pch_can_priv *priv = netdev_priv(ndev);
  488. if (!pch_can_int_pending(priv))
  489. return IRQ_NONE;
  490. pch_can_set_int_enables(priv, PCH_CAN_NONE);
  491. napi_schedule(&priv->napi);
  492. return IRQ_HANDLED;
  493. }
  494. static void pch_fifo_thresh(struct pch_can_priv *priv, int obj_id)
  495. {
  496. if (obj_id < PCH_FIFO_THRESH) {
  497. iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL |
  498. PCH_CMASK_ARB, &priv->regs->ifregs[0].cmask);
  499. /* Clearing the Dir bit. */
  500. pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR);
  501. /* Clearing NewDat & IntPnd */
  502. pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
  503. PCH_IF_MCONT_INTPND);
  504. pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id);
  505. } else if (obj_id > PCH_FIFO_THRESH) {
  506. pch_can_int_clr(priv, obj_id);
  507. } else if (obj_id == PCH_FIFO_THRESH) {
  508. int cnt;
  509. for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++)
  510. pch_can_int_clr(priv, cnt + 1);
  511. }
  512. }
  513. static void pch_can_rx_msg_lost(struct net_device *ndev, int obj_id)
  514. {
  515. struct pch_can_priv *priv = netdev_priv(ndev);
  516. struct net_device_stats *stats = &(priv->ndev->stats);
  517. struct sk_buff *skb;
  518. struct can_frame *cf;
  519. netdev_dbg(priv->ndev, "Msg Obj is overwritten.\n");
  520. pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
  521. PCH_IF_MCONT_MSGLOST);
  522. iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
  523. &priv->regs->ifregs[0].cmask);
  524. pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id);
  525. skb = alloc_can_err_skb(ndev, &cf);
  526. if (!skb)
  527. return;
  528. cf->can_id |= CAN_ERR_CRTL;
  529. cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
  530. stats->rx_over_errors++;
  531. stats->rx_errors++;
  532. netif_receive_skb(skb);
  533. }
  534. static int pch_can_rx_normal(struct net_device *ndev, u32 obj_num, int quota)
  535. {
  536. u32 reg;
  537. canid_t id;
  538. int rcv_pkts = 0;
  539. struct sk_buff *skb;
  540. struct can_frame *cf;
  541. struct pch_can_priv *priv = netdev_priv(ndev);
  542. struct net_device_stats *stats = &(priv->ndev->stats);
  543. int i;
  544. u32 id2;
  545. u16 data_reg;
  546. do {
  547. /* Reading the message object from the Message RAM */
  548. iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
  549. pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_num);
  550. /* Reading the MCONT register. */
  551. reg = ioread32(&priv->regs->ifregs[0].mcont);
  552. if (reg & PCH_IF_MCONT_EOB)
  553. break;
  554. /* If MsgLost bit set. */
  555. if (reg & PCH_IF_MCONT_MSGLOST) {
  556. pch_can_rx_msg_lost(ndev, obj_num);
  557. rcv_pkts++;
  558. quota--;
  559. obj_num++;
  560. continue;
  561. } else if (!(reg & PCH_IF_MCONT_NEWDAT)) {
  562. obj_num++;
  563. continue;
  564. }
  565. skb = alloc_can_skb(priv->ndev, &cf);
  566. if (!skb) {
  567. netdev_err(ndev, "alloc_can_skb Failed\n");
  568. return rcv_pkts;
  569. }
  570. /* Get Received data */
  571. id2 = ioread32(&priv->regs->ifregs[0].id2);
  572. if (id2 & PCH_ID2_XTD) {
  573. id = (ioread32(&priv->regs->ifregs[0].id1) & 0xffff);
  574. id |= (((id2) & 0x1fff) << 16);
  575. cf->can_id = id | CAN_EFF_FLAG;
  576. } else {
  577. id = (id2 >> 2) & CAN_SFF_MASK;
  578. cf->can_id = id;
  579. }
  580. if (id2 & PCH_ID2_DIR)
  581. cf->can_id |= CAN_RTR_FLAG;
  582. cf->can_dlc = get_can_dlc((ioread32(&priv->regs->
  583. ifregs[0].mcont)) & 0xF);
  584. for (i = 0; i < cf->can_dlc; i += 2) {
  585. data_reg = ioread16(&priv->regs->ifregs[0].data[i / 2]);
  586. cf->data[i] = data_reg;
  587. cf->data[i + 1] = data_reg >> 8;
  588. }
  589. netif_receive_skb(skb);
  590. rcv_pkts++;
  591. stats->rx_packets++;
  592. quota--;
  593. stats->rx_bytes += cf->can_dlc;
  594. pch_fifo_thresh(priv, obj_num);
  595. obj_num++;
  596. } while (quota > 0);
  597. return rcv_pkts;
  598. }
  599. static void pch_can_tx_complete(struct net_device *ndev, u32 int_stat)
  600. {
  601. struct pch_can_priv *priv = netdev_priv(ndev);
  602. struct net_device_stats *stats = &(priv->ndev->stats);
  603. u32 dlc;
  604. can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_END - 1);
  605. iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND,
  606. &priv->regs->ifregs[1].cmask);
  607. pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, int_stat);
  608. dlc = get_can_dlc(ioread32(&priv->regs->ifregs[1].mcont) &
  609. PCH_IF_MCONT_DLC);
  610. stats->tx_bytes += dlc;
  611. stats->tx_packets++;
  612. if (int_stat == PCH_TX_OBJ_END)
  613. netif_wake_queue(ndev);
  614. }
  615. static int pch_can_poll(struct napi_struct *napi, int quota)
  616. {
  617. struct net_device *ndev = napi->dev;
  618. struct pch_can_priv *priv = netdev_priv(ndev);
  619. u32 int_stat;
  620. u32 reg_stat;
  621. int quota_save = quota;
  622. int_stat = pch_can_int_pending(priv);
  623. if (!int_stat)
  624. goto end;
  625. if (int_stat == PCH_STATUS_INT) {
  626. reg_stat = ioread32(&priv->regs->stat);
  627. if ((reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) &&
  628. ((reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL)) {
  629. pch_can_error(ndev, reg_stat);
  630. quota--;
  631. }
  632. if (reg_stat & (PCH_TX_OK | PCH_RX_OK))
  633. pch_can_bit_clear(&priv->regs->stat,
  634. reg_stat & (PCH_TX_OK | PCH_RX_OK));
  635. int_stat = pch_can_int_pending(priv);
  636. }
  637. if (quota == 0)
  638. goto end;
  639. if ((int_stat >= PCH_RX_OBJ_START) && (int_stat <= PCH_RX_OBJ_END)) {
  640. quota -= pch_can_rx_normal(ndev, int_stat, quota);
  641. } else if ((int_stat >= PCH_TX_OBJ_START) &&
  642. (int_stat <= PCH_TX_OBJ_END)) {
  643. /* Handle transmission interrupt */
  644. pch_can_tx_complete(ndev, int_stat);
  645. }
  646. end:
  647. napi_complete(napi);
  648. pch_can_set_int_enables(priv, PCH_CAN_ALL);
  649. return quota_save - quota;
  650. }
  651. static int pch_set_bittiming(struct net_device *ndev)
  652. {
  653. struct pch_can_priv *priv = netdev_priv(ndev);
  654. const struct can_bittiming *bt = &priv->can.bittiming;
  655. u32 canbit;
  656. u32 bepe;
  657. /* Setting the CCE bit for accessing the Can Timing register. */
  658. pch_can_bit_set(&priv->regs->cont, PCH_CTRL_CCE);
  659. canbit = (bt->brp - 1) & PCH_MSK_BITT_BRP;
  660. canbit |= (bt->sjw - 1) << PCH_BIT_SJW_SHIFT;
  661. canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << PCH_BIT_TSEG1_SHIFT;
  662. canbit |= (bt->phase_seg2 - 1) << PCH_BIT_TSEG2_SHIFT;
  663. bepe = ((bt->brp - 1) & PCH_MSK_BRPE_BRPE) >> PCH_BIT_BRPE_BRPE_SHIFT;
  664. iowrite32(canbit, &priv->regs->bitt);
  665. iowrite32(bepe, &priv->regs->brpe);
  666. pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_CCE);
  667. return 0;
  668. }
  669. static void pch_can_start(struct net_device *ndev)
  670. {
  671. struct pch_can_priv *priv = netdev_priv(ndev);
  672. if (priv->can.state != CAN_STATE_STOPPED)
  673. pch_can_reset(priv);
  674. pch_set_bittiming(ndev);
  675. pch_can_set_optmode(priv);
  676. pch_can_set_tx_all(priv, 1);
  677. pch_can_set_rx_all(priv, 1);
  678. /* Setting the CAN to run mode. */
  679. pch_can_set_run_mode(priv, PCH_CAN_RUN);
  680. priv->can.state = CAN_STATE_ERROR_ACTIVE;
  681. return;
  682. }
  683. static int pch_can_do_set_mode(struct net_device *ndev, enum can_mode mode)
  684. {
  685. int ret = 0;
  686. switch (mode) {
  687. case CAN_MODE_START:
  688. pch_can_start(ndev);
  689. netif_wake_queue(ndev);
  690. break;
  691. default:
  692. ret = -EOPNOTSUPP;
  693. break;
  694. }
  695. return ret;
  696. }
  697. static int pch_can_open(struct net_device *ndev)
  698. {
  699. struct pch_can_priv *priv = netdev_priv(ndev);
  700. int retval;
  701. /* Regstering the interrupt. */
  702. retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED,
  703. ndev->name, ndev);
  704. if (retval) {
  705. netdev_err(ndev, "request_irq failed.\n");
  706. goto req_irq_err;
  707. }
  708. /* Open common can device */
  709. retval = open_candev(ndev);
  710. if (retval) {
  711. netdev_err(ndev, "open_candev() failed %d\n", retval);
  712. goto err_open_candev;
  713. }
  714. pch_can_init(priv);
  715. pch_can_start(ndev);
  716. napi_enable(&priv->napi);
  717. netif_start_queue(ndev);
  718. return 0;
  719. err_open_candev:
  720. free_irq(priv->dev->irq, ndev);
  721. req_irq_err:
  722. pch_can_release(priv);
  723. return retval;
  724. }
  725. static int pch_close(struct net_device *ndev)
  726. {
  727. struct pch_can_priv *priv = netdev_priv(ndev);
  728. netif_stop_queue(ndev);
  729. napi_disable(&priv->napi);
  730. pch_can_release(priv);
  731. free_irq(priv->dev->irq, ndev);
  732. close_candev(ndev);
  733. priv->can.state = CAN_STATE_STOPPED;
  734. return 0;
  735. }
  736. static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
  737. {
  738. struct pch_can_priv *priv = netdev_priv(ndev);
  739. struct can_frame *cf = (struct can_frame *)skb->data;
  740. int tx_obj_no;
  741. int i;
  742. u32 id2;
  743. if (can_dropped_invalid_skb(ndev, skb))
  744. return NETDEV_TX_OK;
  745. tx_obj_no = priv->tx_obj;
  746. if (priv->tx_obj == PCH_TX_OBJ_END) {
  747. if (ioread32(&priv->regs->treq2) & PCH_TREQ2_TX_MASK)
  748. netif_stop_queue(ndev);
  749. priv->tx_obj = PCH_TX_OBJ_START;
  750. } else {
  751. priv->tx_obj++;
  752. }
  753. /* Setting the CMASK register. */
  754. pch_can_bit_set(&priv->regs->ifregs[1].cmask, PCH_CMASK_ALL);
  755. /* If ID extended is set. */
  756. if (cf->can_id & CAN_EFF_FLAG) {
  757. iowrite32(cf->can_id & 0xffff, &priv->regs->ifregs[1].id1);
  758. id2 = ((cf->can_id >> 16) & 0x1fff) | PCH_ID2_XTD;
  759. } else {
  760. iowrite32(0, &priv->regs->ifregs[1].id1);
  761. id2 = (cf->can_id & CAN_SFF_MASK) << 2;
  762. }
  763. id2 |= PCH_ID_MSGVAL;
  764. /* If remote frame has to be transmitted.. */
  765. if (!(cf->can_id & CAN_RTR_FLAG))
  766. id2 |= PCH_ID2_DIR;
  767. iowrite32(id2, &priv->regs->ifregs[1].id2);
  768. /* Copy data to register */
  769. for (i = 0; i < cf->can_dlc; i += 2) {
  770. iowrite16(cf->data[i] | (cf->data[i + 1] << 8),
  771. &priv->regs->ifregs[1].data[i / 2]);
  772. }
  773. can_put_echo_skb(skb, ndev, tx_obj_no - PCH_RX_OBJ_END - 1);
  774. /* Set the size of the data. Update if2_mcont */
  775. iowrite32(cf->can_dlc | PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_TXRQXT |
  776. PCH_IF_MCONT_TXIE, &priv->regs->ifregs[1].mcont);
  777. pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, tx_obj_no);
  778. return NETDEV_TX_OK;
  779. }
  780. static const struct net_device_ops pch_can_netdev_ops = {
  781. .ndo_open = pch_can_open,
  782. .ndo_stop = pch_close,
  783. .ndo_start_xmit = pch_xmit,
  784. .ndo_change_mtu = can_change_mtu,
  785. };
  786. static void pch_can_remove(struct pci_dev *pdev)
  787. {
  788. struct net_device *ndev = pci_get_drvdata(pdev);
  789. struct pch_can_priv *priv = netdev_priv(ndev);
  790. unregister_candev(priv->ndev);
  791. if (priv->use_msi)
  792. pci_disable_msi(priv->dev);
  793. pci_release_regions(pdev);
  794. pci_disable_device(pdev);
  795. pch_can_reset(priv);
  796. pci_iounmap(pdev, priv->regs);
  797. free_candev(priv->ndev);
  798. }
  799. #ifdef CONFIG_PM
  800. static void pch_can_set_int_custom(struct pch_can_priv *priv)
  801. {
  802. /* Clearing the IE, SIE and EIE bits of Can control register. */
  803. pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
  804. /* Appropriately setting them. */
  805. pch_can_bit_set(&priv->regs->cont,
  806. ((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1));
  807. }
  808. /* This function retrieves interrupt enabled for the CAN device. */
  809. static u32 pch_can_get_int_enables(struct pch_can_priv *priv)
  810. {
  811. /* Obtaining the status of IE, SIE and EIE interrupt bits. */
  812. return (ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1;
  813. }
  814. static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num,
  815. enum pch_ifreg dir)
  816. {
  817. u32 ie, enable;
  818. if (dir)
  819. ie = PCH_IF_MCONT_RXIE;
  820. else
  821. ie = PCH_IF_MCONT_TXIE;
  822. iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
  823. pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
  824. if (((ioread32(&priv->regs->ifregs[dir].id2)) & PCH_ID_MSGVAL) &&
  825. ((ioread32(&priv->regs->ifregs[dir].mcont)) & ie))
  826. enable = 1;
  827. else
  828. enable = 0;
  829. return enable;
  830. }
  831. static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv,
  832. u32 buffer_num, int set)
  833. {
  834. iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
  835. pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
  836. iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
  837. &priv->regs->ifregs[0].cmask);
  838. if (set)
  839. pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
  840. PCH_IF_MCONT_EOB);
  841. else
  842. pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB);
  843. pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
  844. }
  845. static u32 pch_can_get_rx_buffer_link(struct pch_can_priv *priv, u32 buffer_num)
  846. {
  847. u32 link;
  848. iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
  849. pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
  850. if (ioread32(&priv->regs->ifregs[0].mcont) & PCH_IF_MCONT_EOB)
  851. link = 0;
  852. else
  853. link = 1;
  854. return link;
  855. }
  856. static int pch_can_get_buffer_status(struct pch_can_priv *priv)
  857. {
  858. return (ioread32(&priv->regs->treq1) & 0xffff) |
  859. (ioread32(&priv->regs->treq2) << 16);
  860. }
  861. static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state)
  862. {
  863. int i;
  864. int retval;
  865. u32 buf_stat; /* Variable for reading the transmit buffer status. */
  866. int counter = PCH_COUNTER_LIMIT;
  867. struct net_device *dev = pci_get_drvdata(pdev);
  868. struct pch_can_priv *priv = netdev_priv(dev);
  869. /* Stop the CAN controller */
  870. pch_can_set_run_mode(priv, PCH_CAN_STOP);
  871. /* Indicate that we are aboutto/in suspend */
  872. priv->can.state = CAN_STATE_STOPPED;
  873. /* Waiting for all transmission to complete. */
  874. while (counter) {
  875. buf_stat = pch_can_get_buffer_status(priv);
  876. if (!buf_stat)
  877. break;
  878. counter--;
  879. udelay(1);
  880. }
  881. if (!counter)
  882. dev_err(&pdev->dev, "%s -> Transmission time out.\n", __func__);
  883. /* Save interrupt configuration and then disable them */
  884. priv->int_enables = pch_can_get_int_enables(priv);
  885. pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
  886. /* Save Tx buffer enable state */
  887. for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
  888. priv->tx_enable[i - 1] = pch_can_get_rxtx_ir(priv, i,
  889. PCH_TX_IFREG);
  890. /* Disable all Transmit buffers */
  891. pch_can_set_tx_all(priv, 0);
  892. /* Save Rx buffer enable state */
  893. for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
  894. priv->rx_enable[i - 1] = pch_can_get_rxtx_ir(priv, i,
  895. PCH_RX_IFREG);
  896. priv->rx_link[i - 1] = pch_can_get_rx_buffer_link(priv, i);
  897. }
  898. /* Disable all Receive buffers */
  899. pch_can_set_rx_all(priv, 0);
  900. retval = pci_save_state(pdev);
  901. if (retval) {
  902. dev_err(&pdev->dev, "pci_save_state failed.\n");
  903. } else {
  904. pci_enable_wake(pdev, PCI_D3hot, 0);
  905. pci_disable_device(pdev);
  906. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  907. }
  908. return retval;
  909. }
  910. static int pch_can_resume(struct pci_dev *pdev)
  911. {
  912. int i;
  913. int retval;
  914. struct net_device *dev = pci_get_drvdata(pdev);
  915. struct pch_can_priv *priv = netdev_priv(dev);
  916. pci_set_power_state(pdev, PCI_D0);
  917. pci_restore_state(pdev);
  918. retval = pci_enable_device(pdev);
  919. if (retval) {
  920. dev_err(&pdev->dev, "pci_enable_device failed.\n");
  921. return retval;
  922. }
  923. pci_enable_wake(pdev, PCI_D3hot, 0);
  924. priv->can.state = CAN_STATE_ERROR_ACTIVE;
  925. /* Disabling all interrupts. */
  926. pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
  927. /* Setting the CAN device in Stop Mode. */
  928. pch_can_set_run_mode(priv, PCH_CAN_STOP);
  929. /* Configuring the transmit and receive buffers. */
  930. pch_can_config_rx_tx_buffers(priv);
  931. /* Restore the CAN state */
  932. pch_set_bittiming(dev);
  933. /* Listen/Active */
  934. pch_can_set_optmode(priv);
  935. /* Enabling the transmit buffer. */
  936. for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
  937. pch_can_set_rxtx(priv, i, priv->tx_enable[i - 1], PCH_TX_IFREG);
  938. /* Configuring the receive buffer and enabling them. */
  939. for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
  940. /* Restore buffer link */
  941. pch_can_set_rx_buffer_link(priv, i, priv->rx_link[i - 1]);
  942. /* Restore buffer enables */
  943. pch_can_set_rxtx(priv, i, priv->rx_enable[i - 1], PCH_RX_IFREG);
  944. }
  945. /* Enable CAN Interrupts */
  946. pch_can_set_int_custom(priv);
  947. /* Restore Run Mode */
  948. pch_can_set_run_mode(priv, PCH_CAN_RUN);
  949. return retval;
  950. }
  951. #else
  952. #define pch_can_suspend NULL
  953. #define pch_can_resume NULL
  954. #endif
  955. static int pch_can_get_berr_counter(const struct net_device *dev,
  956. struct can_berr_counter *bec)
  957. {
  958. struct pch_can_priv *priv = netdev_priv(dev);
  959. u32 errc = ioread32(&priv->regs->errc);
  960. bec->txerr = errc & PCH_TEC;
  961. bec->rxerr = (errc & PCH_REC) >> 8;
  962. return 0;
  963. }
  964. static int pch_can_probe(struct pci_dev *pdev,
  965. const struct pci_device_id *id)
  966. {
  967. struct net_device *ndev;
  968. struct pch_can_priv *priv;
  969. int rc;
  970. void __iomem *addr;
  971. rc = pci_enable_device(pdev);
  972. if (rc) {
  973. dev_err(&pdev->dev, "Failed pci_enable_device %d\n", rc);
  974. goto probe_exit_endev;
  975. }
  976. rc = pci_request_regions(pdev, KBUILD_MODNAME);
  977. if (rc) {
  978. dev_err(&pdev->dev, "Failed pci_request_regions %d\n", rc);
  979. goto probe_exit_pcireq;
  980. }
  981. addr = pci_iomap(pdev, 1, 0);
  982. if (!addr) {
  983. rc = -EIO;
  984. dev_err(&pdev->dev, "Failed pci_iomap\n");
  985. goto probe_exit_ipmap;
  986. }
  987. ndev = alloc_candev(sizeof(struct pch_can_priv), PCH_TX_OBJ_END);
  988. if (!ndev) {
  989. rc = -ENOMEM;
  990. dev_err(&pdev->dev, "Failed alloc_candev\n");
  991. goto probe_exit_alloc_candev;
  992. }
  993. priv = netdev_priv(ndev);
  994. priv->ndev = ndev;
  995. priv->regs = addr;
  996. priv->dev = pdev;
  997. priv->can.bittiming_const = &pch_can_bittiming_const;
  998. priv->can.do_set_mode = pch_can_do_set_mode;
  999. priv->can.do_get_berr_counter = pch_can_get_berr_counter;
  1000. priv->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY |
  1001. CAN_CTRLMODE_LOOPBACK;
  1002. priv->tx_obj = PCH_TX_OBJ_START; /* Point head of Tx Obj */
  1003. ndev->irq = pdev->irq;
  1004. ndev->flags |= IFF_ECHO;
  1005. pci_set_drvdata(pdev, ndev);
  1006. SET_NETDEV_DEV(ndev, &pdev->dev);
  1007. ndev->netdev_ops = &pch_can_netdev_ops;
  1008. priv->can.clock.freq = PCH_CAN_CLK; /* Hz */
  1009. netif_napi_add(ndev, &priv->napi, pch_can_poll, PCH_RX_OBJ_END);
  1010. rc = pci_enable_msi(priv->dev);
  1011. if (rc) {
  1012. netdev_err(ndev, "PCH CAN opened without MSI\n");
  1013. priv->use_msi = 0;
  1014. } else {
  1015. netdev_err(ndev, "PCH CAN opened with MSI\n");
  1016. pci_set_master(pdev);
  1017. priv->use_msi = 1;
  1018. }
  1019. rc = register_candev(ndev);
  1020. if (rc) {
  1021. dev_err(&pdev->dev, "Failed register_candev %d\n", rc);
  1022. goto probe_exit_reg_candev;
  1023. }
  1024. return 0;
  1025. probe_exit_reg_candev:
  1026. if (priv->use_msi)
  1027. pci_disable_msi(priv->dev);
  1028. free_candev(ndev);
  1029. probe_exit_alloc_candev:
  1030. pci_iounmap(pdev, addr);
  1031. probe_exit_ipmap:
  1032. pci_release_regions(pdev);
  1033. probe_exit_pcireq:
  1034. pci_disable_device(pdev);
  1035. probe_exit_endev:
  1036. return rc;
  1037. }
  1038. static struct pci_driver pch_can_pci_driver = {
  1039. .name = "pch_can",
  1040. .id_table = pch_pci_tbl,
  1041. .probe = pch_can_probe,
  1042. .remove = pch_can_remove,
  1043. .suspend = pch_can_suspend,
  1044. .resume = pch_can_resume,
  1045. };
  1046. module_pci_driver(pch_can_pci_driver);
  1047. MODULE_DESCRIPTION("Intel EG20T PCH CAN(Controller Area Network) Driver");
  1048. MODULE_LICENSE("GPL v2");
  1049. MODULE_VERSION("0.94");