mx2_emmaprp.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Support eMMa-PrP through mem2mem framework.
  4. *
  5. * eMMa-PrP is a piece of HW that allows fetching buffers
  6. * from one memory location and do several operations on
  7. * them such as scaling or format conversion giving, as a result
  8. * a new processed buffer in another memory location.
  9. *
  10. * Based on mem2mem_testdev.c by Pawel Osciak.
  11. *
  12. * Copyright (c) 2011 Vista Silicon S.L.
  13. * Javier Martin <javier.martin@vista-silicon.com>
  14. */
  15. #include <linux/module.h>
  16. #include <linux/clk.h>
  17. #include <linux/slab.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/io.h>
  20. #include <linux/platform_device.h>
  21. #include <media/v4l2-mem2mem.h>
  22. #include <media/v4l2-device.h>
  23. #include <media/v4l2-ioctl.h>
  24. #include <media/videobuf2-dma-contig.h>
  25. #include <linux/sizes.h>
  26. #define EMMAPRP_MODULE_NAME "mem2mem-emmaprp"
  27. MODULE_DESCRIPTION("Mem-to-mem device which supports eMMa-PrP present in mx2 SoCs");
  28. MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com");
  29. MODULE_LICENSE("GPL");
  30. MODULE_VERSION("0.0.1");
  31. static bool debug;
  32. module_param(debug, bool, 0644);
  33. #define MIN_W 32
  34. #define MIN_H 32
  35. #define MAX_W 2040
  36. #define MAX_H 2046
  37. #define S_ALIGN 1 /* multiple of 2 */
  38. #define W_ALIGN_YUV420 3 /* multiple of 8 */
  39. #define W_ALIGN_OTHERS 2 /* multiple of 4 */
  40. #define H_ALIGN 1 /* multiple of 2 */
  41. /* Flags that indicate a format can be used for capture/output */
  42. #define MEM2MEM_CAPTURE (1 << 0)
  43. #define MEM2MEM_OUTPUT (1 << 1)
  44. #define MEM2MEM_NAME "m2m-emmaprp"
  45. /* In bytes, per queue */
  46. #define MEM2MEM_VID_MEM_LIMIT SZ_16M
  47. #define dprintk(dev, fmt, arg...) \
  48. v4l2_dbg(1, debug, &dev->v4l2_dev, "%s: " fmt, __func__, ## arg)
  49. /* EMMA PrP */
  50. #define PRP_CNTL 0x00
  51. #define PRP_INTR_CNTL 0x04
  52. #define PRP_INTRSTATUS 0x08
  53. #define PRP_SOURCE_Y_PTR 0x0c
  54. #define PRP_SOURCE_CB_PTR 0x10
  55. #define PRP_SOURCE_CR_PTR 0x14
  56. #define PRP_DEST_RGB1_PTR 0x18
  57. #define PRP_DEST_RGB2_PTR 0x1c
  58. #define PRP_DEST_Y_PTR 0x20
  59. #define PRP_DEST_CB_PTR 0x24
  60. #define PRP_DEST_CR_PTR 0x28
  61. #define PRP_SRC_FRAME_SIZE 0x2c
  62. #define PRP_DEST_CH1_LINE_STRIDE 0x30
  63. #define PRP_SRC_PIXEL_FORMAT_CNTL 0x34
  64. #define PRP_CH1_PIXEL_FORMAT_CNTL 0x38
  65. #define PRP_CH1_OUT_IMAGE_SIZE 0x3c
  66. #define PRP_CH2_OUT_IMAGE_SIZE 0x40
  67. #define PRP_SRC_LINE_STRIDE 0x44
  68. #define PRP_CSC_COEF_012 0x48
  69. #define PRP_CSC_COEF_345 0x4c
  70. #define PRP_CSC_COEF_678 0x50
  71. #define PRP_CH1_RZ_HORI_COEF1 0x54
  72. #define PRP_CH1_RZ_HORI_COEF2 0x58
  73. #define PRP_CH1_RZ_HORI_VALID 0x5c
  74. #define PRP_CH1_RZ_VERT_COEF1 0x60
  75. #define PRP_CH1_RZ_VERT_COEF2 0x64
  76. #define PRP_CH1_RZ_VERT_VALID 0x68
  77. #define PRP_CH2_RZ_HORI_COEF1 0x6c
  78. #define PRP_CH2_RZ_HORI_COEF2 0x70
  79. #define PRP_CH2_RZ_HORI_VALID 0x74
  80. #define PRP_CH2_RZ_VERT_COEF1 0x78
  81. #define PRP_CH2_RZ_VERT_COEF2 0x7c
  82. #define PRP_CH2_RZ_VERT_VALID 0x80
  83. #define PRP_CNTL_CH1EN (1 << 0)
  84. #define PRP_CNTL_CH2EN (1 << 1)
  85. #define PRP_CNTL_CSIEN (1 << 2)
  86. #define PRP_CNTL_DATA_IN_YUV420 (0 << 3)
  87. #define PRP_CNTL_DATA_IN_YUV422 (1 << 3)
  88. #define PRP_CNTL_DATA_IN_RGB16 (2 << 3)
  89. #define PRP_CNTL_DATA_IN_RGB32 (3 << 3)
  90. #define PRP_CNTL_CH1_OUT_RGB8 (0 << 5)
  91. #define PRP_CNTL_CH1_OUT_RGB16 (1 << 5)
  92. #define PRP_CNTL_CH1_OUT_RGB32 (2 << 5)
  93. #define PRP_CNTL_CH1_OUT_YUV422 (3 << 5)
  94. #define PRP_CNTL_CH2_OUT_YUV420 (0 << 7)
  95. #define PRP_CNTL_CH2_OUT_YUV422 (1 << 7)
  96. #define PRP_CNTL_CH2_OUT_YUV444 (2 << 7)
  97. #define PRP_CNTL_CH1_LEN (1 << 9)
  98. #define PRP_CNTL_CH2_LEN (1 << 10)
  99. #define PRP_CNTL_SKIP_FRAME (1 << 11)
  100. #define PRP_CNTL_SWRST (1 << 12)
  101. #define PRP_CNTL_CLKEN (1 << 13)
  102. #define PRP_CNTL_WEN (1 << 14)
  103. #define PRP_CNTL_CH1BYP (1 << 15)
  104. #define PRP_CNTL_IN_TSKIP(x) ((x) << 16)
  105. #define PRP_CNTL_CH1_TSKIP(x) ((x) << 19)
  106. #define PRP_CNTL_CH2_TSKIP(x) ((x) << 22)
  107. #define PRP_CNTL_INPUT_FIFO_LEVEL(x) ((x) << 25)
  108. #define PRP_CNTL_RZ_FIFO_LEVEL(x) ((x) << 27)
  109. #define PRP_CNTL_CH2B1EN (1 << 29)
  110. #define PRP_CNTL_CH2B2EN (1 << 30)
  111. #define PRP_CNTL_CH2FEN (1UL << 31)
  112. #define PRP_SIZE_HEIGHT(x) (x)
  113. #define PRP_SIZE_WIDTH(x) ((x) << 16)
  114. /* IRQ Enable and status register */
  115. #define PRP_INTR_RDERR (1 << 0)
  116. #define PRP_INTR_CH1WERR (1 << 1)
  117. #define PRP_INTR_CH2WERR (1 << 2)
  118. #define PRP_INTR_CH1FC (1 << 3)
  119. #define PRP_INTR_CH2FC (1 << 5)
  120. #define PRP_INTR_LBOVF (1 << 7)
  121. #define PRP_INTR_CH2OVF (1 << 8)
  122. #define PRP_INTR_ST_RDERR (1 << 0)
  123. #define PRP_INTR_ST_CH1WERR (1 << 1)
  124. #define PRP_INTR_ST_CH2WERR (1 << 2)
  125. #define PRP_INTR_ST_CH2B2CI (1 << 3)
  126. #define PRP_INTR_ST_CH2B1CI (1 << 4)
  127. #define PRP_INTR_ST_CH1B2CI (1 << 5)
  128. #define PRP_INTR_ST_CH1B1CI (1 << 6)
  129. #define PRP_INTR_ST_LBOVF (1 << 7)
  130. #define PRP_INTR_ST_CH2OVF (1 << 8)
  131. struct emmaprp_fmt {
  132. u32 fourcc;
  133. /* Types the format can be used for */
  134. u32 types;
  135. };
  136. static struct emmaprp_fmt formats[] = {
  137. {
  138. .fourcc = V4L2_PIX_FMT_YUV420,
  139. .types = MEM2MEM_CAPTURE,
  140. },
  141. {
  142. .fourcc = V4L2_PIX_FMT_YUYV,
  143. .types = MEM2MEM_OUTPUT,
  144. },
  145. };
  146. /* Per-queue, driver-specific private data */
  147. struct emmaprp_q_data {
  148. unsigned int width;
  149. unsigned int height;
  150. unsigned int sizeimage;
  151. struct emmaprp_fmt *fmt;
  152. };
  153. enum {
  154. V4L2_M2M_SRC = 0,
  155. V4L2_M2M_DST = 1,
  156. };
  157. #define NUM_FORMATS ARRAY_SIZE(formats)
  158. static struct emmaprp_fmt *find_format(struct v4l2_format *f)
  159. {
  160. struct emmaprp_fmt *fmt;
  161. unsigned int k;
  162. for (k = 0; k < NUM_FORMATS; k++) {
  163. fmt = &formats[k];
  164. if (fmt->fourcc == f->fmt.pix.pixelformat)
  165. break;
  166. }
  167. if (k == NUM_FORMATS)
  168. return NULL;
  169. return &formats[k];
  170. }
  171. struct emmaprp_dev {
  172. struct v4l2_device v4l2_dev;
  173. struct video_device *vfd;
  174. struct mutex dev_mutex;
  175. spinlock_t irqlock;
  176. void __iomem *base_emma;
  177. struct clk *clk_emma_ahb, *clk_emma_ipg;
  178. struct v4l2_m2m_dev *m2m_dev;
  179. };
  180. struct emmaprp_ctx {
  181. struct v4l2_fh fh;
  182. struct emmaprp_dev *dev;
  183. /* Abort requested by m2m */
  184. int aborting;
  185. struct emmaprp_q_data q_data[2];
  186. };
  187. static struct emmaprp_q_data *get_q_data(struct emmaprp_ctx *ctx,
  188. enum v4l2_buf_type type)
  189. {
  190. switch (type) {
  191. case V4L2_BUF_TYPE_VIDEO_OUTPUT:
  192. return &(ctx->q_data[V4L2_M2M_SRC]);
  193. case V4L2_BUF_TYPE_VIDEO_CAPTURE:
  194. return &(ctx->q_data[V4L2_M2M_DST]);
  195. default:
  196. BUG();
  197. }
  198. return NULL;
  199. }
  200. /*
  201. * mem2mem callbacks
  202. */
  203. static void emmaprp_job_abort(void *priv)
  204. {
  205. struct emmaprp_ctx *ctx = priv;
  206. struct emmaprp_dev *pcdev = ctx->dev;
  207. ctx->aborting = 1;
  208. dprintk(pcdev, "Aborting task\n");
  209. v4l2_m2m_job_finish(pcdev->m2m_dev, ctx->fh.m2m_ctx);
  210. }
  211. static inline void emmaprp_dump_regs(struct emmaprp_dev *pcdev)
  212. {
  213. dprintk(pcdev,
  214. "eMMa-PrP Registers:\n"
  215. " SOURCE_Y_PTR = 0x%08X\n"
  216. " SRC_FRAME_SIZE = 0x%08X\n"
  217. " DEST_Y_PTR = 0x%08X\n"
  218. " DEST_CR_PTR = 0x%08X\n"
  219. " DEST_CB_PTR = 0x%08X\n"
  220. " CH2_OUT_IMAGE_SIZE = 0x%08X\n"
  221. " CNTL = 0x%08X\n",
  222. readl(pcdev->base_emma + PRP_SOURCE_Y_PTR),
  223. readl(pcdev->base_emma + PRP_SRC_FRAME_SIZE),
  224. readl(pcdev->base_emma + PRP_DEST_Y_PTR),
  225. readl(pcdev->base_emma + PRP_DEST_CR_PTR),
  226. readl(pcdev->base_emma + PRP_DEST_CB_PTR),
  227. readl(pcdev->base_emma + PRP_CH2_OUT_IMAGE_SIZE),
  228. readl(pcdev->base_emma + PRP_CNTL));
  229. }
  230. static void emmaprp_device_run(void *priv)
  231. {
  232. struct emmaprp_ctx *ctx = priv;
  233. struct emmaprp_q_data *s_q_data, *d_q_data;
  234. struct vb2_v4l2_buffer *src_buf, *dst_buf;
  235. struct emmaprp_dev *pcdev = ctx->dev;
  236. unsigned int s_width, s_height;
  237. unsigned int d_width, d_height;
  238. unsigned int d_size;
  239. dma_addr_t p_in, p_out;
  240. u32 tmp;
  241. src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
  242. dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  243. s_q_data = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  244. s_width = s_q_data->width;
  245. s_height = s_q_data->height;
  246. d_q_data = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  247. d_width = d_q_data->width;
  248. d_height = d_q_data->height;
  249. d_size = d_width * d_height;
  250. p_in = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
  251. p_out = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
  252. if (!p_in || !p_out) {
  253. v4l2_err(&pcdev->v4l2_dev,
  254. "Acquiring kernel pointers to buffers failed\n");
  255. return;
  256. }
  257. /* Input frame parameters */
  258. writel(p_in, pcdev->base_emma + PRP_SOURCE_Y_PTR);
  259. writel(PRP_SIZE_WIDTH(s_width) | PRP_SIZE_HEIGHT(s_height),
  260. pcdev->base_emma + PRP_SRC_FRAME_SIZE);
  261. /* Output frame parameters */
  262. writel(p_out, pcdev->base_emma + PRP_DEST_Y_PTR);
  263. writel(p_out + d_size, pcdev->base_emma + PRP_DEST_CB_PTR);
  264. writel(p_out + d_size + (d_size >> 2),
  265. pcdev->base_emma + PRP_DEST_CR_PTR);
  266. writel(PRP_SIZE_WIDTH(d_width) | PRP_SIZE_HEIGHT(d_height),
  267. pcdev->base_emma + PRP_CH2_OUT_IMAGE_SIZE);
  268. /* IRQ configuration */
  269. tmp = readl(pcdev->base_emma + PRP_INTR_CNTL);
  270. writel(tmp | PRP_INTR_RDERR |
  271. PRP_INTR_CH2WERR |
  272. PRP_INTR_CH2FC,
  273. pcdev->base_emma + PRP_INTR_CNTL);
  274. emmaprp_dump_regs(pcdev);
  275. /* Enable transfer */
  276. tmp = readl(pcdev->base_emma + PRP_CNTL);
  277. writel(tmp | PRP_CNTL_CH2_OUT_YUV420 |
  278. PRP_CNTL_DATA_IN_YUV422 |
  279. PRP_CNTL_CH2EN,
  280. pcdev->base_emma + PRP_CNTL);
  281. }
  282. static irqreturn_t emmaprp_irq(int irq_emma, void *data)
  283. {
  284. struct emmaprp_dev *pcdev = data;
  285. struct emmaprp_ctx *curr_ctx;
  286. struct vb2_v4l2_buffer *src_vb, *dst_vb;
  287. unsigned long flags;
  288. u32 irqst;
  289. /* Check irq flags and clear irq */
  290. irqst = readl(pcdev->base_emma + PRP_INTRSTATUS);
  291. writel(irqst, pcdev->base_emma + PRP_INTRSTATUS);
  292. dprintk(pcdev, "irqst = 0x%08x\n", irqst);
  293. curr_ctx = v4l2_m2m_get_curr_priv(pcdev->m2m_dev);
  294. if (curr_ctx == NULL) {
  295. pr_err("Instance released before the end of transaction\n");
  296. return IRQ_HANDLED;
  297. }
  298. if (!curr_ctx->aborting) {
  299. if ((irqst & PRP_INTR_ST_RDERR) ||
  300. (irqst & PRP_INTR_ST_CH2WERR)) {
  301. pr_err("PrP bus error occurred, this transfer is probably corrupted\n");
  302. writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL);
  303. } else if (irqst & PRP_INTR_ST_CH2B1CI) { /* buffer ready */
  304. src_vb = v4l2_m2m_src_buf_remove(curr_ctx->fh.m2m_ctx);
  305. dst_vb = v4l2_m2m_dst_buf_remove(curr_ctx->fh.m2m_ctx);
  306. dst_vb->vb2_buf.timestamp = src_vb->vb2_buf.timestamp;
  307. dst_vb->flags &=
  308. ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
  309. dst_vb->flags |=
  310. src_vb->flags
  311. & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
  312. dst_vb->timecode = src_vb->timecode;
  313. spin_lock_irqsave(&pcdev->irqlock, flags);
  314. v4l2_m2m_buf_done(src_vb, VB2_BUF_STATE_DONE);
  315. v4l2_m2m_buf_done(dst_vb, VB2_BUF_STATE_DONE);
  316. spin_unlock_irqrestore(&pcdev->irqlock, flags);
  317. }
  318. }
  319. v4l2_m2m_job_finish(pcdev->m2m_dev, curr_ctx->fh.m2m_ctx);
  320. return IRQ_HANDLED;
  321. }
  322. /*
  323. * video ioctls
  324. */
  325. static int vidioc_querycap(struct file *file, void *priv,
  326. struct v4l2_capability *cap)
  327. {
  328. strscpy(cap->driver, MEM2MEM_NAME, sizeof(cap->driver));
  329. strscpy(cap->card, MEM2MEM_NAME, sizeof(cap->card));
  330. return 0;
  331. }
  332. static int enum_fmt(struct v4l2_fmtdesc *f, u32 type)
  333. {
  334. int i, num;
  335. struct emmaprp_fmt *fmt;
  336. num = 0;
  337. for (i = 0; i < NUM_FORMATS; ++i) {
  338. if (formats[i].types & type) {
  339. /* index-th format of type type found ? */
  340. if (num == f->index)
  341. break;
  342. /* Correct type but haven't reached our index yet,
  343. * just increment per-type index */
  344. ++num;
  345. }
  346. }
  347. if (i < NUM_FORMATS) {
  348. /* Format found */
  349. fmt = &formats[i];
  350. f->pixelformat = fmt->fourcc;
  351. return 0;
  352. }
  353. /* Format not found */
  354. return -EINVAL;
  355. }
  356. static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
  357. struct v4l2_fmtdesc *f)
  358. {
  359. return enum_fmt(f, MEM2MEM_CAPTURE);
  360. }
  361. static int vidioc_enum_fmt_vid_out(struct file *file, void *priv,
  362. struct v4l2_fmtdesc *f)
  363. {
  364. return enum_fmt(f, MEM2MEM_OUTPUT);
  365. }
  366. static int vidioc_g_fmt(struct emmaprp_ctx *ctx, struct v4l2_format *f)
  367. {
  368. struct vb2_queue *vq;
  369. struct emmaprp_q_data *q_data;
  370. vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
  371. if (!vq)
  372. return -EINVAL;
  373. q_data = get_q_data(ctx, f->type);
  374. f->fmt.pix.width = q_data->width;
  375. f->fmt.pix.height = q_data->height;
  376. f->fmt.pix.field = V4L2_FIELD_NONE;
  377. f->fmt.pix.pixelformat = q_data->fmt->fourcc;
  378. if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420)
  379. f->fmt.pix.bytesperline = q_data->width * 3 / 2;
  380. else /* YUYV */
  381. f->fmt.pix.bytesperline = q_data->width * 2;
  382. f->fmt.pix.sizeimage = q_data->sizeimage;
  383. return 0;
  384. }
  385. static int vidioc_g_fmt_vid_out(struct file *file, void *priv,
  386. struct v4l2_format *f)
  387. {
  388. return vidioc_g_fmt(priv, f);
  389. }
  390. static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
  391. struct v4l2_format *f)
  392. {
  393. return vidioc_g_fmt(priv, f);
  394. }
  395. static int vidioc_try_fmt(struct v4l2_format *f)
  396. {
  397. enum v4l2_field field;
  398. if (!find_format(f))
  399. return -EINVAL;
  400. field = f->fmt.pix.field;
  401. if (field == V4L2_FIELD_ANY)
  402. field = V4L2_FIELD_NONE;
  403. else if (V4L2_FIELD_NONE != field)
  404. return -EINVAL;
  405. /* V4L2 specification suggests the driver corrects the format struct
  406. * if any of the dimensions is unsupported */
  407. f->fmt.pix.field = field;
  408. if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420) {
  409. v4l_bound_align_image(&f->fmt.pix.width, MIN_W, MAX_W,
  410. W_ALIGN_YUV420, &f->fmt.pix.height,
  411. MIN_H, MAX_H, H_ALIGN, S_ALIGN);
  412. f->fmt.pix.bytesperline = f->fmt.pix.width * 3 / 2;
  413. } else {
  414. v4l_bound_align_image(&f->fmt.pix.width, MIN_W, MAX_W,
  415. W_ALIGN_OTHERS, &f->fmt.pix.height,
  416. MIN_H, MAX_H, H_ALIGN, S_ALIGN);
  417. f->fmt.pix.bytesperline = f->fmt.pix.width * 2;
  418. }
  419. f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline;
  420. return 0;
  421. }
  422. static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
  423. struct v4l2_format *f)
  424. {
  425. struct emmaprp_fmt *fmt;
  426. struct emmaprp_ctx *ctx = priv;
  427. fmt = find_format(f);
  428. if (!fmt || !(fmt->types & MEM2MEM_CAPTURE)) {
  429. v4l2_err(&ctx->dev->v4l2_dev,
  430. "Fourcc format (0x%08x) invalid.\n",
  431. f->fmt.pix.pixelformat);
  432. return -EINVAL;
  433. }
  434. return vidioc_try_fmt(f);
  435. }
  436. static int vidioc_try_fmt_vid_out(struct file *file, void *priv,
  437. struct v4l2_format *f)
  438. {
  439. struct emmaprp_fmt *fmt;
  440. struct emmaprp_ctx *ctx = priv;
  441. fmt = find_format(f);
  442. if (!fmt || !(fmt->types & MEM2MEM_OUTPUT)) {
  443. v4l2_err(&ctx->dev->v4l2_dev,
  444. "Fourcc format (0x%08x) invalid.\n",
  445. f->fmt.pix.pixelformat);
  446. return -EINVAL;
  447. }
  448. return vidioc_try_fmt(f);
  449. }
  450. static int vidioc_s_fmt(struct emmaprp_ctx *ctx, struct v4l2_format *f)
  451. {
  452. struct emmaprp_q_data *q_data;
  453. struct vb2_queue *vq;
  454. int ret;
  455. vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
  456. if (!vq)
  457. return -EINVAL;
  458. q_data = get_q_data(ctx, f->type);
  459. if (!q_data)
  460. return -EINVAL;
  461. if (vb2_is_busy(vq)) {
  462. v4l2_err(&ctx->dev->v4l2_dev, "%s queue busy\n", __func__);
  463. return -EBUSY;
  464. }
  465. ret = vidioc_try_fmt(f);
  466. if (ret)
  467. return ret;
  468. q_data->fmt = find_format(f);
  469. q_data->width = f->fmt.pix.width;
  470. q_data->height = f->fmt.pix.height;
  471. if (q_data->fmt->fourcc == V4L2_PIX_FMT_YUV420)
  472. q_data->sizeimage = q_data->width * q_data->height * 3 / 2;
  473. else /* YUYV */
  474. q_data->sizeimage = q_data->width * q_data->height * 2;
  475. dprintk(ctx->dev,
  476. "Setting format for type %d, wxh: %dx%d, fmt: %d\n",
  477. f->type, q_data->width, q_data->height, q_data->fmt->fourcc);
  478. return 0;
  479. }
  480. static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
  481. struct v4l2_format *f)
  482. {
  483. int ret;
  484. ret = vidioc_try_fmt_vid_cap(file, priv, f);
  485. if (ret)
  486. return ret;
  487. return vidioc_s_fmt(priv, f);
  488. }
  489. static int vidioc_s_fmt_vid_out(struct file *file, void *priv,
  490. struct v4l2_format *f)
  491. {
  492. int ret;
  493. ret = vidioc_try_fmt_vid_out(file, priv, f);
  494. if (ret)
  495. return ret;
  496. return vidioc_s_fmt(priv, f);
  497. }
  498. static const struct v4l2_ioctl_ops emmaprp_ioctl_ops = {
  499. .vidioc_querycap = vidioc_querycap,
  500. .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
  501. .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
  502. .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
  503. .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
  504. .vidioc_enum_fmt_vid_out = vidioc_enum_fmt_vid_out,
  505. .vidioc_g_fmt_vid_out = vidioc_g_fmt_vid_out,
  506. .vidioc_try_fmt_vid_out = vidioc_try_fmt_vid_out,
  507. .vidioc_s_fmt_vid_out = vidioc_s_fmt_vid_out,
  508. .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
  509. .vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
  510. .vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
  511. .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
  512. .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
  513. .vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
  514. .vidioc_streamon = v4l2_m2m_ioctl_streamon,
  515. .vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
  516. };
  517. /*
  518. * Queue operations
  519. */
  520. static int emmaprp_queue_setup(struct vb2_queue *vq,
  521. unsigned int *nbuffers, unsigned int *nplanes,
  522. unsigned int sizes[], struct device *alloc_devs[])
  523. {
  524. struct emmaprp_ctx *ctx = vb2_get_drv_priv(vq);
  525. struct emmaprp_q_data *q_data;
  526. unsigned int size, count = *nbuffers;
  527. q_data = get_q_data(ctx, vq->type);
  528. if (q_data->fmt->fourcc == V4L2_PIX_FMT_YUV420)
  529. size = q_data->width * q_data->height * 3 / 2;
  530. else
  531. size = q_data->width * q_data->height * 2;
  532. while (size * count > MEM2MEM_VID_MEM_LIMIT)
  533. (count)--;
  534. *nplanes = 1;
  535. *nbuffers = count;
  536. sizes[0] = size;
  537. dprintk(ctx->dev, "get %d buffer(s) of size %d each.\n", count, size);
  538. return 0;
  539. }
  540. static int emmaprp_buf_prepare(struct vb2_buffer *vb)
  541. {
  542. struct emmaprp_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
  543. struct emmaprp_q_data *q_data;
  544. dprintk(ctx->dev, "type: %d\n", vb->vb2_queue->type);
  545. q_data = get_q_data(ctx, vb->vb2_queue->type);
  546. if (vb2_plane_size(vb, 0) < q_data->sizeimage) {
  547. dprintk(ctx->dev,
  548. "%s data will not fit into plane(%lu < %lu)\n",
  549. __func__, vb2_plane_size(vb, 0),
  550. (long)q_data->sizeimage);
  551. return -EINVAL;
  552. }
  553. vb2_set_plane_payload(vb, 0, q_data->sizeimage);
  554. return 0;
  555. }
  556. static void emmaprp_buf_queue(struct vb2_buffer *vb)
  557. {
  558. struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
  559. struct emmaprp_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
  560. v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
  561. }
  562. static const struct vb2_ops emmaprp_qops = {
  563. .queue_setup = emmaprp_queue_setup,
  564. .buf_prepare = emmaprp_buf_prepare,
  565. .buf_queue = emmaprp_buf_queue,
  566. .wait_prepare = vb2_ops_wait_prepare,
  567. .wait_finish = vb2_ops_wait_finish,
  568. };
  569. static int queue_init(void *priv, struct vb2_queue *src_vq,
  570. struct vb2_queue *dst_vq)
  571. {
  572. struct emmaprp_ctx *ctx = priv;
  573. int ret;
  574. src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
  575. src_vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
  576. src_vq->drv_priv = ctx;
  577. src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
  578. src_vq->ops = &emmaprp_qops;
  579. src_vq->mem_ops = &vb2_dma_contig_memops;
  580. src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
  581. src_vq->dev = ctx->dev->v4l2_dev.dev;
  582. src_vq->lock = &ctx->dev->dev_mutex;
  583. ret = vb2_queue_init(src_vq);
  584. if (ret)
  585. return ret;
  586. dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
  587. dst_vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
  588. dst_vq->drv_priv = ctx;
  589. dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
  590. dst_vq->ops = &emmaprp_qops;
  591. dst_vq->mem_ops = &vb2_dma_contig_memops;
  592. dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
  593. dst_vq->dev = ctx->dev->v4l2_dev.dev;
  594. dst_vq->lock = &ctx->dev->dev_mutex;
  595. return vb2_queue_init(dst_vq);
  596. }
  597. /*
  598. * File operations
  599. */
  600. static int emmaprp_open(struct file *file)
  601. {
  602. struct emmaprp_dev *pcdev = video_drvdata(file);
  603. struct emmaprp_ctx *ctx;
  604. ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
  605. if (!ctx)
  606. return -ENOMEM;
  607. v4l2_fh_init(&ctx->fh, video_devdata(file));
  608. file->private_data = &ctx->fh;
  609. ctx->dev = pcdev;
  610. if (mutex_lock_interruptible(&pcdev->dev_mutex)) {
  611. kfree(ctx);
  612. return -ERESTARTSYS;
  613. }
  614. ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(pcdev->m2m_dev, ctx, &queue_init);
  615. if (IS_ERR(ctx->fh.m2m_ctx)) {
  616. int ret = PTR_ERR(ctx->fh.m2m_ctx);
  617. mutex_unlock(&pcdev->dev_mutex);
  618. kfree(ctx);
  619. return ret;
  620. }
  621. clk_prepare_enable(pcdev->clk_emma_ipg);
  622. clk_prepare_enable(pcdev->clk_emma_ahb);
  623. ctx->q_data[V4L2_M2M_SRC].fmt = &formats[1];
  624. ctx->q_data[V4L2_M2M_DST].fmt = &formats[0];
  625. v4l2_fh_add(&ctx->fh);
  626. mutex_unlock(&pcdev->dev_mutex);
  627. dprintk(pcdev, "Created instance %p, m2m_ctx: %p\n", ctx, ctx->fh.m2m_ctx);
  628. return 0;
  629. }
  630. static int emmaprp_release(struct file *file)
  631. {
  632. struct emmaprp_dev *pcdev = video_drvdata(file);
  633. struct emmaprp_ctx *ctx = file->private_data;
  634. dprintk(pcdev, "Releasing instance %p\n", ctx);
  635. mutex_lock(&pcdev->dev_mutex);
  636. clk_disable_unprepare(pcdev->clk_emma_ahb);
  637. clk_disable_unprepare(pcdev->clk_emma_ipg);
  638. v4l2_fh_del(&ctx->fh);
  639. v4l2_fh_exit(&ctx->fh);
  640. v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
  641. mutex_unlock(&pcdev->dev_mutex);
  642. kfree(ctx);
  643. return 0;
  644. }
  645. static const struct v4l2_file_operations emmaprp_fops = {
  646. .owner = THIS_MODULE,
  647. .open = emmaprp_open,
  648. .release = emmaprp_release,
  649. .poll = v4l2_m2m_fop_poll,
  650. .unlocked_ioctl = video_ioctl2,
  651. .mmap = v4l2_m2m_fop_mmap,
  652. };
  653. static const struct video_device emmaprp_videodev = {
  654. .name = MEM2MEM_NAME,
  655. .fops = &emmaprp_fops,
  656. .ioctl_ops = &emmaprp_ioctl_ops,
  657. .minor = -1,
  658. .release = video_device_release,
  659. .vfl_dir = VFL_DIR_M2M,
  660. .device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING,
  661. };
  662. static const struct v4l2_m2m_ops m2m_ops = {
  663. .device_run = emmaprp_device_run,
  664. .job_abort = emmaprp_job_abort,
  665. };
  666. static int emmaprp_probe(struct platform_device *pdev)
  667. {
  668. struct emmaprp_dev *pcdev;
  669. struct video_device *vfd;
  670. struct resource *res;
  671. int irq, ret;
  672. pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL);
  673. if (!pcdev)
  674. return -ENOMEM;
  675. spin_lock_init(&pcdev->irqlock);
  676. pcdev->clk_emma_ipg = devm_clk_get(&pdev->dev, "ipg");
  677. if (IS_ERR(pcdev->clk_emma_ipg)) {
  678. return PTR_ERR(pcdev->clk_emma_ipg);
  679. }
  680. pcdev->clk_emma_ahb = devm_clk_get(&pdev->dev, "ahb");
  681. if (IS_ERR(pcdev->clk_emma_ahb))
  682. return PTR_ERR(pcdev->clk_emma_ahb);
  683. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  684. pcdev->base_emma = devm_ioremap_resource(&pdev->dev, res);
  685. if (IS_ERR(pcdev->base_emma))
  686. return PTR_ERR(pcdev->base_emma);
  687. ret = v4l2_device_register(&pdev->dev, &pcdev->v4l2_dev);
  688. if (ret)
  689. return ret;
  690. mutex_init(&pcdev->dev_mutex);
  691. vfd = video_device_alloc();
  692. if (!vfd) {
  693. v4l2_err(&pcdev->v4l2_dev, "Failed to allocate video device\n");
  694. ret = -ENOMEM;
  695. goto unreg_dev;
  696. }
  697. *vfd = emmaprp_videodev;
  698. vfd->lock = &pcdev->dev_mutex;
  699. vfd->v4l2_dev = &pcdev->v4l2_dev;
  700. video_set_drvdata(vfd, pcdev);
  701. pcdev->vfd = vfd;
  702. v4l2_info(&pcdev->v4l2_dev, EMMAPRP_MODULE_NAME
  703. " Device registered as /dev/video%d\n", vfd->num);
  704. platform_set_drvdata(pdev, pcdev);
  705. irq = platform_get_irq(pdev, 0);
  706. if (irq < 0) {
  707. ret = irq;
  708. goto rel_vdev;
  709. }
  710. ret = devm_request_irq(&pdev->dev, irq, emmaprp_irq, 0,
  711. dev_name(&pdev->dev), pcdev);
  712. if (ret)
  713. goto rel_vdev;
  714. pcdev->m2m_dev = v4l2_m2m_init(&m2m_ops);
  715. if (IS_ERR(pcdev->m2m_dev)) {
  716. v4l2_err(&pcdev->v4l2_dev, "Failed to init mem2mem device\n");
  717. ret = PTR_ERR(pcdev->m2m_dev);
  718. goto rel_vdev;
  719. }
  720. ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
  721. if (ret) {
  722. v4l2_err(&pcdev->v4l2_dev, "Failed to register video device\n");
  723. goto rel_m2m;
  724. }
  725. return 0;
  726. rel_m2m:
  727. v4l2_m2m_release(pcdev->m2m_dev);
  728. rel_vdev:
  729. video_device_release(vfd);
  730. unreg_dev:
  731. v4l2_device_unregister(&pcdev->v4l2_dev);
  732. mutex_destroy(&pcdev->dev_mutex);
  733. return ret;
  734. }
  735. static int emmaprp_remove(struct platform_device *pdev)
  736. {
  737. struct emmaprp_dev *pcdev = platform_get_drvdata(pdev);
  738. v4l2_info(&pcdev->v4l2_dev, "Removing " EMMAPRP_MODULE_NAME);
  739. video_unregister_device(pcdev->vfd);
  740. v4l2_m2m_release(pcdev->m2m_dev);
  741. v4l2_device_unregister(&pcdev->v4l2_dev);
  742. mutex_destroy(&pcdev->dev_mutex);
  743. return 0;
  744. }
  745. static struct platform_driver emmaprp_pdrv = {
  746. .probe = emmaprp_probe,
  747. .remove = emmaprp_remove,
  748. .driver = {
  749. .name = MEM2MEM_NAME,
  750. },
  751. };
  752. module_platform_driver(emmaprp_pdrv);