imx-pxp.c 50 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * i.MX Pixel Pipeline (PXP) mem-to-mem scaler/CSC/rotator driver
  4. *
  5. * Copyright (c) 2018 Pengutronix, Philipp Zabel
  6. *
  7. * based on vim2m
  8. *
  9. * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
  10. * Pawel Osciak, <pawel@osciak.com>
  11. * Marek Szyprowski, <m.szyprowski@samsung.com>
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/delay.h>
  15. #include <linux/dma-mapping.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/io.h>
  18. #include <linux/iopoll.h>
  19. #include <linux/module.h>
  20. #include <linux/of.h>
  21. #include <linux/sched.h>
  22. #include <linux/slab.h>
  23. #include <linux/platform_device.h>
  24. #include <media/v4l2-mem2mem.h>
  25. #include <media/v4l2-device.h>
  26. #include <media/v4l2-ioctl.h>
  27. #include <media/v4l2-ctrls.h>
  28. #include <media/v4l2-event.h>
  29. #include <media/videobuf2-dma-contig.h>
  30. #include "imx-pxp.h"
  31. static unsigned int debug;
  32. module_param(debug, uint, 0644);
  33. MODULE_PARM_DESC(debug, "activates debug info");
  34. #define MIN_W 8
  35. #define MIN_H 8
  36. #define MAX_W 4096
  37. #define MAX_H 4096
  38. #define ALIGN_W 3 /* 8x8 pixel blocks */
  39. #define ALIGN_H 3
  40. /* Flags that indicate a format can be used for capture/output */
  41. #define MEM2MEM_CAPTURE (1 << 0)
  42. #define MEM2MEM_OUTPUT (1 << 1)
  43. #define MEM2MEM_NAME "pxp"
  44. /* Flags that indicate processing mode */
  45. #define MEM2MEM_HFLIP (1 << 0)
  46. #define MEM2MEM_VFLIP (1 << 1)
  47. #define dprintk(dev, fmt, arg...) \
  48. v4l2_dbg(1, debug, &dev->v4l2_dev, "%s: " fmt, __func__, ## arg)
  49. struct pxp_fmt {
  50. u32 fourcc;
  51. int depth;
  52. /* Types the format can be used for */
  53. u32 types;
  54. };
  55. static struct pxp_fmt formats[] = {
  56. {
  57. .fourcc = V4L2_PIX_FMT_XBGR32,
  58. .depth = 32,
  59. /* Both capture and output format */
  60. .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
  61. }, {
  62. .fourcc = V4L2_PIX_FMT_ABGR32,
  63. .depth = 32,
  64. /* Capture-only format */
  65. .types = MEM2MEM_CAPTURE,
  66. }, {
  67. .fourcc = V4L2_PIX_FMT_BGR24,
  68. .depth = 24,
  69. .types = MEM2MEM_CAPTURE,
  70. }, {
  71. .fourcc = V4L2_PIX_FMT_RGB565,
  72. .depth = 16,
  73. .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
  74. }, {
  75. .fourcc = V4L2_PIX_FMT_RGB555,
  76. .depth = 16,
  77. .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
  78. }, {
  79. .fourcc = V4L2_PIX_FMT_RGB444,
  80. .depth = 16,
  81. .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
  82. }, {
  83. .fourcc = V4L2_PIX_FMT_VUYA32,
  84. .depth = 32,
  85. .types = MEM2MEM_CAPTURE,
  86. }, {
  87. .fourcc = V4L2_PIX_FMT_VUYX32,
  88. .depth = 32,
  89. .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
  90. }, {
  91. .fourcc = V4L2_PIX_FMT_UYVY,
  92. .depth = 16,
  93. .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
  94. }, {
  95. .fourcc = V4L2_PIX_FMT_YUYV,
  96. .depth = 16,
  97. /* Output-only format */
  98. .types = MEM2MEM_OUTPUT,
  99. }, {
  100. .fourcc = V4L2_PIX_FMT_VYUY,
  101. .depth = 16,
  102. .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
  103. }, {
  104. .fourcc = V4L2_PIX_FMT_YVYU,
  105. .depth = 16,
  106. .types = MEM2MEM_OUTPUT,
  107. }, {
  108. .fourcc = V4L2_PIX_FMT_GREY,
  109. .depth = 8,
  110. .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
  111. }, {
  112. .fourcc = V4L2_PIX_FMT_Y4,
  113. .depth = 4,
  114. .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
  115. }, {
  116. .fourcc = V4L2_PIX_FMT_NV16,
  117. .depth = 16,
  118. .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
  119. }, {
  120. .fourcc = V4L2_PIX_FMT_NV12,
  121. .depth = 12,
  122. .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
  123. }, {
  124. .fourcc = V4L2_PIX_FMT_NV21,
  125. .depth = 12,
  126. .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
  127. }, {
  128. .fourcc = V4L2_PIX_FMT_NV61,
  129. .depth = 16,
  130. .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
  131. }, {
  132. .fourcc = V4L2_PIX_FMT_YUV422P,
  133. .depth = 16,
  134. .types = MEM2MEM_OUTPUT,
  135. }, {
  136. .fourcc = V4L2_PIX_FMT_YUV420,
  137. .depth = 12,
  138. .types = MEM2MEM_OUTPUT,
  139. },
  140. };
  141. #define NUM_FORMATS ARRAY_SIZE(formats)
  142. /* Per-queue, driver-specific private data */
  143. struct pxp_q_data {
  144. unsigned int width;
  145. unsigned int height;
  146. unsigned int bytesperline;
  147. unsigned int sizeimage;
  148. unsigned int sequence;
  149. struct pxp_fmt *fmt;
  150. enum v4l2_ycbcr_encoding ycbcr_enc;
  151. enum v4l2_quantization quant;
  152. };
  153. enum {
  154. V4L2_M2M_SRC = 0,
  155. V4L2_M2M_DST = 1,
  156. };
  157. static struct pxp_fmt *find_format(struct v4l2_format *f)
  158. {
  159. struct pxp_fmt *fmt;
  160. unsigned int k;
  161. for (k = 0; k < NUM_FORMATS; k++) {
  162. fmt = &formats[k];
  163. if (fmt->fourcc == f->fmt.pix.pixelformat)
  164. break;
  165. }
  166. if (k == NUM_FORMATS)
  167. return NULL;
  168. return &formats[k];
  169. }
  170. struct pxp_dev {
  171. struct v4l2_device v4l2_dev;
  172. struct video_device vfd;
  173. struct clk *clk;
  174. void __iomem *mmio;
  175. atomic_t num_inst;
  176. struct mutex dev_mutex;
  177. spinlock_t irqlock;
  178. struct v4l2_m2m_dev *m2m_dev;
  179. };
  180. struct pxp_ctx {
  181. struct v4l2_fh fh;
  182. struct pxp_dev *dev;
  183. struct v4l2_ctrl_handler hdl;
  184. /* Abort requested by m2m */
  185. int aborting;
  186. /* Processing mode */
  187. int mode;
  188. u8 alpha_component;
  189. enum v4l2_colorspace colorspace;
  190. enum v4l2_xfer_func xfer_func;
  191. /* Source and destination queue data */
  192. struct pxp_q_data q_data[2];
  193. };
  194. static inline struct pxp_ctx *file2ctx(struct file *file)
  195. {
  196. return container_of(file->private_data, struct pxp_ctx, fh);
  197. }
  198. static struct pxp_q_data *get_q_data(struct pxp_ctx *ctx,
  199. enum v4l2_buf_type type)
  200. {
  201. if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
  202. return &ctx->q_data[V4L2_M2M_SRC];
  203. else
  204. return &ctx->q_data[V4L2_M2M_DST];
  205. }
  206. static u32 pxp_v4l2_pix_fmt_to_ps_format(u32 v4l2_pix_fmt)
  207. {
  208. switch (v4l2_pix_fmt) {
  209. case V4L2_PIX_FMT_XBGR32: return BV_PXP_PS_CTRL_FORMAT__RGB888;
  210. case V4L2_PIX_FMT_RGB555: return BV_PXP_PS_CTRL_FORMAT__RGB555;
  211. case V4L2_PIX_FMT_RGB444: return BV_PXP_PS_CTRL_FORMAT__RGB444;
  212. case V4L2_PIX_FMT_RGB565: return BV_PXP_PS_CTRL_FORMAT__RGB565;
  213. case V4L2_PIX_FMT_VUYX32: return BV_PXP_PS_CTRL_FORMAT__YUV1P444;
  214. case V4L2_PIX_FMT_UYVY: return BV_PXP_PS_CTRL_FORMAT__UYVY1P422;
  215. case V4L2_PIX_FMT_YUYV: return BM_PXP_PS_CTRL_WB_SWAP |
  216. BV_PXP_PS_CTRL_FORMAT__UYVY1P422;
  217. case V4L2_PIX_FMT_VYUY: return BV_PXP_PS_CTRL_FORMAT__VYUY1P422;
  218. case V4L2_PIX_FMT_YVYU: return BM_PXP_PS_CTRL_WB_SWAP |
  219. BV_PXP_PS_CTRL_FORMAT__VYUY1P422;
  220. case V4L2_PIX_FMT_GREY: return BV_PXP_PS_CTRL_FORMAT__Y8;
  221. default:
  222. case V4L2_PIX_FMT_Y4: return BV_PXP_PS_CTRL_FORMAT__Y4;
  223. case V4L2_PIX_FMT_NV16: return BV_PXP_PS_CTRL_FORMAT__YUV2P422;
  224. case V4L2_PIX_FMT_NV12: return BV_PXP_PS_CTRL_FORMAT__YUV2P420;
  225. case V4L2_PIX_FMT_NV21: return BV_PXP_PS_CTRL_FORMAT__YVU2P420;
  226. case V4L2_PIX_FMT_NV61: return BV_PXP_PS_CTRL_FORMAT__YVU2P422;
  227. case V4L2_PIX_FMT_YUV422P: return BV_PXP_PS_CTRL_FORMAT__YUV422;
  228. case V4L2_PIX_FMT_YUV420: return BV_PXP_PS_CTRL_FORMAT__YUV420;
  229. }
  230. }
  231. static u32 pxp_v4l2_pix_fmt_to_out_format(u32 v4l2_pix_fmt)
  232. {
  233. switch (v4l2_pix_fmt) {
  234. case V4L2_PIX_FMT_XBGR32: return BV_PXP_OUT_CTRL_FORMAT__RGB888;
  235. case V4L2_PIX_FMT_ABGR32: return BV_PXP_OUT_CTRL_FORMAT__ARGB8888;
  236. case V4L2_PIX_FMT_BGR24: return BV_PXP_OUT_CTRL_FORMAT__RGB888P;
  237. /* Missing V4L2 pixel formats for ARGB1555 and ARGB4444 */
  238. case V4L2_PIX_FMT_RGB555: return BV_PXP_OUT_CTRL_FORMAT__RGB555;
  239. case V4L2_PIX_FMT_RGB444: return BV_PXP_OUT_CTRL_FORMAT__RGB444;
  240. case V4L2_PIX_FMT_RGB565: return BV_PXP_OUT_CTRL_FORMAT__RGB565;
  241. case V4L2_PIX_FMT_VUYA32:
  242. case V4L2_PIX_FMT_VUYX32: return BV_PXP_OUT_CTRL_FORMAT__YUV1P444;
  243. case V4L2_PIX_FMT_UYVY: return BV_PXP_OUT_CTRL_FORMAT__UYVY1P422;
  244. case V4L2_PIX_FMT_VYUY: return BV_PXP_OUT_CTRL_FORMAT__VYUY1P422;
  245. case V4L2_PIX_FMT_GREY: return BV_PXP_OUT_CTRL_FORMAT__Y8;
  246. default:
  247. case V4L2_PIX_FMT_Y4: return BV_PXP_OUT_CTRL_FORMAT__Y4;
  248. case V4L2_PIX_FMT_NV16: return BV_PXP_OUT_CTRL_FORMAT__YUV2P422;
  249. case V4L2_PIX_FMT_NV12: return BV_PXP_OUT_CTRL_FORMAT__YUV2P420;
  250. case V4L2_PIX_FMT_NV61: return BV_PXP_OUT_CTRL_FORMAT__YVU2P422;
  251. case V4L2_PIX_FMT_NV21: return BV_PXP_OUT_CTRL_FORMAT__YVU2P420;
  252. }
  253. }
  254. static bool pxp_v4l2_pix_fmt_is_yuv(u32 v4l2_pix_fmt)
  255. {
  256. switch (v4l2_pix_fmt) {
  257. case V4L2_PIX_FMT_VUYA32:
  258. case V4L2_PIX_FMT_VUYX32:
  259. case V4L2_PIX_FMT_UYVY:
  260. case V4L2_PIX_FMT_YUYV:
  261. case V4L2_PIX_FMT_VYUY:
  262. case V4L2_PIX_FMT_YVYU:
  263. case V4L2_PIX_FMT_NV16:
  264. case V4L2_PIX_FMT_NV12:
  265. case V4L2_PIX_FMT_NV61:
  266. case V4L2_PIX_FMT_NV21:
  267. case V4L2_PIX_FMT_YUV420:
  268. case V4L2_PIX_FMT_YUV422P:
  269. case V4L2_PIX_FMT_GREY:
  270. case V4L2_PIX_FMT_Y4:
  271. return true;
  272. default:
  273. return false;
  274. }
  275. }
  276. static void pxp_setup_csc(struct pxp_ctx *ctx)
  277. {
  278. struct pxp_dev *dev = ctx->dev;
  279. enum v4l2_ycbcr_encoding ycbcr_enc;
  280. enum v4l2_quantization quantization;
  281. if (pxp_v4l2_pix_fmt_is_yuv(ctx->q_data[V4L2_M2M_SRC].fmt->fourcc) &&
  282. !pxp_v4l2_pix_fmt_is_yuv(ctx->q_data[V4L2_M2M_DST].fmt->fourcc)) {
  283. /*
  284. * CSC1 YUV/YCbCr to RGB conversion is implemented as follows:
  285. *
  286. * |R| |C0 0 C1| |Y + Yoffset |
  287. * |G| = |C0 C3 C2| * |Cb + UVoffset|
  288. * |B| |C0 C4 0 | |Cr + UVoffset|
  289. *
  290. * Results are clamped to 0..255.
  291. *
  292. * BT.601 limited range:
  293. *
  294. * |R| |1.1644 0.0000 1.5960| |Y - 16 |
  295. * |G| = |1.1644 -0.3917 -0.8129| * |Cb - 128|
  296. * |B| |1.1644 2.0172 0.0000| |Cr - 128|
  297. */
  298. static const u32 csc1_coef_bt601_lim[3] = {
  299. BM_PXP_CSC1_COEF0_YCBCR_MODE |
  300. BF_PXP_CSC1_COEF0_C0(0x12a) | /* 1.1641 (-0.03 %) */
  301. BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
  302. BF_PXP_CSC1_COEF0_Y_OFFSET(-16),
  303. BF_PXP_CSC1_COEF1_C1(0x198) | /* 1.5938 (-0.23 %) */
  304. BF_PXP_CSC1_COEF1_C4(0x204), /* 2.0156 (-0.16 %) */
  305. BF_PXP_CSC1_COEF2_C2(0x730) | /* -0.8125 (+0.04 %) */
  306. BF_PXP_CSC1_COEF2_C3(0x79c), /* -0.3906 (+0.11 %) */
  307. };
  308. /*
  309. * BT.601 full range:
  310. *
  311. * |R| |1.0000 0.0000 1.4020| |Y + 0 |
  312. * |G| = |1.0000 -0.3441 -0.7141| * |Cb - 128|
  313. * |B| |1.0000 1.7720 0.0000| |Cr - 128|
  314. */
  315. static const u32 csc1_coef_bt601_full[3] = {
  316. BM_PXP_CSC1_COEF0_YCBCR_MODE |
  317. BF_PXP_CSC1_COEF0_C0(0x100) | /* 1.0000 (+0.00 %) */
  318. BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
  319. BF_PXP_CSC1_COEF0_Y_OFFSET(0),
  320. BF_PXP_CSC1_COEF1_C1(0x166) | /* 1.3984 (-0.36 %) */
  321. BF_PXP_CSC1_COEF1_C4(0x1c5), /* 1.7695 (-0.25 %) */
  322. BF_PXP_CSC1_COEF2_C2(0x74a) | /* -0.7109 (+0.32 %) */
  323. BF_PXP_CSC1_COEF2_C3(0x7a8), /* -0.3438 (+0.04 %) */
  324. };
  325. /*
  326. * Rec.709 limited range:
  327. *
  328. * |R| |1.1644 0.0000 1.7927| |Y - 16 |
  329. * |G| = |1.1644 -0.2132 -0.5329| * |Cb - 128|
  330. * |B| |1.1644 2.1124 0.0000| |Cr - 128|
  331. */
  332. static const u32 csc1_coef_rec709_lim[3] = {
  333. BM_PXP_CSC1_COEF0_YCBCR_MODE |
  334. BF_PXP_CSC1_COEF0_C0(0x12a) | /* 1.1641 (-0.03 %) */
  335. BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
  336. BF_PXP_CSC1_COEF0_Y_OFFSET(-16),
  337. BF_PXP_CSC1_COEF1_C1(0x1ca) | /* 1.7891 (-0.37 %) */
  338. BF_PXP_CSC1_COEF1_C4(0x21c), /* 2.1094 (-0.30 %) */
  339. BF_PXP_CSC1_COEF2_C2(0x778) | /* -0.5312 (+0.16 %) */
  340. BF_PXP_CSC1_COEF2_C3(0x7ca), /* -0.2109 (+0.23 %) */
  341. };
  342. /*
  343. * Rec.709 full range:
  344. *
  345. * |R| |1.0000 0.0000 1.5748| |Y + 0 |
  346. * |G| = |1.0000 -0.1873 -0.4681| * |Cb - 128|
  347. * |B| |1.0000 1.8556 0.0000| |Cr - 128|
  348. */
  349. static const u32 csc1_coef_rec709_full[3] = {
  350. BM_PXP_CSC1_COEF0_YCBCR_MODE |
  351. BF_PXP_CSC1_COEF0_C0(0x100) | /* 1.0000 (+0.00 %) */
  352. BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
  353. BF_PXP_CSC1_COEF0_Y_OFFSET(0),
  354. BF_PXP_CSC1_COEF1_C1(0x193) | /* 1.5742 (-0.06 %) */
  355. BF_PXP_CSC1_COEF1_C4(0x1db), /* 1.8555 (-0.01 %) */
  356. BF_PXP_CSC1_COEF2_C2(0x789) | /* -0.4648 (+0.33 %) */
  357. BF_PXP_CSC1_COEF2_C3(0x7d1), /* -0.1836 (+0.37 %) */
  358. };
  359. /*
  360. * BT.2020 limited range:
  361. *
  362. * |R| |1.1644 0.0000 1.6787| |Y - 16 |
  363. * |G| = |1.1644 -0.1874 -0.6505| * |Cb - 128|
  364. * |B| |1.1644 2.1418 0.0000| |Cr - 128|
  365. */
  366. static const u32 csc1_coef_bt2020_lim[3] = {
  367. BM_PXP_CSC1_COEF0_YCBCR_MODE |
  368. BF_PXP_CSC1_COEF0_C0(0x12a) | /* 1.1641 (-0.03 %) */
  369. BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
  370. BF_PXP_CSC1_COEF0_Y_OFFSET(-16),
  371. BF_PXP_CSC1_COEF1_C1(0x1ad) | /* 1.6758 (-0.29 %) */
  372. BF_PXP_CSC1_COEF1_C4(0x224), /* 2.1406 (-0.11 %) */
  373. BF_PXP_CSC1_COEF2_C2(0x75a) | /* -0.6484 (+0.20 %) */
  374. BF_PXP_CSC1_COEF2_C3(0x7d1), /* -0.1836 (+0.38 %) */
  375. };
  376. /*
  377. * BT.2020 full range:
  378. *
  379. * |R| |1.0000 0.0000 1.4746| |Y + 0 |
  380. * |G| = |1.0000 -0.1646 -0.5714| * |Cb - 128|
  381. * |B| |1.0000 1.8814 0.0000| |Cr - 128|
  382. */
  383. static const u32 csc1_coef_bt2020_full[3] = {
  384. BM_PXP_CSC1_COEF0_YCBCR_MODE |
  385. BF_PXP_CSC1_COEF0_C0(0x100) | /* 1.0000 (+0.00 %) */
  386. BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
  387. BF_PXP_CSC1_COEF0_Y_OFFSET(0),
  388. BF_PXP_CSC1_COEF1_C1(0x179) | /* 1.4727 (-0.19 %) */
  389. BF_PXP_CSC1_COEF1_C4(0x1e1), /* 1.8789 (-0.25 %) */
  390. BF_PXP_CSC1_COEF2_C2(0x76e) | /* -0.5703 (+0.11 %) */
  391. BF_PXP_CSC1_COEF2_C3(0x7d6), /* -0.1641 (+0.05 %) */
  392. };
  393. /*
  394. * SMPTE 240m limited range:
  395. *
  396. * |R| |1.1644 0.0000 1.7937| |Y - 16 |
  397. * |G| = |1.1644 -0.2565 -0.5427| * |Cb - 128|
  398. * |B| |1.1644 2.0798 0.0000| |Cr - 128|
  399. */
  400. static const u32 csc1_coef_smpte240m_lim[3] = {
  401. BM_PXP_CSC1_COEF0_YCBCR_MODE |
  402. BF_PXP_CSC1_COEF0_C0(0x12a) | /* 1.1641 (-0.03 %) */
  403. BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
  404. BF_PXP_CSC1_COEF0_Y_OFFSET(-16),
  405. BF_PXP_CSC1_COEF1_C1(0x1cb) | /* 1.7930 (-0.07 %) */
  406. BF_PXP_CSC1_COEF1_C4(0x214), /* 2.0781 (-0.17 %) */
  407. BF_PXP_CSC1_COEF2_C2(0x776) | /* -0.5391 (+0.36 %) */
  408. BF_PXP_CSC1_COEF2_C3(0x7bf), /* -0.2539 (+0.26 %) */
  409. };
  410. /*
  411. * SMPTE 240m full range:
  412. *
  413. * |R| |1.0000 0.0000 1.5756| |Y + 0 |
  414. * |G| = |1.0000 -0.2253 -0.4767| * |Cb - 128|
  415. * |B| |1.0000 1.8270 0.0000| |Cr - 128|
  416. */
  417. static const u32 csc1_coef_smpte240m_full[3] = {
  418. BM_PXP_CSC1_COEF0_YCBCR_MODE |
  419. BF_PXP_CSC1_COEF0_C0(0x100) | /* 1.0000 (+0.00 %) */
  420. BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
  421. BF_PXP_CSC1_COEF0_Y_OFFSET(0),
  422. BF_PXP_CSC1_COEF1_C1(0x193) | /* 1.5742 (-0.14 %) */
  423. BF_PXP_CSC1_COEF1_C4(0x1d3), /* 1.8242 (-0.28 %) */
  424. BF_PXP_CSC1_COEF2_C2(0x786) | /* -0.4766 (+0.01 %) */
  425. BF_PXP_CSC1_COEF2_C3(0x7c7), /* -0.2227 (+0.26 %) */
  426. };
  427. const u32 *csc1_coef;
  428. ycbcr_enc = ctx->q_data[V4L2_M2M_SRC].ycbcr_enc;
  429. quantization = ctx->q_data[V4L2_M2M_SRC].quant;
  430. if (ycbcr_enc == V4L2_YCBCR_ENC_601) {
  431. if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
  432. csc1_coef = csc1_coef_bt601_full;
  433. else
  434. csc1_coef = csc1_coef_bt601_lim;
  435. } else if (ycbcr_enc == V4L2_YCBCR_ENC_709) {
  436. if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
  437. csc1_coef = csc1_coef_rec709_full;
  438. else
  439. csc1_coef = csc1_coef_rec709_lim;
  440. } else if (ycbcr_enc == V4L2_YCBCR_ENC_BT2020) {
  441. if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
  442. csc1_coef = csc1_coef_bt2020_full;
  443. else
  444. csc1_coef = csc1_coef_bt2020_lim;
  445. } else {
  446. if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
  447. csc1_coef = csc1_coef_smpte240m_full;
  448. else
  449. csc1_coef = csc1_coef_smpte240m_lim;
  450. }
  451. writel(csc1_coef[0], dev->mmio + HW_PXP_CSC1_COEF0);
  452. writel(csc1_coef[1], dev->mmio + HW_PXP_CSC1_COEF1);
  453. writel(csc1_coef[2], dev->mmio + HW_PXP_CSC1_COEF2);
  454. } else {
  455. writel(BM_PXP_CSC1_COEF0_BYPASS, dev->mmio + HW_PXP_CSC1_COEF0);
  456. }
  457. if (!pxp_v4l2_pix_fmt_is_yuv(ctx->q_data[V4L2_M2M_SRC].fmt->fourcc) &&
  458. pxp_v4l2_pix_fmt_is_yuv(ctx->q_data[V4L2_M2M_DST].fmt->fourcc)) {
  459. /*
  460. * CSC2 RGB to YUV/YCbCr conversion is implemented as follows:
  461. *
  462. * |Y | |A1 A2 A3| |R| |D1|
  463. * |Cb| = |B1 B2 B3| * |G| + |D2|
  464. * |Cr| |C1 C2 C3| |B| |D3|
  465. *
  466. * Results are clamped to 0..255.
  467. *
  468. * BT.601 limited range:
  469. *
  470. * |Y | | 0.2568 0.5041 0.0979| |R| |16 |
  471. * |Cb| = |-0.1482 -0.2910 0.4392| * |G| + |128|
  472. * |Cr| | 0.4392 0.4392 -0.3678| |B| |128|
  473. */
  474. static const u32 csc2_coef_bt601_lim[6] = {
  475. BF_PXP_CSC2_COEF0_A2(0x081) | /* 0.5039 (-0.02 %) */
  476. BF_PXP_CSC2_COEF0_A1(0x041), /* 0.2539 (-0.29 %) */
  477. BF_PXP_CSC2_COEF1_B1(0x7db) | /* -0.1445 (+0.37 %) */
  478. BF_PXP_CSC2_COEF1_A3(0x019), /* 0.0977 (-0.02 %) */
  479. BF_PXP_CSC2_COEF2_B3(0x070) | /* 0.4375 (-0.17 %) */
  480. BF_PXP_CSC2_COEF2_B2(0x7b6), /* -0.2891 (+0.20 %) */
  481. BF_PXP_CSC2_COEF3_C2(0x7a2) | /* -0.3672 (+0.06 %) */
  482. BF_PXP_CSC2_COEF3_C1(0x070), /* 0.4375 (-0.17 %) */
  483. BF_PXP_CSC2_COEF4_D1(16) |
  484. BF_PXP_CSC2_COEF4_C3(0x7ee), /* -0.0703 (+0.11 %) */
  485. BF_PXP_CSC2_COEF5_D3(128) |
  486. BF_PXP_CSC2_COEF5_D2(128),
  487. };
  488. /*
  489. * BT.601 full range:
  490. *
  491. * |Y | | 0.2990 0.5870 0.1140| |R| |0 |
  492. * |Cb| = |-0.1687 -0.3313 0.5000| * |G| + |128|
  493. * |Cr| | 0.5000 0.5000 -0.4187| |B| |128|
  494. */
  495. static const u32 csc2_coef_bt601_full[6] = {
  496. BF_PXP_CSC2_COEF0_A2(0x096) | /* 0.5859 (-0.11 %) */
  497. BF_PXP_CSC2_COEF0_A1(0x04c), /* 0.2969 (-0.21 %) */
  498. BF_PXP_CSC2_COEF1_B1(0x7d5) | /* -0.1680 (+0.07 %) */
  499. BF_PXP_CSC2_COEF1_A3(0x01d), /* 0.1133 (-0.07 %) */
  500. BF_PXP_CSC2_COEF2_B3(0x080) | /* 0.5000 (+0.00 %) */
  501. BF_PXP_CSC2_COEF2_B2(0x7ac), /* -0.3281 (+0.32 %) */
  502. BF_PXP_CSC2_COEF3_C2(0x795) | /* -0.4180 (+0.07 %) */
  503. BF_PXP_CSC2_COEF3_C1(0x080), /* 0.5000 (+0.00 %) */
  504. BF_PXP_CSC2_COEF4_D1(0) |
  505. BF_PXP_CSC2_COEF4_C3(0x7ec), /* -0.0781 (+0.32 %) */
  506. BF_PXP_CSC2_COEF5_D3(128) |
  507. BF_PXP_CSC2_COEF5_D2(128),
  508. };
  509. /*
  510. * Rec.709 limited range:
  511. *
  512. * |Y | | 0.1826 0.6142 0.0620| |R| |16 |
  513. * |Cb| = |-0.1007 -0.3385 0.4392| * |G| + |128|
  514. * |Cr| | 0.4392 0.4392 -0.3990| |B| |128|
  515. */
  516. static const u32 csc2_coef_rec709_lim[6] = {
  517. BF_PXP_CSC2_COEF0_A2(0x09d) | /* 0.6133 (-0.09 %) */
  518. BF_PXP_CSC2_COEF0_A1(0x02e), /* 0.1797 (-0.29 %) */
  519. BF_PXP_CSC2_COEF1_B1(0x7e7) | /* -0.0977 (+0.30 %) */
  520. BF_PXP_CSC2_COEF1_A3(0x00f), /* 0.0586 (-0.34 %) */
  521. BF_PXP_CSC2_COEF2_B3(0x070) | /* 0.4375 (-0.17 %) */
  522. BF_PXP_CSC2_COEF2_B2(0x7aa), /* -0.3359 (+0.26 %) */
  523. BF_PXP_CSC2_COEF3_C2(0x79a) | /* -0.3984 (+0.05 %) */
  524. BF_PXP_CSC2_COEF3_C1(0x070), /* 0.4375 (-0.17 %) */
  525. BF_PXP_CSC2_COEF4_D1(16) |
  526. BF_PXP_CSC2_COEF4_C3(0x7f6), /* -0.0391 (+0.12 %) */
  527. BF_PXP_CSC2_COEF5_D3(128) |
  528. BF_PXP_CSC2_COEF5_D2(128),
  529. };
  530. /*
  531. * Rec.709 full range:
  532. *
  533. * |Y | | 0.2126 0.7152 0.0722| |R| |0 |
  534. * |Cb| = |-0.1146 -0.3854 0.5000| * |G| + |128|
  535. * |Cr| | 0.5000 0.5000 -0.4542| |B| |128|
  536. */
  537. static const u32 csc2_coef_rec709_full[6] = {
  538. BF_PXP_CSC2_COEF0_A2(0x0b7) | /* 0.7148 (-0.04 %) */
  539. BF_PXP_CSC2_COEF0_A1(0x036), /* 0.2109 (-0.17 %) */
  540. BF_PXP_CSC2_COEF1_B1(0x7e3) | /* -0.1133 (+0.13 %) */
  541. BF_PXP_CSC2_COEF1_A3(0x012), /* 0.0703 (-0.19 %) */
  542. BF_PXP_CSC2_COEF2_B3(0x080) | /* 0.5000 (+0.00 %) */
  543. BF_PXP_CSC2_COEF2_B2(0x79e), /* -0.3828 (+0.26 %) */
  544. BF_PXP_CSC2_COEF3_C2(0x78c) | /* -0.4531 (+0.11 %) */
  545. BF_PXP_CSC2_COEF3_C1(0x080), /* 0.5000 (+0.00 %) */
  546. BF_PXP_CSC2_COEF4_D1(0) |
  547. BF_PXP_CSC2_COEF4_C3(0x7f5), /* -0.0430 (+0.28 %) */
  548. BF_PXP_CSC2_COEF5_D3(128) |
  549. BF_PXP_CSC2_COEF5_D2(128),
  550. };
  551. /*
  552. * BT.2020 limited range:
  553. *
  554. * |Y | | 0.2256 0.5823 0.0509| |R| |16 |
  555. * |Cb| = |-0.1226 -0.3166 0.4392| * |G| + |128|
  556. * |Cr| | 0.4392 0.4392 -0.4039| |B| |128|
  557. */
  558. static const u32 csc2_coef_bt2020_lim[6] = {
  559. BF_PXP_CSC2_COEF0_A2(0x095) | /* 0.5820 (-0.03 %) */
  560. BF_PXP_CSC2_COEF0_A1(0x039), /* 0.2227 (-0.30 %) */
  561. BF_PXP_CSC2_COEF1_B1(0x7e1) | /* -0.1211 (+0.15 %) */
  562. BF_PXP_CSC2_COEF1_A3(0x00d), /* 0.0508 (-0.01 %) */
  563. BF_PXP_CSC2_COEF2_B3(0x070) | /* 0.4375 (-0.17 %) */
  564. BF_PXP_CSC2_COEF2_B2(0x7af), /* -0.3164 (+0.02 %) */
  565. BF_PXP_CSC2_COEF3_C2(0x799) | /* -0.4023 (+0.16 %) */
  566. BF_PXP_CSC2_COEF3_C1(0x070), /* 0.4375 (-0.17 %) */
  567. BF_PXP_CSC2_COEF4_D1(16) |
  568. BF_PXP_CSC2_COEF4_C3(0x7f7), /* -0.0352 (+0.02 %) */
  569. BF_PXP_CSC2_COEF5_D3(128) |
  570. BF_PXP_CSC2_COEF5_D2(128),
  571. };
  572. /*
  573. * BT.2020 full range:
  574. *
  575. * |Y | | 0.2627 0.6780 0.0593| |R| |0 |
  576. * |Cb| = |-0.1396 -0.3604 0.5000| * |G| + |128|
  577. * |Cr| | 0.5000 0.5000 -0.4598| |B| |128|
  578. */
  579. static const u32 csc2_coef_bt2020_full[6] = {
  580. BF_PXP_CSC2_COEF0_A2(0x0ad) | /* 0.6758 (-0.22 %) */
  581. BF_PXP_CSC2_COEF0_A1(0x043), /* 0.2617 (-0.10 %) */
  582. BF_PXP_CSC2_COEF1_B1(0x7dd) | /* -0.1367 (+0.29 %) */
  583. BF_PXP_CSC2_COEF1_A3(0x00f), /* 0.0586 (-0.07 %) */
  584. BF_PXP_CSC2_COEF2_B3(0x080) | /* 0.5000 (+0.00 %) */
  585. BF_PXP_CSC2_COEF2_B2(0x7a4), /* -0.3594 (+0.10 %) */
  586. BF_PXP_CSC2_COEF3_C2(0x78b) | /* -0.4570 (+0.28 %) */
  587. BF_PXP_CSC2_COEF3_C1(0x080), /* 0.5000 (+0.00 %) */
  588. BF_PXP_CSC2_COEF4_D1(0) |
  589. BF_PXP_CSC2_COEF4_C3(0x7f6), /* -0.0391 (+0.11 %) */
  590. BF_PXP_CSC2_COEF5_D3(128) |
  591. BF_PXP_CSC2_COEF5_D2(128),
  592. };
  593. /*
  594. * SMPTE 240m limited range:
  595. *
  596. * |Y | | 0.1821 0.6020 0.0747| |R| |16 |
  597. * |Cb| = |-0.1019 -0.3373 0.4392| * |G| + |128|
  598. * |Cr| | 0.4392 0.4392 -0.3909| |B| |128|
  599. */
  600. static const u32 csc2_coef_smpte240m_lim[6] = {
  601. BF_PXP_CSC2_COEF0_A2(0x09a) | /* 0.6016 (-0.05 %) */
  602. BF_PXP_CSC2_COEF0_A1(0x02e), /* 0.1797 (-0.24 %) */
  603. BF_PXP_CSC2_COEF1_B1(0x7e6) | /* -0.1016 (+0.03 %) */
  604. BF_PXP_CSC2_COEF1_A3(0x013), /* 0.0742 (-0.05 %) */
  605. BF_PXP_CSC2_COEF2_B3(0x070) | /* 0.4375 (-0.17 %) */
  606. BF_PXP_CSC2_COEF2_B2(0x7aa), /* -0.3359 (+0.14 %) */
  607. BF_PXP_CSC2_COEF3_C2(0x79c) | /* -0.3906 (+0.03 %) */
  608. BF_PXP_CSC2_COEF3_C1(0x070), /* 0.4375 (-0.17 %) */
  609. BF_PXP_CSC2_COEF4_D1(16) |
  610. BF_PXP_CSC2_COEF4_C3(0x7f4), /* -0.0469 (+0.14 %) */
  611. BF_PXP_CSC2_COEF5_D3(128) |
  612. BF_PXP_CSC2_COEF5_D2(128),
  613. };
  614. /*
  615. * SMPTE 240m full range:
  616. *
  617. * |Y | | 0.2120 0.7010 0.0870| |R| |0 |
  618. * |Cb| = |-0.1160 -0.3840 0.5000| * |G| + |128|
  619. * |Cr| | 0.5000 0.5000 -0.4450| |B| |128|
  620. */
  621. static const u32 csc2_coef_smpte240m_full[6] = {
  622. BF_PXP_CSC2_COEF0_A2(0x0b3) | /* 0.6992 (-0.18 %) */
  623. BF_PXP_CSC2_COEF0_A1(0x036), /* 0.2109 (-0.11 %) */
  624. BF_PXP_CSC2_COEF1_B1(0x7e3) | /* -0.1133 (+0.27 %) */
  625. BF_PXP_CSC2_COEF1_A3(0x016), /* 0.0859 (-0.11 %) */
  626. BF_PXP_CSC2_COEF2_B3(0x080) | /* 0.5000 (+0.00 %) */
  627. BF_PXP_CSC2_COEF2_B2(0x79e), /* -0.3828 (+0.12 %) */
  628. BF_PXP_CSC2_COEF3_C2(0x78f) | /* -0.4414 (+0.36 %) */
  629. BF_PXP_CSC2_COEF3_C1(0x080), /* 0.5000 (+0.00 %) */
  630. BF_PXP_CSC2_COEF4_D1(0) |
  631. BF_PXP_CSC2_COEF4_C3(0x7f2), /* -0.0547 (+0.03 %) */
  632. BF_PXP_CSC2_COEF5_D3(128) |
  633. BF_PXP_CSC2_COEF5_D2(128),
  634. };
  635. const u32 *csc2_coef;
  636. u32 csc2_ctrl;
  637. ycbcr_enc = ctx->q_data[V4L2_M2M_DST].ycbcr_enc;
  638. quantization = ctx->q_data[V4L2_M2M_DST].quant;
  639. if (ycbcr_enc == V4L2_YCBCR_ENC_601) {
  640. if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
  641. csc2_coef = csc2_coef_bt601_full;
  642. else
  643. csc2_coef = csc2_coef_bt601_lim;
  644. } else if (ycbcr_enc == V4L2_YCBCR_ENC_709) {
  645. if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
  646. csc2_coef = csc2_coef_rec709_full;
  647. else
  648. csc2_coef = csc2_coef_rec709_lim;
  649. } else if (ycbcr_enc == V4L2_YCBCR_ENC_BT2020) {
  650. if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
  651. csc2_coef = csc2_coef_bt2020_full;
  652. else
  653. csc2_coef = csc2_coef_bt2020_lim;
  654. } else {
  655. if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
  656. csc2_coef = csc2_coef_smpte240m_full;
  657. else
  658. csc2_coef = csc2_coef_smpte240m_lim;
  659. }
  660. if (quantization == V4L2_QUANTIZATION_FULL_RANGE) {
  661. csc2_ctrl = BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YUV <<
  662. BP_PXP_CSC2_CTRL_CSC_MODE;
  663. } else {
  664. csc2_ctrl = BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YCbCr <<
  665. BP_PXP_CSC2_CTRL_CSC_MODE;
  666. }
  667. writel(csc2_ctrl, dev->mmio + HW_PXP_CSC2_CTRL);
  668. writel(csc2_coef[0], dev->mmio + HW_PXP_CSC2_COEF0);
  669. writel(csc2_coef[1], dev->mmio + HW_PXP_CSC2_COEF1);
  670. writel(csc2_coef[2], dev->mmio + HW_PXP_CSC2_COEF2);
  671. writel(csc2_coef[3], dev->mmio + HW_PXP_CSC2_COEF3);
  672. writel(csc2_coef[4], dev->mmio + HW_PXP_CSC2_COEF4);
  673. writel(csc2_coef[5], dev->mmio + HW_PXP_CSC2_COEF5);
  674. } else {
  675. writel(BM_PXP_CSC2_CTRL_BYPASS, dev->mmio + HW_PXP_CSC2_CTRL);
  676. }
  677. }
  678. static int pxp_start(struct pxp_ctx *ctx, struct vb2_v4l2_buffer *in_vb,
  679. struct vb2_v4l2_buffer *out_vb)
  680. {
  681. struct pxp_dev *dev = ctx->dev;
  682. struct pxp_q_data *q_data;
  683. u32 src_width, src_height, src_stride, src_fourcc;
  684. u32 dst_width, dst_height, dst_stride, dst_fourcc;
  685. dma_addr_t p_in, p_out;
  686. u32 ctrl, out_ctrl, out_buf, out_buf2, out_pitch, out_lrc, out_ps_ulc;
  687. u32 out_ps_lrc;
  688. u32 ps_ctrl, ps_buf, ps_ubuf, ps_vbuf, ps_pitch, ps_scale, ps_offset;
  689. u32 as_ulc, as_lrc;
  690. u32 y_size;
  691. u32 decx, decy, xscale, yscale;
  692. q_data = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  693. src_width = ctx->q_data[V4L2_M2M_SRC].width;
  694. dst_width = ctx->q_data[V4L2_M2M_DST].width;
  695. src_height = ctx->q_data[V4L2_M2M_SRC].height;
  696. dst_height = ctx->q_data[V4L2_M2M_DST].height;
  697. src_stride = ctx->q_data[V4L2_M2M_SRC].bytesperline;
  698. dst_stride = ctx->q_data[V4L2_M2M_DST].bytesperline;
  699. src_fourcc = ctx->q_data[V4L2_M2M_SRC].fmt->fourcc;
  700. dst_fourcc = ctx->q_data[V4L2_M2M_DST].fmt->fourcc;
  701. p_in = vb2_dma_contig_plane_dma_addr(&in_vb->vb2_buf, 0);
  702. p_out = vb2_dma_contig_plane_dma_addr(&out_vb->vb2_buf, 0);
  703. if (!p_in || !p_out) {
  704. v4l2_err(&dev->v4l2_dev,
  705. "Acquiring DMA addresses of buffers failed\n");
  706. return -EFAULT;
  707. }
  708. out_vb->sequence =
  709. get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE)->sequence++;
  710. in_vb->sequence = q_data->sequence++;
  711. out_vb->vb2_buf.timestamp = in_vb->vb2_buf.timestamp;
  712. if (in_vb->flags & V4L2_BUF_FLAG_TIMECODE)
  713. out_vb->timecode = in_vb->timecode;
  714. out_vb->field = in_vb->field;
  715. out_vb->flags = in_vb->flags &
  716. (V4L2_BUF_FLAG_TIMECODE |
  717. V4L2_BUF_FLAG_KEYFRAME |
  718. V4L2_BUF_FLAG_PFRAME |
  719. V4L2_BUF_FLAG_BFRAME |
  720. V4L2_BUF_FLAG_TSTAMP_SRC_MASK);
  721. /* Rotation disabled, 8x8 block size */
  722. ctrl = BF_PXP_CTRL_VFLIP0(!!(ctx->mode & MEM2MEM_VFLIP)) |
  723. BF_PXP_CTRL_HFLIP0(!!(ctx->mode & MEM2MEM_HFLIP));
  724. /* Always write alpha value as V4L2_CID_ALPHA_COMPONENT */
  725. out_ctrl = BF_PXP_OUT_CTRL_ALPHA(ctx->alpha_component) |
  726. BF_PXP_OUT_CTRL_ALPHA_OUTPUT(1) |
  727. pxp_v4l2_pix_fmt_to_out_format(dst_fourcc);
  728. out_buf = p_out;
  729. switch (dst_fourcc) {
  730. case V4L2_PIX_FMT_NV12:
  731. case V4L2_PIX_FMT_NV21:
  732. case V4L2_PIX_FMT_NV16:
  733. case V4L2_PIX_FMT_NV61:
  734. out_buf2 = out_buf + dst_stride * dst_height;
  735. break;
  736. default:
  737. out_buf2 = 0;
  738. }
  739. out_pitch = BF_PXP_OUT_PITCH_PITCH(dst_stride);
  740. out_lrc = BF_PXP_OUT_LRC_X(dst_width - 1) |
  741. BF_PXP_OUT_LRC_Y(dst_height - 1);
  742. /* PS covers whole output */
  743. out_ps_ulc = BF_PXP_OUT_PS_ULC_X(0) | BF_PXP_OUT_PS_ULC_Y(0);
  744. out_ps_lrc = BF_PXP_OUT_PS_LRC_X(dst_width - 1) |
  745. BF_PXP_OUT_PS_LRC_Y(dst_height - 1);
  746. /* no AS */
  747. as_ulc = BF_PXP_OUT_AS_ULC_X(1) | BF_PXP_OUT_AS_ULC_Y(1);
  748. as_lrc = BF_PXP_OUT_AS_LRC_X(0) | BF_PXP_OUT_AS_LRC_Y(0);
  749. decx = (src_width <= dst_width) ? 0 : ilog2(src_width / dst_width);
  750. decy = (src_height <= dst_height) ? 0 : ilog2(src_height / dst_height);
  751. ps_ctrl = BF_PXP_PS_CTRL_DECX(decx) | BF_PXP_PS_CTRL_DECY(decy) |
  752. pxp_v4l2_pix_fmt_to_ps_format(src_fourcc);
  753. ps_buf = p_in;
  754. y_size = src_stride * src_height;
  755. switch (src_fourcc) {
  756. case V4L2_PIX_FMT_YUV420:
  757. ps_ubuf = ps_buf + y_size;
  758. ps_vbuf = ps_ubuf + y_size / 4;
  759. break;
  760. case V4L2_PIX_FMT_YUV422P:
  761. ps_ubuf = ps_buf + y_size;
  762. ps_vbuf = ps_ubuf + y_size / 2;
  763. break;
  764. case V4L2_PIX_FMT_NV12:
  765. case V4L2_PIX_FMT_NV21:
  766. case V4L2_PIX_FMT_NV16:
  767. case V4L2_PIX_FMT_NV61:
  768. ps_ubuf = ps_buf + y_size;
  769. ps_vbuf = 0;
  770. break;
  771. case V4L2_PIX_FMT_GREY:
  772. case V4L2_PIX_FMT_Y4:
  773. ps_ubuf = 0;
  774. /* In grayscale mode, ps_vbuf contents are reused as CbCr */
  775. ps_vbuf = 0x8080;
  776. break;
  777. default:
  778. ps_ubuf = 0;
  779. ps_vbuf = 0;
  780. break;
  781. }
  782. ps_pitch = BF_PXP_PS_PITCH_PITCH(src_stride);
  783. if (decx) {
  784. xscale = (src_width >> decx) * 0x1000 / dst_width;
  785. } else {
  786. switch (src_fourcc) {
  787. case V4L2_PIX_FMT_UYVY:
  788. case V4L2_PIX_FMT_YUYV:
  789. case V4L2_PIX_FMT_VYUY:
  790. case V4L2_PIX_FMT_YVYU:
  791. case V4L2_PIX_FMT_NV16:
  792. case V4L2_PIX_FMT_NV12:
  793. case V4L2_PIX_FMT_NV21:
  794. case V4L2_PIX_FMT_NV61:
  795. case V4L2_PIX_FMT_YUV422P:
  796. case V4L2_PIX_FMT_YUV420:
  797. /*
  798. * This avoids sampling past the right edge for
  799. * horizontally chroma subsampled formats.
  800. */
  801. xscale = (src_width - 2) * 0x1000 / (dst_width - 1);
  802. break;
  803. default:
  804. xscale = (src_width - 1) * 0x1000 / (dst_width - 1);
  805. break;
  806. }
  807. }
  808. if (decy)
  809. yscale = (src_height >> decy) * 0x1000 / dst_height;
  810. else
  811. yscale = (src_height - 1) * 0x1000 / (dst_height - 1);
  812. ps_scale = BF_PXP_PS_SCALE_YSCALE(yscale) |
  813. BF_PXP_PS_SCALE_XSCALE(xscale);
  814. ps_offset = BF_PXP_PS_OFFSET_YOFFSET(0) | BF_PXP_PS_OFFSET_XOFFSET(0);
  815. writel(ctrl, dev->mmio + HW_PXP_CTRL);
  816. /* skip STAT */
  817. writel(out_ctrl, dev->mmio + HW_PXP_OUT_CTRL);
  818. writel(out_buf, dev->mmio + HW_PXP_OUT_BUF);
  819. writel(out_buf2, dev->mmio + HW_PXP_OUT_BUF2);
  820. writel(out_pitch, dev->mmio + HW_PXP_OUT_PITCH);
  821. writel(out_lrc, dev->mmio + HW_PXP_OUT_LRC);
  822. writel(out_ps_ulc, dev->mmio + HW_PXP_OUT_PS_ULC);
  823. writel(out_ps_lrc, dev->mmio + HW_PXP_OUT_PS_LRC);
  824. writel(as_ulc, dev->mmio + HW_PXP_OUT_AS_ULC);
  825. writel(as_lrc, dev->mmio + HW_PXP_OUT_AS_LRC);
  826. writel(ps_ctrl, dev->mmio + HW_PXP_PS_CTRL);
  827. writel(ps_buf, dev->mmio + HW_PXP_PS_BUF);
  828. writel(ps_ubuf, dev->mmio + HW_PXP_PS_UBUF);
  829. writel(ps_vbuf, dev->mmio + HW_PXP_PS_VBUF);
  830. writel(ps_pitch, dev->mmio + HW_PXP_PS_PITCH);
  831. writel(0x00ffffff, dev->mmio + HW_PXP_PS_BACKGROUND_0);
  832. writel(ps_scale, dev->mmio + HW_PXP_PS_SCALE);
  833. writel(ps_offset, dev->mmio + HW_PXP_PS_OFFSET);
  834. /* disable processed surface color keying */
  835. writel(0x00ffffff, dev->mmio + HW_PXP_PS_CLRKEYLOW_0);
  836. writel(0x00000000, dev->mmio + HW_PXP_PS_CLRKEYHIGH_0);
  837. /* disable alpha surface color keying */
  838. writel(0x00ffffff, dev->mmio + HW_PXP_AS_CLRKEYLOW_0);
  839. writel(0x00000000, dev->mmio + HW_PXP_AS_CLRKEYHIGH_0);
  840. /* setup CSC */
  841. pxp_setup_csc(ctx);
  842. /* bypass LUT */
  843. writel(BM_PXP_LUT_CTRL_BYPASS, dev->mmio + HW_PXP_LUT_CTRL);
  844. writel(BF_PXP_DATA_PATH_CTRL0_MUX15_SEL(0)|
  845. BF_PXP_DATA_PATH_CTRL0_MUX14_SEL(1)|
  846. BF_PXP_DATA_PATH_CTRL0_MUX13_SEL(0)|
  847. BF_PXP_DATA_PATH_CTRL0_MUX12_SEL(0)|
  848. BF_PXP_DATA_PATH_CTRL0_MUX11_SEL(0)|
  849. BF_PXP_DATA_PATH_CTRL0_MUX10_SEL(0)|
  850. BF_PXP_DATA_PATH_CTRL0_MUX9_SEL(1)|
  851. BF_PXP_DATA_PATH_CTRL0_MUX8_SEL(0)|
  852. BF_PXP_DATA_PATH_CTRL0_MUX7_SEL(0)|
  853. BF_PXP_DATA_PATH_CTRL0_MUX6_SEL(0)|
  854. BF_PXP_DATA_PATH_CTRL0_MUX5_SEL(0)|
  855. BF_PXP_DATA_PATH_CTRL0_MUX4_SEL(0)|
  856. BF_PXP_DATA_PATH_CTRL0_MUX3_SEL(0)|
  857. BF_PXP_DATA_PATH_CTRL0_MUX2_SEL(0)|
  858. BF_PXP_DATA_PATH_CTRL0_MUX1_SEL(0)|
  859. BF_PXP_DATA_PATH_CTRL0_MUX0_SEL(0),
  860. dev->mmio + HW_PXP_DATA_PATH_CTRL0);
  861. writel(BF_PXP_DATA_PATH_CTRL1_MUX17_SEL(1) |
  862. BF_PXP_DATA_PATH_CTRL1_MUX16_SEL(1),
  863. dev->mmio + HW_PXP_DATA_PATH_CTRL1);
  864. writel(0xffff, dev->mmio + HW_PXP_IRQ_MASK);
  865. /* ungate, enable PS/AS/OUT and PXP operation */
  866. writel(BM_PXP_CTRL_IRQ_ENABLE, dev->mmio + HW_PXP_CTRL_SET);
  867. writel(BM_PXP_CTRL_ENABLE | BM_PXP_CTRL_ENABLE_CSC2 |
  868. BM_PXP_CTRL_ENABLE_LUT | BM_PXP_CTRL_ENABLE_ROTATE0 |
  869. BM_PXP_CTRL_ENABLE_PS_AS_OUT, dev->mmio + HW_PXP_CTRL_SET);
  870. return 0;
  871. }
  872. static void pxp_job_finish(struct pxp_dev *dev)
  873. {
  874. struct pxp_ctx *curr_ctx;
  875. struct vb2_v4l2_buffer *src_vb, *dst_vb;
  876. unsigned long flags;
  877. curr_ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
  878. if (curr_ctx == NULL) {
  879. pr_err("Instance released before the end of transaction\n");
  880. return;
  881. }
  882. src_vb = v4l2_m2m_src_buf_remove(curr_ctx->fh.m2m_ctx);
  883. dst_vb = v4l2_m2m_dst_buf_remove(curr_ctx->fh.m2m_ctx);
  884. spin_lock_irqsave(&dev->irqlock, flags);
  885. v4l2_m2m_buf_done(src_vb, VB2_BUF_STATE_DONE);
  886. v4l2_m2m_buf_done(dst_vb, VB2_BUF_STATE_DONE);
  887. spin_unlock_irqrestore(&dev->irqlock, flags);
  888. dprintk(curr_ctx->dev, "Finishing transaction\n");
  889. v4l2_m2m_job_finish(dev->m2m_dev, curr_ctx->fh.m2m_ctx);
  890. }
  891. /*
  892. * mem2mem callbacks
  893. */
  894. static void pxp_device_run(void *priv)
  895. {
  896. struct pxp_ctx *ctx = priv;
  897. struct vb2_v4l2_buffer *src_buf, *dst_buf;
  898. src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
  899. dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  900. pxp_start(ctx, src_buf, dst_buf);
  901. }
  902. static int pxp_job_ready(void *priv)
  903. {
  904. struct pxp_ctx *ctx = priv;
  905. if (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) < 1 ||
  906. v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx) < 1) {
  907. dprintk(ctx->dev, "Not enough buffers available\n");
  908. return 0;
  909. }
  910. return 1;
  911. }
  912. static void pxp_job_abort(void *priv)
  913. {
  914. struct pxp_ctx *ctx = priv;
  915. /* Will cancel the transaction in the next interrupt handler */
  916. ctx->aborting = 1;
  917. }
  918. /*
  919. * interrupt handler
  920. */
  921. static irqreturn_t pxp_irq_handler(int irq, void *dev_id)
  922. {
  923. struct pxp_dev *dev = dev_id;
  924. u32 stat;
  925. stat = readl(dev->mmio + HW_PXP_STAT);
  926. if (stat & BM_PXP_STAT_IRQ0) {
  927. /* we expect x = 0, y = height, irq0 = 1 */
  928. if (stat & ~(BM_PXP_STAT_BLOCKX | BM_PXP_STAT_BLOCKY |
  929. BM_PXP_STAT_IRQ0))
  930. dprintk(dev, "%s: stat = 0x%08x\n", __func__, stat);
  931. writel(BM_PXP_STAT_IRQ0, dev->mmio + HW_PXP_STAT_CLR);
  932. pxp_job_finish(dev);
  933. } else {
  934. u32 irq = readl(dev->mmio + HW_PXP_IRQ);
  935. dprintk(dev, "%s: stat = 0x%08x\n", __func__, stat);
  936. dprintk(dev, "%s: irq = 0x%08x\n", __func__, irq);
  937. writel(irq, dev->mmio + HW_PXP_IRQ_CLR);
  938. }
  939. return IRQ_HANDLED;
  940. }
  941. /*
  942. * video ioctls
  943. */
  944. static int pxp_querycap(struct file *file, void *priv,
  945. struct v4l2_capability *cap)
  946. {
  947. strscpy(cap->driver, MEM2MEM_NAME, sizeof(cap->driver));
  948. strscpy(cap->card, MEM2MEM_NAME, sizeof(cap->card));
  949. snprintf(cap->bus_info, sizeof(cap->bus_info),
  950. "platform:%s", MEM2MEM_NAME);
  951. return 0;
  952. }
  953. static int pxp_enum_fmt(struct v4l2_fmtdesc *f, u32 type)
  954. {
  955. int i, num;
  956. struct pxp_fmt *fmt;
  957. num = 0;
  958. for (i = 0; i < NUM_FORMATS; ++i) {
  959. if (formats[i].types & type) {
  960. /* index-th format of type type found ? */
  961. if (num == f->index)
  962. break;
  963. /*
  964. * Correct type but haven't reached our index yet,
  965. * just increment per-type index
  966. */
  967. ++num;
  968. }
  969. }
  970. if (i < NUM_FORMATS) {
  971. /* Format found */
  972. fmt = &formats[i];
  973. f->pixelformat = fmt->fourcc;
  974. return 0;
  975. }
  976. /* Format not found */
  977. return -EINVAL;
  978. }
  979. static int pxp_enum_fmt_vid_cap(struct file *file, void *priv,
  980. struct v4l2_fmtdesc *f)
  981. {
  982. return pxp_enum_fmt(f, MEM2MEM_CAPTURE);
  983. }
  984. static int pxp_enum_fmt_vid_out(struct file *file, void *priv,
  985. struct v4l2_fmtdesc *f)
  986. {
  987. return pxp_enum_fmt(f, MEM2MEM_OUTPUT);
  988. }
  989. static int pxp_g_fmt(struct pxp_ctx *ctx, struct v4l2_format *f)
  990. {
  991. struct vb2_queue *vq;
  992. struct pxp_q_data *q_data;
  993. vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
  994. if (!vq)
  995. return -EINVAL;
  996. q_data = get_q_data(ctx, f->type);
  997. f->fmt.pix.width = q_data->width;
  998. f->fmt.pix.height = q_data->height;
  999. f->fmt.pix.field = V4L2_FIELD_NONE;
  1000. f->fmt.pix.pixelformat = q_data->fmt->fourcc;
  1001. f->fmt.pix.bytesperline = q_data->bytesperline;
  1002. f->fmt.pix.sizeimage = q_data->sizeimage;
  1003. f->fmt.pix.colorspace = ctx->colorspace;
  1004. f->fmt.pix.xfer_func = ctx->xfer_func;
  1005. f->fmt.pix.ycbcr_enc = q_data->ycbcr_enc;
  1006. f->fmt.pix.quantization = q_data->quant;
  1007. return 0;
  1008. }
  1009. static int pxp_g_fmt_vid_out(struct file *file, void *priv,
  1010. struct v4l2_format *f)
  1011. {
  1012. return pxp_g_fmt(file2ctx(file), f);
  1013. }
  1014. static int pxp_g_fmt_vid_cap(struct file *file, void *priv,
  1015. struct v4l2_format *f)
  1016. {
  1017. return pxp_g_fmt(file2ctx(file), f);
  1018. }
  1019. static inline u32 pxp_bytesperline(struct pxp_fmt *fmt, u32 width)
  1020. {
  1021. switch (fmt->fourcc) {
  1022. case V4L2_PIX_FMT_YUV420:
  1023. case V4L2_PIX_FMT_NV12:
  1024. case V4L2_PIX_FMT_NV21:
  1025. case V4L2_PIX_FMT_YUV422P:
  1026. case V4L2_PIX_FMT_NV16:
  1027. case V4L2_PIX_FMT_NV61:
  1028. return width;
  1029. default:
  1030. return (width * fmt->depth) >> 3;
  1031. }
  1032. }
  1033. static inline u32 pxp_sizeimage(struct pxp_fmt *fmt, u32 width, u32 height)
  1034. {
  1035. return (fmt->depth * width * height) >> 3;
  1036. }
  1037. static int pxp_try_fmt(struct v4l2_format *f, struct pxp_fmt *fmt)
  1038. {
  1039. v4l_bound_align_image(&f->fmt.pix.width, MIN_W, MAX_W, ALIGN_W,
  1040. &f->fmt.pix.height, MIN_H, MAX_H, ALIGN_H, 0);
  1041. f->fmt.pix.bytesperline = pxp_bytesperline(fmt, f->fmt.pix.width);
  1042. f->fmt.pix.sizeimage = pxp_sizeimage(fmt, f->fmt.pix.width,
  1043. f->fmt.pix.height);
  1044. f->fmt.pix.field = V4L2_FIELD_NONE;
  1045. return 0;
  1046. }
  1047. static void
  1048. pxp_fixup_colorimetry_cap(struct pxp_ctx *ctx, u32 dst_fourcc,
  1049. enum v4l2_ycbcr_encoding *ycbcr_enc,
  1050. enum v4l2_quantization *quantization)
  1051. {
  1052. bool dst_is_yuv = pxp_v4l2_pix_fmt_is_yuv(dst_fourcc);
  1053. if (pxp_v4l2_pix_fmt_is_yuv(ctx->q_data[V4L2_M2M_SRC].fmt->fourcc) ==
  1054. dst_is_yuv) {
  1055. /*
  1056. * There is no support for conversion between different YCbCr
  1057. * encodings or between RGB limited and full range.
  1058. */
  1059. *ycbcr_enc = ctx->q_data[V4L2_M2M_SRC].ycbcr_enc;
  1060. *quantization = ctx->q_data[V4L2_M2M_SRC].quant;
  1061. } else {
  1062. *ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(ctx->colorspace);
  1063. *quantization = V4L2_MAP_QUANTIZATION_DEFAULT(!dst_is_yuv,
  1064. ctx->colorspace,
  1065. *ycbcr_enc);
  1066. }
  1067. }
  1068. static int pxp_try_fmt_vid_cap(struct file *file, void *priv,
  1069. struct v4l2_format *f)
  1070. {
  1071. struct pxp_fmt *fmt;
  1072. struct pxp_ctx *ctx = file2ctx(file);
  1073. fmt = find_format(f);
  1074. if (!fmt) {
  1075. f->fmt.pix.pixelformat = formats[0].fourcc;
  1076. fmt = find_format(f);
  1077. }
  1078. if (!(fmt->types & MEM2MEM_CAPTURE)) {
  1079. v4l2_err(&ctx->dev->v4l2_dev,
  1080. "Fourcc format (0x%08x) invalid.\n",
  1081. f->fmt.pix.pixelformat);
  1082. return -EINVAL;
  1083. }
  1084. f->fmt.pix.colorspace = ctx->colorspace;
  1085. f->fmt.pix.xfer_func = ctx->xfer_func;
  1086. pxp_fixup_colorimetry_cap(ctx, fmt->fourcc,
  1087. &f->fmt.pix.ycbcr_enc,
  1088. &f->fmt.pix.quantization);
  1089. return pxp_try_fmt(f, fmt);
  1090. }
  1091. static int pxp_try_fmt_vid_out(struct file *file, void *priv,
  1092. struct v4l2_format *f)
  1093. {
  1094. struct pxp_fmt *fmt;
  1095. struct pxp_ctx *ctx = file2ctx(file);
  1096. fmt = find_format(f);
  1097. if (!fmt) {
  1098. f->fmt.pix.pixelformat = formats[0].fourcc;
  1099. fmt = find_format(f);
  1100. }
  1101. if (!(fmt->types & MEM2MEM_OUTPUT)) {
  1102. v4l2_err(&ctx->dev->v4l2_dev,
  1103. "Fourcc format (0x%08x) invalid.\n",
  1104. f->fmt.pix.pixelformat);
  1105. return -EINVAL;
  1106. }
  1107. if (!f->fmt.pix.colorspace)
  1108. f->fmt.pix.colorspace = V4L2_COLORSPACE_REC709;
  1109. return pxp_try_fmt(f, fmt);
  1110. }
  1111. static int pxp_s_fmt(struct pxp_ctx *ctx, struct v4l2_format *f)
  1112. {
  1113. struct pxp_q_data *q_data;
  1114. struct vb2_queue *vq;
  1115. vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
  1116. if (!vq)
  1117. return -EINVAL;
  1118. q_data = get_q_data(ctx, f->type);
  1119. if (!q_data)
  1120. return -EINVAL;
  1121. if (vb2_is_busy(vq)) {
  1122. v4l2_err(&ctx->dev->v4l2_dev, "%s queue busy\n", __func__);
  1123. return -EBUSY;
  1124. }
  1125. q_data->fmt = find_format(f);
  1126. q_data->width = f->fmt.pix.width;
  1127. q_data->height = f->fmt.pix.height;
  1128. q_data->bytesperline = f->fmt.pix.bytesperline;
  1129. q_data->sizeimage = f->fmt.pix.sizeimage;
  1130. dprintk(ctx->dev,
  1131. "Setting format for type %d, wxh: %dx%d, fmt: %d\n",
  1132. f->type, q_data->width, q_data->height, q_data->fmt->fourcc);
  1133. return 0;
  1134. }
  1135. static int pxp_s_fmt_vid_cap(struct file *file, void *priv,
  1136. struct v4l2_format *f)
  1137. {
  1138. struct pxp_ctx *ctx = file2ctx(file);
  1139. int ret;
  1140. ret = pxp_try_fmt_vid_cap(file, priv, f);
  1141. if (ret)
  1142. return ret;
  1143. ret = pxp_s_fmt(file2ctx(file), f);
  1144. if (ret)
  1145. return ret;
  1146. ctx->q_data[V4L2_M2M_DST].ycbcr_enc = f->fmt.pix.ycbcr_enc;
  1147. ctx->q_data[V4L2_M2M_DST].quant = f->fmt.pix.quantization;
  1148. return 0;
  1149. }
  1150. static int pxp_s_fmt_vid_out(struct file *file, void *priv,
  1151. struct v4l2_format *f)
  1152. {
  1153. struct pxp_ctx *ctx = file2ctx(file);
  1154. int ret;
  1155. ret = pxp_try_fmt_vid_out(file, priv, f);
  1156. if (ret)
  1157. return ret;
  1158. ret = pxp_s_fmt(file2ctx(file), f);
  1159. if (ret)
  1160. return ret;
  1161. ctx->colorspace = f->fmt.pix.colorspace;
  1162. ctx->xfer_func = f->fmt.pix.xfer_func;
  1163. ctx->q_data[V4L2_M2M_SRC].ycbcr_enc = f->fmt.pix.ycbcr_enc;
  1164. ctx->q_data[V4L2_M2M_SRC].quant = f->fmt.pix.quantization;
  1165. pxp_fixup_colorimetry_cap(ctx, ctx->q_data[V4L2_M2M_DST].fmt->fourcc,
  1166. &ctx->q_data[V4L2_M2M_DST].ycbcr_enc,
  1167. &ctx->q_data[V4L2_M2M_DST].quant);
  1168. return 0;
  1169. }
  1170. static int pxp_s_ctrl(struct v4l2_ctrl *ctrl)
  1171. {
  1172. struct pxp_ctx *ctx =
  1173. container_of(ctrl->handler, struct pxp_ctx, hdl);
  1174. switch (ctrl->id) {
  1175. case V4L2_CID_HFLIP:
  1176. if (ctrl->val)
  1177. ctx->mode |= MEM2MEM_HFLIP;
  1178. else
  1179. ctx->mode &= ~MEM2MEM_HFLIP;
  1180. break;
  1181. case V4L2_CID_VFLIP:
  1182. if (ctrl->val)
  1183. ctx->mode |= MEM2MEM_VFLIP;
  1184. else
  1185. ctx->mode &= ~MEM2MEM_VFLIP;
  1186. break;
  1187. case V4L2_CID_ALPHA_COMPONENT:
  1188. ctx->alpha_component = ctrl->val;
  1189. break;
  1190. default:
  1191. v4l2_err(&ctx->dev->v4l2_dev, "Invalid control\n");
  1192. return -EINVAL;
  1193. }
  1194. return 0;
  1195. }
  1196. static const struct v4l2_ctrl_ops pxp_ctrl_ops = {
  1197. .s_ctrl = pxp_s_ctrl,
  1198. };
  1199. static const struct v4l2_ioctl_ops pxp_ioctl_ops = {
  1200. .vidioc_querycap = pxp_querycap,
  1201. .vidioc_enum_fmt_vid_cap = pxp_enum_fmt_vid_cap,
  1202. .vidioc_g_fmt_vid_cap = pxp_g_fmt_vid_cap,
  1203. .vidioc_try_fmt_vid_cap = pxp_try_fmt_vid_cap,
  1204. .vidioc_s_fmt_vid_cap = pxp_s_fmt_vid_cap,
  1205. .vidioc_enum_fmt_vid_out = pxp_enum_fmt_vid_out,
  1206. .vidioc_g_fmt_vid_out = pxp_g_fmt_vid_out,
  1207. .vidioc_try_fmt_vid_out = pxp_try_fmt_vid_out,
  1208. .vidioc_s_fmt_vid_out = pxp_s_fmt_vid_out,
  1209. .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
  1210. .vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
  1211. .vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
  1212. .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
  1213. .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
  1214. .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
  1215. .vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
  1216. .vidioc_streamon = v4l2_m2m_ioctl_streamon,
  1217. .vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
  1218. .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
  1219. .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
  1220. };
  1221. /*
  1222. * Queue operations
  1223. */
  1224. static int pxp_queue_setup(struct vb2_queue *vq,
  1225. unsigned int *nbuffers, unsigned int *nplanes,
  1226. unsigned int sizes[], struct device *alloc_devs[])
  1227. {
  1228. struct pxp_ctx *ctx = vb2_get_drv_priv(vq);
  1229. struct pxp_q_data *q_data;
  1230. unsigned int size, count = *nbuffers;
  1231. q_data = get_q_data(ctx, vq->type);
  1232. size = q_data->sizeimage;
  1233. *nbuffers = count;
  1234. if (*nplanes)
  1235. return sizes[0] < size ? -EINVAL : 0;
  1236. *nplanes = 1;
  1237. sizes[0] = size;
  1238. dprintk(ctx->dev, "get %d buffer(s) of size %d each.\n", count, size);
  1239. return 0;
  1240. }
  1241. static int pxp_buf_prepare(struct vb2_buffer *vb)
  1242. {
  1243. struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
  1244. struct pxp_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
  1245. struct pxp_dev *dev = ctx->dev;
  1246. struct pxp_q_data *q_data;
  1247. dprintk(ctx->dev, "type: %d\n", vb->vb2_queue->type);
  1248. q_data = get_q_data(ctx, vb->vb2_queue->type);
  1249. if (V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) {
  1250. if (vbuf->field == V4L2_FIELD_ANY)
  1251. vbuf->field = V4L2_FIELD_NONE;
  1252. if (vbuf->field != V4L2_FIELD_NONE) {
  1253. dprintk(dev, "%s field isn't supported\n", __func__);
  1254. return -EINVAL;
  1255. }
  1256. }
  1257. if (vb2_plane_size(vb, 0) < q_data->sizeimage) {
  1258. dprintk(dev, "%s data will not fit into plane (%lu < %lu)\n",
  1259. __func__, vb2_plane_size(vb, 0),
  1260. (long)q_data->sizeimage);
  1261. return -EINVAL;
  1262. }
  1263. vb2_set_plane_payload(vb, 0, q_data->sizeimage);
  1264. return 0;
  1265. }
  1266. static void pxp_buf_queue(struct vb2_buffer *vb)
  1267. {
  1268. struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
  1269. struct pxp_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
  1270. v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
  1271. }
  1272. static int pxp_start_streaming(struct vb2_queue *q, unsigned int count)
  1273. {
  1274. struct pxp_ctx *ctx = vb2_get_drv_priv(q);
  1275. struct pxp_q_data *q_data = get_q_data(ctx, q->type);
  1276. q_data->sequence = 0;
  1277. return 0;
  1278. }
  1279. static void pxp_stop_streaming(struct vb2_queue *q)
  1280. {
  1281. struct pxp_ctx *ctx = vb2_get_drv_priv(q);
  1282. struct vb2_v4l2_buffer *vbuf;
  1283. unsigned long flags;
  1284. for (;;) {
  1285. if (V4L2_TYPE_IS_OUTPUT(q->type))
  1286. vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
  1287. else
  1288. vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
  1289. if (vbuf == NULL)
  1290. return;
  1291. spin_lock_irqsave(&ctx->dev->irqlock, flags);
  1292. v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR);
  1293. spin_unlock_irqrestore(&ctx->dev->irqlock, flags);
  1294. }
  1295. }
  1296. static const struct vb2_ops pxp_qops = {
  1297. .queue_setup = pxp_queue_setup,
  1298. .buf_prepare = pxp_buf_prepare,
  1299. .buf_queue = pxp_buf_queue,
  1300. .start_streaming = pxp_start_streaming,
  1301. .stop_streaming = pxp_stop_streaming,
  1302. .wait_prepare = vb2_ops_wait_prepare,
  1303. .wait_finish = vb2_ops_wait_finish,
  1304. };
  1305. static int queue_init(void *priv, struct vb2_queue *src_vq,
  1306. struct vb2_queue *dst_vq)
  1307. {
  1308. struct pxp_ctx *ctx = priv;
  1309. int ret;
  1310. src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
  1311. src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
  1312. src_vq->drv_priv = ctx;
  1313. src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
  1314. src_vq->ops = &pxp_qops;
  1315. src_vq->mem_ops = &vb2_dma_contig_memops;
  1316. src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
  1317. src_vq->lock = &ctx->dev->dev_mutex;
  1318. src_vq->dev = ctx->dev->v4l2_dev.dev;
  1319. ret = vb2_queue_init(src_vq);
  1320. if (ret)
  1321. return ret;
  1322. dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
  1323. dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
  1324. dst_vq->drv_priv = ctx;
  1325. dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
  1326. dst_vq->ops = &pxp_qops;
  1327. dst_vq->mem_ops = &vb2_dma_contig_memops;
  1328. dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
  1329. dst_vq->lock = &ctx->dev->dev_mutex;
  1330. dst_vq->dev = ctx->dev->v4l2_dev.dev;
  1331. return vb2_queue_init(dst_vq);
  1332. }
  1333. /*
  1334. * File operations
  1335. */
  1336. static int pxp_open(struct file *file)
  1337. {
  1338. struct pxp_dev *dev = video_drvdata(file);
  1339. struct pxp_ctx *ctx = NULL;
  1340. struct v4l2_ctrl_handler *hdl;
  1341. int rc = 0;
  1342. if (mutex_lock_interruptible(&dev->dev_mutex))
  1343. return -ERESTARTSYS;
  1344. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  1345. if (!ctx) {
  1346. rc = -ENOMEM;
  1347. goto open_unlock;
  1348. }
  1349. v4l2_fh_init(&ctx->fh, video_devdata(file));
  1350. file->private_data = &ctx->fh;
  1351. ctx->dev = dev;
  1352. hdl = &ctx->hdl;
  1353. v4l2_ctrl_handler_init(hdl, 4);
  1354. v4l2_ctrl_new_std(hdl, &pxp_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
  1355. v4l2_ctrl_new_std(hdl, &pxp_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
  1356. v4l2_ctrl_new_std(hdl, &pxp_ctrl_ops, V4L2_CID_ALPHA_COMPONENT,
  1357. 0, 255, 1, 255);
  1358. if (hdl->error) {
  1359. rc = hdl->error;
  1360. v4l2_ctrl_handler_free(hdl);
  1361. kfree(ctx);
  1362. goto open_unlock;
  1363. }
  1364. ctx->fh.ctrl_handler = hdl;
  1365. v4l2_ctrl_handler_setup(hdl);
  1366. ctx->q_data[V4L2_M2M_SRC].fmt = &formats[0];
  1367. ctx->q_data[V4L2_M2M_SRC].width = 640;
  1368. ctx->q_data[V4L2_M2M_SRC].height = 480;
  1369. ctx->q_data[V4L2_M2M_SRC].bytesperline =
  1370. pxp_bytesperline(&formats[0], 640);
  1371. ctx->q_data[V4L2_M2M_SRC].sizeimage =
  1372. pxp_sizeimage(&formats[0], 640, 480);
  1373. ctx->q_data[V4L2_M2M_DST] = ctx->q_data[V4L2_M2M_SRC];
  1374. ctx->colorspace = V4L2_COLORSPACE_REC709;
  1375. ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx, &queue_init);
  1376. if (IS_ERR(ctx->fh.m2m_ctx)) {
  1377. rc = PTR_ERR(ctx->fh.m2m_ctx);
  1378. v4l2_ctrl_handler_free(hdl);
  1379. v4l2_fh_exit(&ctx->fh);
  1380. kfree(ctx);
  1381. goto open_unlock;
  1382. }
  1383. v4l2_fh_add(&ctx->fh);
  1384. atomic_inc(&dev->num_inst);
  1385. dprintk(dev, "Created instance: %p, m2m_ctx: %p\n",
  1386. ctx, ctx->fh.m2m_ctx);
  1387. open_unlock:
  1388. mutex_unlock(&dev->dev_mutex);
  1389. return rc;
  1390. }
  1391. static int pxp_release(struct file *file)
  1392. {
  1393. struct pxp_dev *dev = video_drvdata(file);
  1394. struct pxp_ctx *ctx = file2ctx(file);
  1395. dprintk(dev, "Releasing instance %p\n", ctx);
  1396. v4l2_fh_del(&ctx->fh);
  1397. v4l2_fh_exit(&ctx->fh);
  1398. v4l2_ctrl_handler_free(&ctx->hdl);
  1399. mutex_lock(&dev->dev_mutex);
  1400. v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
  1401. mutex_unlock(&dev->dev_mutex);
  1402. kfree(ctx);
  1403. atomic_dec(&dev->num_inst);
  1404. return 0;
  1405. }
  1406. static const struct v4l2_file_operations pxp_fops = {
  1407. .owner = THIS_MODULE,
  1408. .open = pxp_open,
  1409. .release = pxp_release,
  1410. .poll = v4l2_m2m_fop_poll,
  1411. .unlocked_ioctl = video_ioctl2,
  1412. .mmap = v4l2_m2m_fop_mmap,
  1413. };
  1414. static const struct video_device pxp_videodev = {
  1415. .name = MEM2MEM_NAME,
  1416. .vfl_dir = VFL_DIR_M2M,
  1417. .fops = &pxp_fops,
  1418. .device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING,
  1419. .ioctl_ops = &pxp_ioctl_ops,
  1420. .minor = -1,
  1421. .release = video_device_release_empty,
  1422. };
  1423. static const struct v4l2_m2m_ops m2m_ops = {
  1424. .device_run = pxp_device_run,
  1425. .job_ready = pxp_job_ready,
  1426. .job_abort = pxp_job_abort,
  1427. };
  1428. static int pxp_soft_reset(struct pxp_dev *dev)
  1429. {
  1430. int ret;
  1431. u32 val;
  1432. writel(BM_PXP_CTRL_SFTRST, dev->mmio + HW_PXP_CTRL_CLR);
  1433. writel(BM_PXP_CTRL_CLKGATE, dev->mmio + HW_PXP_CTRL_CLR);
  1434. writel(BM_PXP_CTRL_SFTRST, dev->mmio + HW_PXP_CTRL_SET);
  1435. ret = readl_poll_timeout(dev->mmio + HW_PXP_CTRL, val,
  1436. val & BM_PXP_CTRL_CLKGATE, 0, 100);
  1437. if (ret < 0)
  1438. return ret;
  1439. writel(BM_PXP_CTRL_SFTRST, dev->mmio + HW_PXP_CTRL_CLR);
  1440. writel(BM_PXP_CTRL_CLKGATE, dev->mmio + HW_PXP_CTRL_CLR);
  1441. return 0;
  1442. }
  1443. static int pxp_probe(struct platform_device *pdev)
  1444. {
  1445. struct pxp_dev *dev;
  1446. struct resource *res;
  1447. struct video_device *vfd;
  1448. int irq;
  1449. int ret;
  1450. dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
  1451. if (!dev)
  1452. return -ENOMEM;
  1453. dev->clk = devm_clk_get(&pdev->dev, "axi");
  1454. if (IS_ERR(dev->clk)) {
  1455. ret = PTR_ERR(dev->clk);
  1456. dev_err(&pdev->dev, "Failed to get clk: %d\n", ret);
  1457. return ret;
  1458. }
  1459. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1460. dev->mmio = devm_ioremap_resource(&pdev->dev, res);
  1461. if (IS_ERR(dev->mmio)) {
  1462. ret = PTR_ERR(dev->mmio);
  1463. dev_err(&pdev->dev, "Failed to map register space: %d\n", ret);
  1464. return ret;
  1465. }
  1466. irq = platform_get_irq(pdev, 0);
  1467. if (irq < 0)
  1468. return irq;
  1469. ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, pxp_irq_handler,
  1470. IRQF_ONESHOT, dev_name(&pdev->dev), dev);
  1471. if (ret < 0) {
  1472. dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
  1473. return ret;
  1474. }
  1475. ret = clk_prepare_enable(dev->clk);
  1476. if (ret < 0)
  1477. return ret;
  1478. ret = pxp_soft_reset(dev);
  1479. if (ret < 0) {
  1480. dev_err(&pdev->dev, "PXP reset timeout: %d\n", ret);
  1481. goto err_clk;
  1482. }
  1483. spin_lock_init(&dev->irqlock);
  1484. ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
  1485. if (ret)
  1486. goto err_clk;
  1487. atomic_set(&dev->num_inst, 0);
  1488. mutex_init(&dev->dev_mutex);
  1489. dev->vfd = pxp_videodev;
  1490. vfd = &dev->vfd;
  1491. vfd->lock = &dev->dev_mutex;
  1492. vfd->v4l2_dev = &dev->v4l2_dev;
  1493. video_set_drvdata(vfd, dev);
  1494. snprintf(vfd->name, sizeof(vfd->name), "%s", pxp_videodev.name);
  1495. v4l2_info(&dev->v4l2_dev,
  1496. "Device registered as /dev/video%d\n", vfd->num);
  1497. platform_set_drvdata(pdev, dev);
  1498. dev->m2m_dev = v4l2_m2m_init(&m2m_ops);
  1499. if (IS_ERR(dev->m2m_dev)) {
  1500. v4l2_err(&dev->v4l2_dev, "Failed to init mem2mem device\n");
  1501. ret = PTR_ERR(dev->m2m_dev);
  1502. goto err_v4l2;
  1503. }
  1504. ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
  1505. if (ret) {
  1506. v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
  1507. goto err_m2m;
  1508. }
  1509. return 0;
  1510. err_m2m:
  1511. v4l2_m2m_release(dev->m2m_dev);
  1512. err_v4l2:
  1513. v4l2_device_unregister(&dev->v4l2_dev);
  1514. err_clk:
  1515. clk_disable_unprepare(dev->clk);
  1516. return ret;
  1517. }
  1518. static int pxp_remove(struct platform_device *pdev)
  1519. {
  1520. struct pxp_dev *dev = platform_get_drvdata(pdev);
  1521. writel(BM_PXP_CTRL_CLKGATE, dev->mmio + HW_PXP_CTRL_SET);
  1522. writel(BM_PXP_CTRL_SFTRST, dev->mmio + HW_PXP_CTRL_SET);
  1523. clk_disable_unprepare(dev->clk);
  1524. v4l2_info(&dev->v4l2_dev, "Removing " MEM2MEM_NAME);
  1525. video_unregister_device(&dev->vfd);
  1526. v4l2_m2m_release(dev->m2m_dev);
  1527. v4l2_device_unregister(&dev->v4l2_dev);
  1528. return 0;
  1529. }
  1530. static const struct of_device_id pxp_dt_ids[] = {
  1531. { .compatible = "fsl,imx6ull-pxp", .data = NULL },
  1532. { },
  1533. };
  1534. MODULE_DEVICE_TABLE(of, pxp_dt_ids);
  1535. static struct platform_driver pxp_driver = {
  1536. .probe = pxp_probe,
  1537. .remove = pxp_remove,
  1538. .driver = {
  1539. .name = MEM2MEM_NAME,
  1540. .of_match_table = of_match_ptr(pxp_dt_ids),
  1541. },
  1542. };
  1543. module_platform_driver(pxp_driver);
  1544. MODULE_DESCRIPTION("i.MX PXP mem2mem scaler/CSC/rotator");
  1545. MODULE_AUTHOR("Philipp Zabel <kernel@pengutronix.de>");
  1546. MODULE_LICENSE("GPL");