fimc-isp.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
  4. *
  5. * Copyright (C) 2013 Samsung Electronics Co., Ltd.
  6. *
  7. * Authors: Sylwester Nawrocki <s.nawrocki@samsung.com>
  8. * Younghwan Joo <yhwan.joo@samsung.com>
  9. */
  10. #define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
  11. #include <linux/device.h>
  12. #include <linux/errno.h>
  13. #include <linux/kernel.h>
  14. #include <linux/list.h>
  15. #include <linux/module.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/printk.h>
  18. #include <linux/pm_runtime.h>
  19. #include <linux/slab.h>
  20. #include <linux/types.h>
  21. #include <media/v4l2-device.h>
  22. #include "media-dev.h"
  23. #include "fimc-isp-video.h"
  24. #include "fimc-is-command.h"
  25. #include "fimc-is-param.h"
  26. #include "fimc-is-regs.h"
  27. #include "fimc-is.h"
  28. int fimc_isp_debug;
  29. module_param_named(debug_isp, fimc_isp_debug, int, S_IRUGO | S_IWUSR);
  30. static const struct fimc_fmt fimc_isp_formats[FIMC_ISP_NUM_FORMATS] = {
  31. {
  32. .fourcc = V4L2_PIX_FMT_SGRBG8,
  33. .depth = { 8 },
  34. .color = FIMC_FMT_RAW8,
  35. .memplanes = 1,
  36. .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
  37. }, {
  38. .fourcc = V4L2_PIX_FMT_SGRBG10,
  39. .depth = { 10 },
  40. .color = FIMC_FMT_RAW10,
  41. .memplanes = 1,
  42. .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
  43. }, {
  44. .fourcc = V4L2_PIX_FMT_SGRBG12,
  45. .depth = { 12 },
  46. .color = FIMC_FMT_RAW12,
  47. .memplanes = 1,
  48. .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12,
  49. },
  50. };
  51. /**
  52. * fimc_isp_find_format - lookup color format by fourcc or media bus code
  53. * @pixelformat: fourcc to match, ignored if null
  54. * @mbus_code: media bus code to match, ignored if null
  55. * @index: index to the fimc_isp_formats array, ignored if negative
  56. */
  57. const struct fimc_fmt *fimc_isp_find_format(const u32 *pixelformat,
  58. const u32 *mbus_code, int index)
  59. {
  60. const struct fimc_fmt *fmt, *def_fmt = NULL;
  61. unsigned int i;
  62. int id = 0;
  63. if (index >= (int)ARRAY_SIZE(fimc_isp_formats))
  64. return NULL;
  65. for (i = 0; i < ARRAY_SIZE(fimc_isp_formats); ++i) {
  66. fmt = &fimc_isp_formats[i];
  67. if (pixelformat && fmt->fourcc == *pixelformat)
  68. return fmt;
  69. if (mbus_code && fmt->mbus_code == *mbus_code)
  70. return fmt;
  71. if (index == id)
  72. def_fmt = fmt;
  73. id++;
  74. }
  75. return def_fmt;
  76. }
  77. void fimc_isp_irq_handler(struct fimc_is *is)
  78. {
  79. is->i2h_cmd.args[0] = mcuctl_read(is, MCUCTL_REG_ISSR(20));
  80. is->i2h_cmd.args[1] = mcuctl_read(is, MCUCTL_REG_ISSR(21));
  81. fimc_is_fw_clear_irq1(is, FIMC_IS_INT_FRAME_DONE_ISP);
  82. fimc_isp_video_irq_handler(is);
  83. wake_up(&is->irq_queue);
  84. }
  85. /* Capture subdev media entity operations */
  86. static int fimc_is_link_setup(struct media_entity *entity,
  87. const struct media_pad *local,
  88. const struct media_pad *remote, u32 flags)
  89. {
  90. return 0;
  91. }
  92. static const struct media_entity_operations fimc_is_subdev_media_ops = {
  93. .link_setup = fimc_is_link_setup,
  94. };
  95. static int fimc_is_subdev_enum_mbus_code(struct v4l2_subdev *sd,
  96. struct v4l2_subdev_pad_config *cfg,
  97. struct v4l2_subdev_mbus_code_enum *code)
  98. {
  99. const struct fimc_fmt *fmt;
  100. fmt = fimc_isp_find_format(NULL, NULL, code->index);
  101. if (!fmt)
  102. return -EINVAL;
  103. code->code = fmt->mbus_code;
  104. return 0;
  105. }
  106. static int fimc_isp_subdev_get_fmt(struct v4l2_subdev *sd,
  107. struct v4l2_subdev_pad_config *cfg,
  108. struct v4l2_subdev_format *fmt)
  109. {
  110. struct fimc_isp *isp = v4l2_get_subdevdata(sd);
  111. struct v4l2_mbus_framefmt *mf = &fmt->format;
  112. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  113. *mf = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
  114. return 0;
  115. }
  116. mf->colorspace = V4L2_COLORSPACE_SRGB;
  117. mutex_lock(&isp->subdev_lock);
  118. if (fmt->pad == FIMC_ISP_SD_PAD_SINK) {
  119. /* ISP OTF input image format */
  120. *mf = isp->sink_fmt;
  121. } else {
  122. /* ISP OTF output image format */
  123. *mf = isp->src_fmt;
  124. if (fmt->pad == FIMC_ISP_SD_PAD_SRC_FIFO) {
  125. mf->colorspace = V4L2_COLORSPACE_JPEG;
  126. mf->code = MEDIA_BUS_FMT_YUV10_1X30;
  127. }
  128. }
  129. mutex_unlock(&isp->subdev_lock);
  130. isp_dbg(1, sd, "%s: pad%d: fmt: 0x%x, %dx%d\n", __func__,
  131. fmt->pad, mf->code, mf->width, mf->height);
  132. return 0;
  133. }
  134. static void __isp_subdev_try_format(struct fimc_isp *isp,
  135. struct v4l2_subdev_pad_config *cfg,
  136. struct v4l2_subdev_format *fmt)
  137. {
  138. struct v4l2_mbus_framefmt *mf = &fmt->format;
  139. struct v4l2_mbus_framefmt *format;
  140. mf->colorspace = V4L2_COLORSPACE_SRGB;
  141. if (fmt->pad == FIMC_ISP_SD_PAD_SINK) {
  142. v4l_bound_align_image(&mf->width, FIMC_ISP_SINK_WIDTH_MIN,
  143. FIMC_ISP_SINK_WIDTH_MAX, 0,
  144. &mf->height, FIMC_ISP_SINK_HEIGHT_MIN,
  145. FIMC_ISP_SINK_HEIGHT_MAX, 0, 0);
  146. mf->code = MEDIA_BUS_FMT_SGRBG10_1X10;
  147. } else {
  148. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
  149. format = v4l2_subdev_get_try_format(&isp->subdev, cfg,
  150. FIMC_ISP_SD_PAD_SINK);
  151. else
  152. format = &isp->sink_fmt;
  153. /* Allow changing format only on sink pad */
  154. mf->width = format->width - FIMC_ISP_CAC_MARGIN_WIDTH;
  155. mf->height = format->height - FIMC_ISP_CAC_MARGIN_HEIGHT;
  156. if (fmt->pad == FIMC_ISP_SD_PAD_SRC_FIFO) {
  157. mf->code = MEDIA_BUS_FMT_YUV10_1X30;
  158. mf->colorspace = V4L2_COLORSPACE_JPEG;
  159. } else {
  160. mf->code = format->code;
  161. }
  162. }
  163. }
  164. static int fimc_isp_subdev_set_fmt(struct v4l2_subdev *sd,
  165. struct v4l2_subdev_pad_config *cfg,
  166. struct v4l2_subdev_format *fmt)
  167. {
  168. struct fimc_isp *isp = v4l2_get_subdevdata(sd);
  169. struct fimc_is *is = fimc_isp_to_is(isp);
  170. struct v4l2_mbus_framefmt *mf = &fmt->format;
  171. int ret = 0;
  172. isp_dbg(1, sd, "%s: pad%d: code: 0x%x, %dx%d\n",
  173. __func__, fmt->pad, mf->code, mf->width, mf->height);
  174. mutex_lock(&isp->subdev_lock);
  175. __isp_subdev_try_format(isp, cfg, fmt);
  176. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  177. mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
  178. *mf = fmt->format;
  179. /* Propagate format to the source pads */
  180. if (fmt->pad == FIMC_ISP_SD_PAD_SINK) {
  181. struct v4l2_subdev_format format = *fmt;
  182. unsigned int pad;
  183. for (pad = FIMC_ISP_SD_PAD_SRC_FIFO;
  184. pad < FIMC_ISP_SD_PADS_NUM; pad++) {
  185. format.pad = pad;
  186. __isp_subdev_try_format(isp, cfg, &format);
  187. mf = v4l2_subdev_get_try_format(sd, cfg, pad);
  188. *mf = format.format;
  189. }
  190. }
  191. } else {
  192. if (sd->entity.stream_count == 0) {
  193. if (fmt->pad == FIMC_ISP_SD_PAD_SINK) {
  194. struct v4l2_subdev_format format = *fmt;
  195. isp->sink_fmt = *mf;
  196. format.pad = FIMC_ISP_SD_PAD_SRC_DMA;
  197. __isp_subdev_try_format(isp, cfg, &format);
  198. isp->src_fmt = format.format;
  199. __is_set_frame_size(is, &isp->src_fmt);
  200. } else {
  201. isp->src_fmt = *mf;
  202. }
  203. } else {
  204. ret = -EBUSY;
  205. }
  206. }
  207. mutex_unlock(&isp->subdev_lock);
  208. return ret;
  209. }
  210. static int fimc_isp_subdev_s_stream(struct v4l2_subdev *sd, int on)
  211. {
  212. struct fimc_isp *isp = v4l2_get_subdevdata(sd);
  213. struct fimc_is *is = fimc_isp_to_is(isp);
  214. int ret;
  215. isp_dbg(1, sd, "%s: on: %d\n", __func__, on);
  216. if (!test_bit(IS_ST_INIT_DONE, &is->state))
  217. return -EBUSY;
  218. fimc_is_mem_barrier();
  219. if (on) {
  220. if (__get_pending_param_count(is)) {
  221. ret = fimc_is_itf_s_param(is, true);
  222. if (ret < 0)
  223. return ret;
  224. }
  225. isp_dbg(1, sd, "changing mode to %d\n", is->config_index);
  226. ret = fimc_is_itf_mode_change(is);
  227. if (ret)
  228. return -EINVAL;
  229. clear_bit(IS_ST_STREAM_ON, &is->state);
  230. fimc_is_hw_stream_on(is);
  231. ret = fimc_is_wait_event(is, IS_ST_STREAM_ON, 1,
  232. FIMC_IS_CONFIG_TIMEOUT);
  233. if (ret < 0) {
  234. v4l2_err(sd, "stream on timeout\n");
  235. return ret;
  236. }
  237. } else {
  238. clear_bit(IS_ST_STREAM_OFF, &is->state);
  239. fimc_is_hw_stream_off(is);
  240. ret = fimc_is_wait_event(is, IS_ST_STREAM_OFF, 1,
  241. FIMC_IS_CONFIG_TIMEOUT);
  242. if (ret < 0) {
  243. v4l2_err(sd, "stream off timeout\n");
  244. return ret;
  245. }
  246. is->setfile.sub_index = 0;
  247. }
  248. return 0;
  249. }
  250. static int fimc_isp_subdev_s_power(struct v4l2_subdev *sd, int on)
  251. {
  252. struct fimc_isp *isp = v4l2_get_subdevdata(sd);
  253. struct fimc_is *is = fimc_isp_to_is(isp);
  254. int ret = 0;
  255. pr_debug("on: %d\n", on);
  256. if (on) {
  257. ret = pm_runtime_get_sync(&is->pdev->dev);
  258. if (ret < 0) {
  259. pm_runtime_put(&is->pdev->dev);
  260. return ret;
  261. }
  262. set_bit(IS_ST_PWR_ON, &is->state);
  263. ret = fimc_is_start_firmware(is);
  264. if (ret < 0) {
  265. v4l2_err(sd, "firmware booting failed\n");
  266. pm_runtime_put(&is->pdev->dev);
  267. return ret;
  268. }
  269. set_bit(IS_ST_PWR_SUBIP_ON, &is->state);
  270. ret = fimc_is_hw_initialize(is);
  271. } else {
  272. /* Close sensor */
  273. if (!test_bit(IS_ST_PWR_ON, &is->state)) {
  274. fimc_is_hw_close_sensor(is, 0);
  275. ret = fimc_is_wait_event(is, IS_ST_OPEN_SENSOR, 0,
  276. FIMC_IS_CONFIG_TIMEOUT);
  277. if (ret < 0) {
  278. v4l2_err(sd, "sensor close timeout\n");
  279. return ret;
  280. }
  281. }
  282. /* SUB IP power off */
  283. if (test_bit(IS_ST_PWR_SUBIP_ON, &is->state)) {
  284. fimc_is_hw_subip_power_off(is);
  285. ret = fimc_is_wait_event(is, IS_ST_PWR_SUBIP_ON, 0,
  286. FIMC_IS_CONFIG_TIMEOUT);
  287. if (ret < 0) {
  288. v4l2_err(sd, "sub-IP power off timeout\n");
  289. return ret;
  290. }
  291. }
  292. fimc_is_cpu_set_power(is, 0);
  293. pm_runtime_put_sync(&is->pdev->dev);
  294. clear_bit(IS_ST_PWR_ON, &is->state);
  295. clear_bit(IS_ST_INIT_DONE, &is->state);
  296. is->state = 0;
  297. is->config[is->config_index].p_region_index[0] = 0;
  298. is->config[is->config_index].p_region_index[1] = 0;
  299. set_bit(IS_ST_IDLE, &is->state);
  300. wmb();
  301. }
  302. return ret;
  303. }
  304. static int fimc_isp_subdev_open(struct v4l2_subdev *sd,
  305. struct v4l2_subdev_fh *fh)
  306. {
  307. struct v4l2_mbus_framefmt *format;
  308. struct v4l2_mbus_framefmt fmt = {
  309. .colorspace = V4L2_COLORSPACE_SRGB,
  310. .code = fimc_isp_formats[0].mbus_code,
  311. .width = DEFAULT_PREVIEW_STILL_WIDTH + FIMC_ISP_CAC_MARGIN_WIDTH,
  312. .height = DEFAULT_PREVIEW_STILL_HEIGHT + FIMC_ISP_CAC_MARGIN_HEIGHT,
  313. .field = V4L2_FIELD_NONE,
  314. };
  315. format = v4l2_subdev_get_try_format(sd, fh->pad, FIMC_ISP_SD_PAD_SINK);
  316. *format = fmt;
  317. format = v4l2_subdev_get_try_format(sd, fh->pad, FIMC_ISP_SD_PAD_SRC_FIFO);
  318. fmt.width = DEFAULT_PREVIEW_STILL_WIDTH;
  319. fmt.height = DEFAULT_PREVIEW_STILL_HEIGHT;
  320. *format = fmt;
  321. format = v4l2_subdev_get_try_format(sd, fh->pad, FIMC_ISP_SD_PAD_SRC_DMA);
  322. *format = fmt;
  323. return 0;
  324. }
  325. static int fimc_isp_subdev_registered(struct v4l2_subdev *sd)
  326. {
  327. struct fimc_isp *isp = v4l2_get_subdevdata(sd);
  328. int ret;
  329. /* Use pipeline object allocated by the media device. */
  330. isp->video_capture.ve.pipe = v4l2_get_subdev_hostdata(sd);
  331. ret = fimc_isp_video_device_register(isp, sd->v4l2_dev,
  332. V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
  333. if (ret < 0)
  334. isp->video_capture.ve.pipe = NULL;
  335. return ret;
  336. }
  337. static void fimc_isp_subdev_unregistered(struct v4l2_subdev *sd)
  338. {
  339. struct fimc_isp *isp = v4l2_get_subdevdata(sd);
  340. fimc_isp_video_device_unregister(isp,
  341. V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
  342. }
  343. static const struct v4l2_subdev_internal_ops fimc_is_subdev_internal_ops = {
  344. .registered = fimc_isp_subdev_registered,
  345. .unregistered = fimc_isp_subdev_unregistered,
  346. .open = fimc_isp_subdev_open,
  347. };
  348. static const struct v4l2_subdev_pad_ops fimc_is_subdev_pad_ops = {
  349. .enum_mbus_code = fimc_is_subdev_enum_mbus_code,
  350. .get_fmt = fimc_isp_subdev_get_fmt,
  351. .set_fmt = fimc_isp_subdev_set_fmt,
  352. };
  353. static const struct v4l2_subdev_video_ops fimc_is_subdev_video_ops = {
  354. .s_stream = fimc_isp_subdev_s_stream,
  355. };
  356. static const struct v4l2_subdev_core_ops fimc_is_core_ops = {
  357. .s_power = fimc_isp_subdev_s_power,
  358. };
  359. static const struct v4l2_subdev_ops fimc_is_subdev_ops = {
  360. .core = &fimc_is_core_ops,
  361. .video = &fimc_is_subdev_video_ops,
  362. .pad = &fimc_is_subdev_pad_ops,
  363. };
  364. static int __ctrl_set_white_balance(struct fimc_is *is, int value)
  365. {
  366. switch (value) {
  367. case V4L2_WHITE_BALANCE_AUTO:
  368. __is_set_isp_awb(is, ISP_AWB_COMMAND_AUTO, 0);
  369. break;
  370. case V4L2_WHITE_BALANCE_DAYLIGHT:
  371. __is_set_isp_awb(is, ISP_AWB_COMMAND_ILLUMINATION,
  372. ISP_AWB_ILLUMINATION_DAYLIGHT);
  373. break;
  374. case V4L2_WHITE_BALANCE_CLOUDY:
  375. __is_set_isp_awb(is, ISP_AWB_COMMAND_ILLUMINATION,
  376. ISP_AWB_ILLUMINATION_CLOUDY);
  377. break;
  378. case V4L2_WHITE_BALANCE_INCANDESCENT:
  379. __is_set_isp_awb(is, ISP_AWB_COMMAND_ILLUMINATION,
  380. ISP_AWB_ILLUMINATION_TUNGSTEN);
  381. break;
  382. case V4L2_WHITE_BALANCE_FLUORESCENT:
  383. __is_set_isp_awb(is, ISP_AWB_COMMAND_ILLUMINATION,
  384. ISP_AWB_ILLUMINATION_FLUORESCENT);
  385. break;
  386. default:
  387. return -EINVAL;
  388. }
  389. return 0;
  390. }
  391. static int __ctrl_set_aewb_lock(struct fimc_is *is,
  392. struct v4l2_ctrl *ctrl)
  393. {
  394. bool awb_lock = ctrl->val & V4L2_LOCK_WHITE_BALANCE;
  395. bool ae_lock = ctrl->val & V4L2_LOCK_EXPOSURE;
  396. struct isp_param *isp = &is->is_p_region->parameter.isp;
  397. int cmd, ret;
  398. cmd = ae_lock ? ISP_AA_COMMAND_STOP : ISP_AA_COMMAND_START;
  399. isp->aa.cmd = cmd;
  400. isp->aa.target = ISP_AA_TARGET_AE;
  401. fimc_is_set_param_bit(is, PARAM_ISP_AA);
  402. is->af.ae_lock_state = ae_lock;
  403. wmb();
  404. ret = fimc_is_itf_s_param(is, false);
  405. if (ret < 0)
  406. return ret;
  407. cmd = awb_lock ? ISP_AA_COMMAND_STOP : ISP_AA_COMMAND_START;
  408. isp->aa.cmd = cmd;
  409. isp->aa.target = ISP_AA_TARGET_AE;
  410. fimc_is_set_param_bit(is, PARAM_ISP_AA);
  411. is->af.awb_lock_state = awb_lock;
  412. wmb();
  413. return fimc_is_itf_s_param(is, false);
  414. }
  415. /* Supported manual ISO values */
  416. static const s64 iso_qmenu[] = {
  417. 50, 100, 200, 400, 800,
  418. };
  419. static int __ctrl_set_iso(struct fimc_is *is, int value)
  420. {
  421. unsigned int idx, iso;
  422. if (value == V4L2_ISO_SENSITIVITY_AUTO) {
  423. __is_set_isp_iso(is, ISP_ISO_COMMAND_AUTO, 0);
  424. return 0;
  425. }
  426. idx = is->isp.ctrls.iso->val;
  427. if (idx >= ARRAY_SIZE(iso_qmenu))
  428. return -EINVAL;
  429. iso = iso_qmenu[idx];
  430. __is_set_isp_iso(is, ISP_ISO_COMMAND_MANUAL, iso);
  431. return 0;
  432. }
  433. static int __ctrl_set_metering(struct fimc_is *is, unsigned int value)
  434. {
  435. unsigned int val;
  436. switch (value) {
  437. case V4L2_EXPOSURE_METERING_AVERAGE:
  438. val = ISP_METERING_COMMAND_AVERAGE;
  439. break;
  440. case V4L2_EXPOSURE_METERING_CENTER_WEIGHTED:
  441. val = ISP_METERING_COMMAND_CENTER;
  442. break;
  443. case V4L2_EXPOSURE_METERING_SPOT:
  444. val = ISP_METERING_COMMAND_SPOT;
  445. break;
  446. case V4L2_EXPOSURE_METERING_MATRIX:
  447. val = ISP_METERING_COMMAND_MATRIX;
  448. break;
  449. default:
  450. return -EINVAL;
  451. }
  452. __is_set_isp_metering(is, IS_METERING_CONFIG_CMD, val);
  453. return 0;
  454. }
  455. static int __ctrl_set_afc(struct fimc_is *is, int value)
  456. {
  457. switch (value) {
  458. case V4L2_CID_POWER_LINE_FREQUENCY_DISABLED:
  459. __is_set_isp_afc(is, ISP_AFC_COMMAND_DISABLE, 0);
  460. break;
  461. case V4L2_CID_POWER_LINE_FREQUENCY_50HZ:
  462. __is_set_isp_afc(is, ISP_AFC_COMMAND_MANUAL, 50);
  463. break;
  464. case V4L2_CID_POWER_LINE_FREQUENCY_60HZ:
  465. __is_set_isp_afc(is, ISP_AFC_COMMAND_MANUAL, 60);
  466. break;
  467. case V4L2_CID_POWER_LINE_FREQUENCY_AUTO:
  468. __is_set_isp_afc(is, ISP_AFC_COMMAND_AUTO, 0);
  469. break;
  470. default:
  471. return -EINVAL;
  472. }
  473. return 0;
  474. }
  475. static int __ctrl_set_image_effect(struct fimc_is *is, int value)
  476. {
  477. static const u8 effects[][2] = {
  478. { V4L2_COLORFX_NONE, ISP_IMAGE_EFFECT_DISABLE },
  479. { V4L2_COLORFX_BW, ISP_IMAGE_EFFECT_MONOCHROME },
  480. { V4L2_COLORFX_SEPIA, ISP_IMAGE_EFFECT_SEPIA },
  481. { V4L2_COLORFX_NEGATIVE, ISP_IMAGE_EFFECT_NEGATIVE_MONO },
  482. { 16 /* TODO */, ISP_IMAGE_EFFECT_NEGATIVE_COLOR },
  483. };
  484. int i;
  485. for (i = 0; i < ARRAY_SIZE(effects); i++) {
  486. if (effects[i][0] != value)
  487. continue;
  488. __is_set_isp_effect(is, effects[i][1]);
  489. return 0;
  490. }
  491. return -EINVAL;
  492. }
  493. static int fimc_is_s_ctrl(struct v4l2_ctrl *ctrl)
  494. {
  495. struct fimc_isp *isp = ctrl_to_fimc_isp(ctrl);
  496. struct fimc_is *is = fimc_isp_to_is(isp);
  497. bool set_param = true;
  498. int ret = 0;
  499. switch (ctrl->id) {
  500. case V4L2_CID_CONTRAST:
  501. __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_CONTRAST,
  502. ctrl->val);
  503. break;
  504. case V4L2_CID_SATURATION:
  505. __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_SATURATION,
  506. ctrl->val);
  507. break;
  508. case V4L2_CID_SHARPNESS:
  509. __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_SHARPNESS,
  510. ctrl->val);
  511. break;
  512. case V4L2_CID_EXPOSURE_ABSOLUTE:
  513. __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_EXPOSURE,
  514. ctrl->val);
  515. break;
  516. case V4L2_CID_BRIGHTNESS:
  517. __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS,
  518. ctrl->val);
  519. break;
  520. case V4L2_CID_HUE:
  521. __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_HUE,
  522. ctrl->val);
  523. break;
  524. case V4L2_CID_EXPOSURE_METERING:
  525. ret = __ctrl_set_metering(is, ctrl->val);
  526. break;
  527. case V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE:
  528. ret = __ctrl_set_white_balance(is, ctrl->val);
  529. break;
  530. case V4L2_CID_3A_LOCK:
  531. ret = __ctrl_set_aewb_lock(is, ctrl);
  532. set_param = false;
  533. break;
  534. case V4L2_CID_ISO_SENSITIVITY_AUTO:
  535. ret = __ctrl_set_iso(is, ctrl->val);
  536. break;
  537. case V4L2_CID_POWER_LINE_FREQUENCY:
  538. ret = __ctrl_set_afc(is, ctrl->val);
  539. break;
  540. case V4L2_CID_COLORFX:
  541. __ctrl_set_image_effect(is, ctrl->val);
  542. break;
  543. default:
  544. ret = -EINVAL;
  545. break;
  546. }
  547. if (ret < 0) {
  548. v4l2_err(&isp->subdev, "Failed to set control: %s (%d)\n",
  549. ctrl->name, ctrl->val);
  550. return ret;
  551. }
  552. if (set_param && test_bit(IS_ST_STREAM_ON, &is->state))
  553. return fimc_is_itf_s_param(is, true);
  554. return 0;
  555. }
  556. static const struct v4l2_ctrl_ops fimc_isp_ctrl_ops = {
  557. .s_ctrl = fimc_is_s_ctrl,
  558. };
  559. static void __isp_subdev_set_default_format(struct fimc_isp *isp)
  560. {
  561. struct fimc_is *is = fimc_isp_to_is(isp);
  562. isp->sink_fmt.width = DEFAULT_PREVIEW_STILL_WIDTH +
  563. FIMC_ISP_CAC_MARGIN_WIDTH;
  564. isp->sink_fmt.height = DEFAULT_PREVIEW_STILL_HEIGHT +
  565. FIMC_ISP_CAC_MARGIN_HEIGHT;
  566. isp->sink_fmt.code = MEDIA_BUS_FMT_SGRBG10_1X10;
  567. isp->src_fmt.width = DEFAULT_PREVIEW_STILL_WIDTH;
  568. isp->src_fmt.height = DEFAULT_PREVIEW_STILL_HEIGHT;
  569. isp->src_fmt.code = MEDIA_BUS_FMT_SGRBG10_1X10;
  570. __is_set_frame_size(is, &isp->src_fmt);
  571. }
  572. int fimc_isp_subdev_create(struct fimc_isp *isp)
  573. {
  574. const struct v4l2_ctrl_ops *ops = &fimc_isp_ctrl_ops;
  575. struct v4l2_ctrl_handler *handler = &isp->ctrls.handler;
  576. struct v4l2_subdev *sd = &isp->subdev;
  577. struct fimc_isp_ctrls *ctrls = &isp->ctrls;
  578. int ret;
  579. mutex_init(&isp->subdev_lock);
  580. v4l2_subdev_init(sd, &fimc_is_subdev_ops);
  581. sd->owner = THIS_MODULE;
  582. sd->grp_id = GRP_ID_FIMC_IS;
  583. sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
  584. snprintf(sd->name, sizeof(sd->name), "FIMC-IS-ISP");
  585. sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER;
  586. isp->subdev_pads[FIMC_ISP_SD_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
  587. isp->subdev_pads[FIMC_ISP_SD_PAD_SRC_FIFO].flags = MEDIA_PAD_FL_SOURCE;
  588. isp->subdev_pads[FIMC_ISP_SD_PAD_SRC_DMA].flags = MEDIA_PAD_FL_SOURCE;
  589. ret = media_entity_pads_init(&sd->entity, FIMC_ISP_SD_PADS_NUM,
  590. isp->subdev_pads);
  591. if (ret)
  592. return ret;
  593. v4l2_ctrl_handler_init(handler, 20);
  594. ctrls->saturation = v4l2_ctrl_new_std(handler, ops, V4L2_CID_SATURATION,
  595. -2, 2, 1, 0);
  596. ctrls->brightness = v4l2_ctrl_new_std(handler, ops, V4L2_CID_BRIGHTNESS,
  597. -4, 4, 1, 0);
  598. ctrls->contrast = v4l2_ctrl_new_std(handler, ops, V4L2_CID_CONTRAST,
  599. -2, 2, 1, 0);
  600. ctrls->sharpness = v4l2_ctrl_new_std(handler, ops, V4L2_CID_SHARPNESS,
  601. -2, 2, 1, 0);
  602. ctrls->hue = v4l2_ctrl_new_std(handler, ops, V4L2_CID_HUE,
  603. -2, 2, 1, 0);
  604. ctrls->auto_wb = v4l2_ctrl_new_std_menu(handler, ops,
  605. V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE,
  606. 8, ~0x14e, V4L2_WHITE_BALANCE_AUTO);
  607. ctrls->exposure = v4l2_ctrl_new_std(handler, ops,
  608. V4L2_CID_EXPOSURE_ABSOLUTE,
  609. -4, 4, 1, 0);
  610. ctrls->exp_metering = v4l2_ctrl_new_std_menu(handler, ops,
  611. V4L2_CID_EXPOSURE_METERING, 3,
  612. ~0xf, V4L2_EXPOSURE_METERING_AVERAGE);
  613. v4l2_ctrl_new_std_menu(handler, ops, V4L2_CID_POWER_LINE_FREQUENCY,
  614. V4L2_CID_POWER_LINE_FREQUENCY_AUTO, 0,
  615. V4L2_CID_POWER_LINE_FREQUENCY_AUTO);
  616. /* ISO sensitivity */
  617. ctrls->auto_iso = v4l2_ctrl_new_std_menu(handler, ops,
  618. V4L2_CID_ISO_SENSITIVITY_AUTO, 1, 0,
  619. V4L2_ISO_SENSITIVITY_AUTO);
  620. ctrls->iso = v4l2_ctrl_new_int_menu(handler, ops,
  621. V4L2_CID_ISO_SENSITIVITY, ARRAY_SIZE(iso_qmenu) - 1,
  622. ARRAY_SIZE(iso_qmenu)/2 - 1, iso_qmenu);
  623. ctrls->aewb_lock = v4l2_ctrl_new_std(handler, ops,
  624. V4L2_CID_3A_LOCK, 0, 0x3, 0, 0);
  625. /* TODO: Add support for NEGATIVE_COLOR option */
  626. ctrls->colorfx = v4l2_ctrl_new_std_menu(handler, ops, V4L2_CID_COLORFX,
  627. V4L2_COLORFX_SET_CBCR + 1, ~0x1000f, V4L2_COLORFX_NONE);
  628. if (handler->error) {
  629. media_entity_cleanup(&sd->entity);
  630. return handler->error;
  631. }
  632. v4l2_ctrl_auto_cluster(2, &ctrls->auto_iso,
  633. V4L2_ISO_SENSITIVITY_MANUAL, false);
  634. sd->ctrl_handler = handler;
  635. sd->internal_ops = &fimc_is_subdev_internal_ops;
  636. sd->entity.ops = &fimc_is_subdev_media_ops;
  637. v4l2_set_subdevdata(sd, isp);
  638. __isp_subdev_set_default_format(isp);
  639. return 0;
  640. }
  641. void fimc_isp_subdev_destroy(struct fimc_isp *isp)
  642. {
  643. struct v4l2_subdev *sd = &isp->subdev;
  644. v4l2_device_unregister_subdev(sd);
  645. media_entity_cleanup(&sd->entity);
  646. v4l2_ctrl_handler_free(&isp->ctrls.handler);
  647. v4l2_set_subdevdata(sd, NULL);
  648. }