atmel-isc.h 6.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Microchip Image Sensor Controller (ISC) driver header file
  4. *
  5. * Copyright (C) 2016-2019 Microchip Technology, Inc.
  6. *
  7. * Author: Songjun Wu
  8. * Author: Eugen Hristev <eugen.hristev@microchip.com>
  9. *
  10. */
  11. #ifndef _ATMEL_ISC_H_
  12. #define ISC_MAX_SUPPORT_WIDTH 2592
  13. #define ISC_MAX_SUPPORT_HEIGHT 1944
  14. #define ISC_CLK_MAX_DIV 255
  15. enum isc_clk_id {
  16. ISC_ISPCK = 0,
  17. ISC_MCK = 1,
  18. };
  19. struct isc_clk {
  20. struct clk_hw hw;
  21. struct clk *clk;
  22. struct regmap *regmap;
  23. spinlock_t lock; /* serialize access to clock registers */
  24. u8 id;
  25. u8 parent_id;
  26. u32 div;
  27. struct device *dev;
  28. };
  29. #define to_isc_clk(v) container_of(v, struct isc_clk, hw)
  30. struct isc_buffer {
  31. struct vb2_v4l2_buffer vb;
  32. struct list_head list;
  33. };
  34. struct isc_subdev_entity {
  35. struct v4l2_subdev *sd;
  36. struct v4l2_async_subdev *asd;
  37. struct v4l2_async_notifier notifier;
  38. u32 pfe_cfg0;
  39. struct list_head list;
  40. };
  41. /*
  42. * struct isc_format - ISC media bus format information
  43. This structure represents the interface between the ISC
  44. and the sensor. It's the input format received by
  45. the ISC.
  46. * @fourcc: Fourcc code for this format
  47. * @mbus_code: V4L2 media bus format code.
  48. * @cfa_baycfg: If this format is RAW BAYER, indicate the type of bayer.
  49. this is either BGBG, RGRG, etc.
  50. * @pfe_cfg0_bps: Number of hardware data lines connected to the ISC
  51. */
  52. struct isc_format {
  53. u32 fourcc;
  54. u32 mbus_code;
  55. u32 cfa_baycfg;
  56. bool sd_support;
  57. u32 pfe_cfg0_bps;
  58. };
  59. /* Pipeline bitmap */
  60. #define WB_ENABLE BIT(0)
  61. #define CFA_ENABLE BIT(1)
  62. #define CC_ENABLE BIT(2)
  63. #define GAM_ENABLE BIT(3)
  64. #define GAM_BENABLE BIT(4)
  65. #define GAM_GENABLE BIT(5)
  66. #define GAM_RENABLE BIT(6)
  67. #define CSC_ENABLE BIT(7)
  68. #define CBC_ENABLE BIT(8)
  69. #define SUB422_ENABLE BIT(9)
  70. #define SUB420_ENABLE BIT(10)
  71. #define GAM_ENABLES (GAM_RENABLE | GAM_GENABLE | GAM_BENABLE | GAM_ENABLE)
  72. /*
  73. * struct fmt_config - ISC format configuration and internal pipeline
  74. This structure represents the internal configuration
  75. of the ISC.
  76. It also holds the format that ISC will present to v4l2.
  77. * @sd_format: Pointer to an isc_format struct that holds the sensor
  78. configuration.
  79. * @fourcc: Fourcc code for this format.
  80. * @bpp: Bytes per pixel in the current format.
  81. * @rlp_cfg_mode: Configuration of the RLP (rounding, limiting packaging)
  82. * @dcfg_imode: Configuration of the input of the DMA module
  83. * @dctrl_dview: Configuration of the output of the DMA module
  84. * @bits_pipeline: Configuration of the pipeline, which modules are enabled
  85. */
  86. struct fmt_config {
  87. struct isc_format *sd_format;
  88. u32 fourcc;
  89. u8 bpp;
  90. u32 rlp_cfg_mode;
  91. u32 dcfg_imode;
  92. u32 dctrl_dview;
  93. u32 bits_pipeline;
  94. };
  95. #define HIST_ENTRIES 512
  96. #define HIST_BAYER (ISC_HIS_CFG_MODE_B + 1)
  97. enum{
  98. HIST_INIT = 0,
  99. HIST_ENABLED,
  100. HIST_DISABLED,
  101. };
  102. struct isc_ctrls {
  103. struct v4l2_ctrl_handler handler;
  104. u32 brightness;
  105. u32 contrast;
  106. u8 gamma_index;
  107. #define ISC_WB_NONE 0
  108. #define ISC_WB_AUTO 1
  109. #define ISC_WB_ONETIME 2
  110. u8 awb;
  111. /* one for each component : GR, R, GB, B */
  112. u32 gain[HIST_BAYER];
  113. u32 offset[HIST_BAYER];
  114. u32 hist_entry[HIST_ENTRIES];
  115. u32 hist_count[HIST_BAYER];
  116. u8 hist_id;
  117. u8 hist_stat;
  118. #define HIST_MIN_INDEX 0
  119. #define HIST_MAX_INDEX 1
  120. u32 hist_minmax[HIST_BAYER][2];
  121. };
  122. #define ISC_PIPE_LINE_NODE_NUM 11
  123. /*
  124. * struct isc_device - ISC device driver data/config struct
  125. * @regmap: Register map
  126. * @hclock: Hclock clock input (refer datasheet)
  127. * @ispck: iscpck clock (refer datasheet)
  128. * @isc_clks: ISC clocks
  129. *
  130. * @dev: Registered device driver
  131. * @v4l2_dev: v4l2 registered device
  132. * @video_dev: registered video device
  133. *
  134. * @vb2_vidq: video buffer 2 video queue
  135. * @dma_queue_lock: lock to serialize the dma buffer queue
  136. * @dma_queue: the queue for dma buffers
  137. * @cur_frm: current isc frame/buffer
  138. * @sequence: current frame number
  139. * @stop: true if isc is not streaming, false if streaming
  140. * @comp: completion reference that signals frame completion
  141. *
  142. * @fmt: current v42l format
  143. * @user_formats: list of formats that are supported and agreed with sd
  144. * @num_user_formats: how many formats are in user_formats
  145. *
  146. * @config: current ISC format configuration
  147. * @try_config: the current ISC try format , not yet activated
  148. *
  149. * @ctrls: holds information about ISC controls
  150. * @do_wb_ctrl: control regarding the DO_WHITE_BALANCE button
  151. * @awb_work: workqueue reference for autowhitebalance histogram
  152. * analysis
  153. *
  154. * @lock: lock for serializing userspace file operations
  155. * with ISC operations
  156. * @awb_lock: lock for serializing awb work queue operations
  157. * with DMA/buffer operations
  158. *
  159. * @pipeline: configuration of the ISC pipeline
  160. *
  161. * @current_subdev: current subdevice: the sensor
  162. * @subdev_entities: list of subdevice entitites
  163. */
  164. struct isc_device {
  165. struct regmap *regmap;
  166. struct clk *hclock;
  167. struct clk *ispck;
  168. struct isc_clk isc_clks[2];
  169. struct device *dev;
  170. struct v4l2_device v4l2_dev;
  171. struct video_device video_dev;
  172. struct vb2_queue vb2_vidq;
  173. spinlock_t dma_queue_lock; /* serialize access to dma queue */
  174. struct list_head dma_queue;
  175. struct isc_buffer *cur_frm;
  176. unsigned int sequence;
  177. bool stop;
  178. struct completion comp;
  179. struct v4l2_format fmt;
  180. struct isc_format **user_formats;
  181. unsigned int num_user_formats;
  182. struct fmt_config config;
  183. struct fmt_config try_config;
  184. struct isc_ctrls ctrls;
  185. struct v4l2_ctrl *do_wb_ctrl;
  186. struct work_struct awb_work;
  187. struct mutex lock; /* serialize access to file operations */
  188. spinlock_t awb_lock; /* serialize access to DMA buffers from awb work queue */
  189. struct regmap_field *pipeline[ISC_PIPE_LINE_NODE_NUM];
  190. struct isc_subdev_entity *current_subdev;
  191. struct list_head subdev_entities;
  192. };
  193. #define GAMMA_MAX 2
  194. #define GAMMA_ENTRIES 64
  195. #define ATMEL_ISC_NAME "atmel-isc"
  196. extern struct isc_format formats_list[];
  197. extern const struct isc_format controller_formats[];
  198. extern const u32 isc_gamma_table[GAMMA_MAX + 1][GAMMA_ENTRIES];
  199. extern const struct regmap_config isc_regmap_config;
  200. extern const struct v4l2_async_notifier_operations isc_async_ops;
  201. irqreturn_t isc_interrupt(int irq, void *dev_id);
  202. int isc_pipeline_init(struct isc_device *isc);
  203. int isc_clk_init(struct isc_device *isc);
  204. void isc_subdev_cleanup(struct isc_device *isc);
  205. void isc_clk_cleanup(struct isc_device *isc);
  206. #endif