tc90522.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Toshiba TC90522 Demodulator
  4. *
  5. * Copyright (C) 2014 Akihiro Tsukada <tskd08@gmail.com>
  6. */
  7. /*
  8. * NOTICE:
  9. * This driver is incomplete and lacks init/config of the chips,
  10. * as the necessary info is not disclosed.
  11. * It assumes that users of this driver (such as a PCI bridge of
  12. * DTV receiver cards) properly init and configure the chip
  13. * via I2C *before* calling this driver's init() function.
  14. *
  15. * Currently, PT3 driver is the only one that uses this driver,
  16. * and contains init/config code in its firmware.
  17. * Thus some part of the code might be dependent on PT3 specific config.
  18. */
  19. #include <linux/kernel.h>
  20. #include <linux/math64.h>
  21. #include <linux/dvb/frontend.h>
  22. #include <media/dvb_math.h>
  23. #include "tc90522.h"
  24. #define TC90522_I2C_THRU_REG 0xfe
  25. #define TC90522_MODULE_IDX(addr) (((u8)(addr) & 0x02U) >> 1)
  26. struct tc90522_state {
  27. struct tc90522_config cfg;
  28. struct dvb_frontend fe;
  29. struct i2c_client *i2c_client;
  30. struct i2c_adapter tuner_i2c;
  31. bool lna;
  32. };
  33. struct reg_val {
  34. u8 reg;
  35. u8 val;
  36. };
  37. static int
  38. reg_write(struct tc90522_state *state, const struct reg_val *regs, int num)
  39. {
  40. int i, ret;
  41. struct i2c_msg msg;
  42. ret = 0;
  43. msg.addr = state->i2c_client->addr;
  44. msg.flags = 0;
  45. msg.len = 2;
  46. for (i = 0; i < num; i++) {
  47. msg.buf = (u8 *)&regs[i];
  48. ret = i2c_transfer(state->i2c_client->adapter, &msg, 1);
  49. if (ret == 0)
  50. ret = -EIO;
  51. if (ret < 0)
  52. return ret;
  53. }
  54. return 0;
  55. }
  56. static int reg_read(struct tc90522_state *state, u8 reg, u8 *val, u8 len)
  57. {
  58. struct i2c_msg msgs[2] = {
  59. {
  60. .addr = state->i2c_client->addr,
  61. .flags = 0,
  62. .buf = &reg,
  63. .len = 1,
  64. },
  65. {
  66. .addr = state->i2c_client->addr,
  67. .flags = I2C_M_RD,
  68. .buf = val,
  69. .len = len,
  70. },
  71. };
  72. int ret;
  73. ret = i2c_transfer(state->i2c_client->adapter, msgs, ARRAY_SIZE(msgs));
  74. if (ret == ARRAY_SIZE(msgs))
  75. ret = 0;
  76. else if (ret >= 0)
  77. ret = -EIO;
  78. return ret;
  79. }
  80. static struct tc90522_state *cfg_to_state(struct tc90522_config *c)
  81. {
  82. return container_of(c, struct tc90522_state, cfg);
  83. }
  84. static int tc90522s_set_tsid(struct dvb_frontend *fe)
  85. {
  86. struct reg_val set_tsid[] = {
  87. { 0x8f, 00 },
  88. { 0x90, 00 }
  89. };
  90. set_tsid[0].val = (fe->dtv_property_cache.stream_id & 0xff00) >> 8;
  91. set_tsid[1].val = fe->dtv_property_cache.stream_id & 0xff;
  92. return reg_write(fe->demodulator_priv, set_tsid, ARRAY_SIZE(set_tsid));
  93. }
  94. static int tc90522t_set_layers(struct dvb_frontend *fe)
  95. {
  96. struct reg_val rv;
  97. u8 laysel;
  98. laysel = ~fe->dtv_property_cache.isdbt_layer_enabled & 0x07;
  99. laysel = (laysel & 0x01) << 2 | (laysel & 0x02) | (laysel & 0x04) >> 2;
  100. rv.reg = 0x71;
  101. rv.val = laysel;
  102. return reg_write(fe->demodulator_priv, &rv, 1);
  103. }
  104. /* frontend ops */
  105. static int tc90522s_read_status(struct dvb_frontend *fe, enum fe_status *status)
  106. {
  107. struct tc90522_state *state;
  108. int ret;
  109. u8 reg;
  110. state = fe->demodulator_priv;
  111. ret = reg_read(state, 0xc3, &reg, 1);
  112. if (ret < 0)
  113. return ret;
  114. *status = 0;
  115. if (reg & 0x80) /* input level under min ? */
  116. return 0;
  117. *status |= FE_HAS_SIGNAL;
  118. if (reg & 0x60) /* carrier? */
  119. return 0;
  120. *status |= FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC;
  121. if (reg & 0x10)
  122. return 0;
  123. if (reg_read(state, 0xc5, &reg, 1) < 0 || !(reg & 0x03))
  124. return 0;
  125. *status |= FE_HAS_LOCK;
  126. return 0;
  127. }
  128. static int tc90522t_read_status(struct dvb_frontend *fe, enum fe_status *status)
  129. {
  130. struct tc90522_state *state;
  131. int ret;
  132. u8 reg;
  133. state = fe->demodulator_priv;
  134. ret = reg_read(state, 0x96, &reg, 1);
  135. if (ret < 0)
  136. return ret;
  137. *status = 0;
  138. if (reg & 0xe0) {
  139. *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI
  140. | FE_HAS_SYNC | FE_HAS_LOCK;
  141. return 0;
  142. }
  143. ret = reg_read(state, 0x80, &reg, 1);
  144. if (ret < 0)
  145. return ret;
  146. if (reg & 0xf0)
  147. return 0;
  148. *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER;
  149. if (reg & 0x0c)
  150. return 0;
  151. *status |= FE_HAS_SYNC | FE_HAS_VITERBI;
  152. if (reg & 0x02)
  153. return 0;
  154. *status |= FE_HAS_LOCK;
  155. return 0;
  156. }
  157. static const enum fe_code_rate fec_conv_sat[] = {
  158. FEC_NONE, /* unused */
  159. FEC_1_2, /* for BPSK */
  160. FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_7_8, /* for QPSK */
  161. FEC_2_3, /* for 8PSK. (trellis code) */
  162. };
  163. static int tc90522s_get_frontend(struct dvb_frontend *fe,
  164. struct dtv_frontend_properties *c)
  165. {
  166. struct tc90522_state *state;
  167. struct dtv_fe_stats *stats;
  168. int ret, i;
  169. int layers;
  170. u8 val[10];
  171. u32 cndat;
  172. state = fe->demodulator_priv;
  173. c->delivery_system = SYS_ISDBS;
  174. c->symbol_rate = 28860000;
  175. layers = 0;
  176. ret = reg_read(state, 0xe6, val, 5);
  177. if (ret == 0) {
  178. u8 v;
  179. c->stream_id = val[0] << 8 | val[1];
  180. /* high/single layer */
  181. v = (val[2] & 0x70) >> 4;
  182. c->modulation = (v == 7) ? PSK_8 : QPSK;
  183. c->fec_inner = fec_conv_sat[v];
  184. c->layer[0].fec = c->fec_inner;
  185. c->layer[0].modulation = c->modulation;
  186. c->layer[0].segment_count = val[3] & 0x3f; /* slots */
  187. /* low layer */
  188. v = (val[2] & 0x07);
  189. c->layer[1].fec = fec_conv_sat[v];
  190. if (v == 0) /* no low layer */
  191. c->layer[1].segment_count = 0;
  192. else
  193. c->layer[1].segment_count = val[4] & 0x3f; /* slots */
  194. /*
  195. * actually, BPSK if v==1, but not defined in
  196. * enum fe_modulation
  197. */
  198. c->layer[1].modulation = QPSK;
  199. layers = (v > 0) ? 2 : 1;
  200. }
  201. /* statistics */
  202. stats = &c->strength;
  203. stats->len = 0;
  204. /* let the connected tuner set RSSI property cache */
  205. if (fe->ops.tuner_ops.get_rf_strength) {
  206. u16 dummy;
  207. fe->ops.tuner_ops.get_rf_strength(fe, &dummy);
  208. }
  209. stats = &c->cnr;
  210. stats->len = 1;
  211. stats->stat[0].scale = FE_SCALE_NOT_AVAILABLE;
  212. cndat = 0;
  213. ret = reg_read(state, 0xbc, val, 2);
  214. if (ret == 0)
  215. cndat = val[0] << 8 | val[1];
  216. if (cndat >= 3000) {
  217. u32 p, p4;
  218. s64 cn;
  219. cndat -= 3000; /* cndat: 4.12 fixed point float */
  220. /*
  221. * cnr[mdB] = -1634.6 * P^5 + 14341 * P^4 - 50259 * P^3
  222. * + 88977 * P^2 - 89565 * P + 58857
  223. * (P = sqrt(cndat) / 64)
  224. */
  225. /* p := sqrt(cndat) << 8 = P << 14, 2.14 fixed point float */
  226. /* cn = cnr << 3 */
  227. p = int_sqrt(cndat << 16);
  228. p4 = cndat * cndat;
  229. cn = div64_s64(-16346LL * p4 * p, 10) >> 35;
  230. cn += (14341LL * p4) >> 21;
  231. cn -= (50259LL * cndat * p) >> 23;
  232. cn += (88977LL * cndat) >> 9;
  233. cn -= (89565LL * p) >> 11;
  234. cn += 58857 << 3;
  235. stats->stat[0].svalue = cn >> 3;
  236. stats->stat[0].scale = FE_SCALE_DECIBEL;
  237. }
  238. /* per-layer post viterbi BER (or PER? config dependent?) */
  239. stats = &c->post_bit_error;
  240. memset(stats, 0, sizeof(*stats));
  241. stats->len = layers;
  242. ret = reg_read(state, 0xeb, val, 10);
  243. if (ret < 0)
  244. for (i = 0; i < layers; i++)
  245. stats->stat[i].scale = FE_SCALE_NOT_AVAILABLE;
  246. else {
  247. for (i = 0; i < layers; i++) {
  248. stats->stat[i].scale = FE_SCALE_COUNTER;
  249. stats->stat[i].uvalue = val[i * 5] << 16
  250. | val[i * 5 + 1] << 8 | val[i * 5 + 2];
  251. }
  252. }
  253. stats = &c->post_bit_count;
  254. memset(stats, 0, sizeof(*stats));
  255. stats->len = layers;
  256. if (ret < 0)
  257. for (i = 0; i < layers; i++)
  258. stats->stat[i].scale = FE_SCALE_NOT_AVAILABLE;
  259. else {
  260. for (i = 0; i < layers; i++) {
  261. stats->stat[i].scale = FE_SCALE_COUNTER;
  262. stats->stat[i].uvalue =
  263. val[i * 5 + 3] << 8 | val[i * 5 + 4];
  264. stats->stat[i].uvalue *= 204 * 8;
  265. }
  266. }
  267. return 0;
  268. }
  269. static const enum fe_transmit_mode tm_conv[] = {
  270. TRANSMISSION_MODE_2K,
  271. TRANSMISSION_MODE_4K,
  272. TRANSMISSION_MODE_8K,
  273. 0
  274. };
  275. static const enum fe_code_rate fec_conv_ter[] = {
  276. FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_7_8, 0, 0, 0
  277. };
  278. static const enum fe_modulation mod_conv[] = {
  279. DQPSK, QPSK, QAM_16, QAM_64, 0, 0, 0, 0
  280. };
  281. static int tc90522t_get_frontend(struct dvb_frontend *fe,
  282. struct dtv_frontend_properties *c)
  283. {
  284. struct tc90522_state *state;
  285. struct dtv_fe_stats *stats;
  286. int ret, i;
  287. int layers;
  288. u8 val[15], mode;
  289. u32 cndat;
  290. state = fe->demodulator_priv;
  291. c->delivery_system = SYS_ISDBT;
  292. c->bandwidth_hz = 6000000;
  293. mode = 1;
  294. ret = reg_read(state, 0xb0, val, 1);
  295. if (ret == 0) {
  296. mode = (val[0] & 0xc0) >> 6;
  297. c->transmission_mode = tm_conv[mode];
  298. c->guard_interval = (val[0] & 0x30) >> 4;
  299. }
  300. ret = reg_read(state, 0xb2, val, 6);
  301. layers = 0;
  302. if (ret == 0) {
  303. u8 v;
  304. c->isdbt_partial_reception = val[0] & 0x01;
  305. c->isdbt_sb_mode = (val[0] & 0xc0) == 0x40;
  306. /* layer A */
  307. v = (val[2] & 0x78) >> 3;
  308. if (v == 0x0f)
  309. c->layer[0].segment_count = 0;
  310. else {
  311. layers++;
  312. c->layer[0].segment_count = v;
  313. c->layer[0].fec = fec_conv_ter[(val[1] & 0x1c) >> 2];
  314. c->layer[0].modulation = mod_conv[(val[1] & 0xe0) >> 5];
  315. v = (val[1] & 0x03) << 1 | (val[2] & 0x80) >> 7;
  316. c->layer[0].interleaving = v;
  317. }
  318. /* layer B */
  319. v = (val[3] & 0x03) << 2 | (val[4] & 0xc0) >> 6;
  320. if (v == 0x0f)
  321. c->layer[1].segment_count = 0;
  322. else {
  323. layers++;
  324. c->layer[1].segment_count = v;
  325. c->layer[1].fec = fec_conv_ter[(val[3] & 0xe0) >> 5];
  326. c->layer[1].modulation = mod_conv[(val[2] & 0x07)];
  327. c->layer[1].interleaving = (val[3] & 0x1c) >> 2;
  328. }
  329. /* layer C */
  330. v = (val[5] & 0x1e) >> 1;
  331. if (v == 0x0f)
  332. c->layer[2].segment_count = 0;
  333. else {
  334. layers++;
  335. c->layer[2].segment_count = v;
  336. c->layer[2].fec = fec_conv_ter[(val[4] & 0x07)];
  337. c->layer[2].modulation = mod_conv[(val[4] & 0x38) >> 3];
  338. c->layer[2].interleaving = (val[5] & 0xe0) >> 5;
  339. }
  340. }
  341. /* statistics */
  342. stats = &c->strength;
  343. stats->len = 0;
  344. /* let the connected tuner set RSSI property cache */
  345. if (fe->ops.tuner_ops.get_rf_strength) {
  346. u16 dummy;
  347. fe->ops.tuner_ops.get_rf_strength(fe, &dummy);
  348. }
  349. stats = &c->cnr;
  350. stats->len = 1;
  351. stats->stat[0].scale = FE_SCALE_NOT_AVAILABLE;
  352. cndat = 0;
  353. ret = reg_read(state, 0x8b, val, 3);
  354. if (ret == 0)
  355. cndat = val[0] << 16 | val[1] << 8 | val[2];
  356. if (cndat != 0) {
  357. u32 p, tmp;
  358. s64 cn;
  359. /*
  360. * cnr[mdB] = 0.024 P^4 - 1.6 P^3 + 39.8 P^2 + 549.1 P + 3096.5
  361. * (P = 10log10(5505024/cndat))
  362. */
  363. /* cn = cnr << 3 (61.3 fixed point float */
  364. /* p = 10log10(5505024/cndat) << 24 (8.24 fixed point float)*/
  365. p = intlog10(5505024) - intlog10(cndat);
  366. p *= 10;
  367. cn = 24772;
  368. cn += div64_s64(43827LL * p, 10) >> 24;
  369. tmp = p >> 8;
  370. cn += div64_s64(3184LL * tmp * tmp, 10) >> 32;
  371. tmp = p >> 13;
  372. cn -= div64_s64(128LL * tmp * tmp * tmp, 10) >> 33;
  373. tmp = p >> 18;
  374. cn += div64_s64(192LL * tmp * tmp * tmp * tmp, 1000) >> 24;
  375. stats->stat[0].svalue = cn >> 3;
  376. stats->stat[0].scale = FE_SCALE_DECIBEL;
  377. }
  378. /* per-layer post viterbi BER (or PER? config dependent?) */
  379. stats = &c->post_bit_error;
  380. memset(stats, 0, sizeof(*stats));
  381. stats->len = layers;
  382. ret = reg_read(state, 0x9d, val, 15);
  383. if (ret < 0)
  384. for (i = 0; i < layers; i++)
  385. stats->stat[i].scale = FE_SCALE_NOT_AVAILABLE;
  386. else {
  387. for (i = 0; i < layers; i++) {
  388. stats->stat[i].scale = FE_SCALE_COUNTER;
  389. stats->stat[i].uvalue = val[i * 3] << 16
  390. | val[i * 3 + 1] << 8 | val[i * 3 + 2];
  391. }
  392. }
  393. stats = &c->post_bit_count;
  394. memset(stats, 0, sizeof(*stats));
  395. stats->len = layers;
  396. if (ret < 0)
  397. for (i = 0; i < layers; i++)
  398. stats->stat[i].scale = FE_SCALE_NOT_AVAILABLE;
  399. else {
  400. for (i = 0; i < layers; i++) {
  401. stats->stat[i].scale = FE_SCALE_COUNTER;
  402. stats->stat[i].uvalue =
  403. val[9 + i * 2] << 8 | val[9 + i * 2 + 1];
  404. stats->stat[i].uvalue *= 204 * 8;
  405. }
  406. }
  407. return 0;
  408. }
  409. static const struct reg_val reset_sat = { 0x03, 0x01 };
  410. static const struct reg_val reset_ter = { 0x01, 0x40 };
  411. static int tc90522_set_frontend(struct dvb_frontend *fe)
  412. {
  413. struct tc90522_state *state;
  414. int ret;
  415. state = fe->demodulator_priv;
  416. if (fe->ops.tuner_ops.set_params)
  417. ret = fe->ops.tuner_ops.set_params(fe);
  418. else
  419. ret = -ENODEV;
  420. if (ret < 0)
  421. goto failed;
  422. if (fe->ops.delsys[0] == SYS_ISDBS) {
  423. ret = tc90522s_set_tsid(fe);
  424. if (ret < 0)
  425. goto failed;
  426. ret = reg_write(state, &reset_sat, 1);
  427. } else {
  428. ret = tc90522t_set_layers(fe);
  429. if (ret < 0)
  430. goto failed;
  431. ret = reg_write(state, &reset_ter, 1);
  432. }
  433. if (ret < 0)
  434. goto failed;
  435. return 0;
  436. failed:
  437. dev_warn(&state->tuner_i2c.dev, "(%s) failed. [adap%d-fe%d]\n",
  438. __func__, fe->dvb->num, fe->id);
  439. return ret;
  440. }
  441. static int tc90522_get_tune_settings(struct dvb_frontend *fe,
  442. struct dvb_frontend_tune_settings *settings)
  443. {
  444. if (fe->ops.delsys[0] == SYS_ISDBS) {
  445. settings->min_delay_ms = 250;
  446. settings->step_size = 1000;
  447. settings->max_drift = settings->step_size * 2;
  448. } else {
  449. settings->min_delay_ms = 400;
  450. settings->step_size = 142857;
  451. settings->max_drift = settings->step_size;
  452. }
  453. return 0;
  454. }
  455. static int tc90522_set_if_agc(struct dvb_frontend *fe, bool on)
  456. {
  457. struct reg_val agc_sat[] = {
  458. { 0x0a, 0x00 },
  459. { 0x10, 0x30 },
  460. { 0x11, 0x00 },
  461. { 0x03, 0x01 },
  462. };
  463. struct reg_val agc_ter[] = {
  464. { 0x25, 0x00 },
  465. { 0x23, 0x4c },
  466. { 0x01, 0x40 },
  467. };
  468. struct tc90522_state *state;
  469. struct reg_val *rv;
  470. int num;
  471. state = fe->demodulator_priv;
  472. if (fe->ops.delsys[0] == SYS_ISDBS) {
  473. agc_sat[0].val = on ? 0xff : 0x00;
  474. agc_sat[1].val |= 0x80;
  475. agc_sat[1].val |= on ? 0x01 : 0x00;
  476. agc_sat[2].val |= on ? 0x40 : 0x00;
  477. rv = agc_sat;
  478. num = ARRAY_SIZE(agc_sat);
  479. } else {
  480. agc_ter[0].val = on ? 0x40 : 0x00;
  481. agc_ter[1].val |= on ? 0x00 : 0x01;
  482. rv = agc_ter;
  483. num = ARRAY_SIZE(agc_ter);
  484. }
  485. return reg_write(state, rv, num);
  486. }
  487. static const struct reg_val sleep_sat = { 0x17, 0x01 };
  488. static const struct reg_val sleep_ter = { 0x03, 0x90 };
  489. static int tc90522_sleep(struct dvb_frontend *fe)
  490. {
  491. struct tc90522_state *state;
  492. int ret;
  493. state = fe->demodulator_priv;
  494. if (fe->ops.delsys[0] == SYS_ISDBS)
  495. ret = reg_write(state, &sleep_sat, 1);
  496. else {
  497. ret = reg_write(state, &sleep_ter, 1);
  498. if (ret == 0 && fe->ops.set_lna &&
  499. fe->dtv_property_cache.lna == LNA_AUTO) {
  500. fe->dtv_property_cache.lna = 0;
  501. ret = fe->ops.set_lna(fe);
  502. fe->dtv_property_cache.lna = LNA_AUTO;
  503. }
  504. }
  505. if (ret < 0)
  506. dev_warn(&state->tuner_i2c.dev,
  507. "(%s) failed. [adap%d-fe%d]\n",
  508. __func__, fe->dvb->num, fe->id);
  509. return ret;
  510. }
  511. static const struct reg_val wakeup_sat = { 0x17, 0x00 };
  512. static const struct reg_val wakeup_ter = { 0x03, 0x80 };
  513. static int tc90522_init(struct dvb_frontend *fe)
  514. {
  515. struct tc90522_state *state;
  516. int ret;
  517. /*
  518. * Because the init sequence is not public,
  519. * the parent device/driver should have init'ed the device before.
  520. * just wake up the device here.
  521. */
  522. state = fe->demodulator_priv;
  523. if (fe->ops.delsys[0] == SYS_ISDBS)
  524. ret = reg_write(state, &wakeup_sat, 1);
  525. else {
  526. ret = reg_write(state, &wakeup_ter, 1);
  527. if (ret == 0 && fe->ops.set_lna &&
  528. fe->dtv_property_cache.lna == LNA_AUTO) {
  529. fe->dtv_property_cache.lna = 1;
  530. ret = fe->ops.set_lna(fe);
  531. fe->dtv_property_cache.lna = LNA_AUTO;
  532. }
  533. }
  534. if (ret < 0) {
  535. dev_warn(&state->tuner_i2c.dev,
  536. "(%s) failed. [adap%d-fe%d]\n",
  537. __func__, fe->dvb->num, fe->id);
  538. return ret;
  539. }
  540. /* prefer 'all-layers' to 'none' as a default */
  541. if (fe->dtv_property_cache.isdbt_layer_enabled == 0)
  542. fe->dtv_property_cache.isdbt_layer_enabled = 7;
  543. return tc90522_set_if_agc(fe, true);
  544. }
  545. /*
  546. * tuner I2C adapter functions
  547. */
  548. static int
  549. tc90522_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
  550. {
  551. struct tc90522_state *state;
  552. struct i2c_msg *new_msgs;
  553. int i, j;
  554. int ret, rd_num;
  555. u8 wbuf[256];
  556. u8 *p, *bufend;
  557. if (num <= 0)
  558. return -EINVAL;
  559. rd_num = 0;
  560. for (i = 0; i < num; i++)
  561. if (msgs[i].flags & I2C_M_RD)
  562. rd_num++;
  563. new_msgs = kmalloc_array(num + rd_num, sizeof(*new_msgs), GFP_KERNEL);
  564. if (!new_msgs)
  565. return -ENOMEM;
  566. state = i2c_get_adapdata(adap);
  567. p = wbuf;
  568. bufend = wbuf + sizeof(wbuf);
  569. for (i = 0, j = 0; i < num; i++, j++) {
  570. new_msgs[j].addr = state->i2c_client->addr;
  571. new_msgs[j].flags = msgs[i].flags;
  572. if (msgs[i].flags & I2C_M_RD) {
  573. new_msgs[j].flags &= ~I2C_M_RD;
  574. if (p + 2 > bufend)
  575. break;
  576. p[0] = TC90522_I2C_THRU_REG;
  577. p[1] = msgs[i].addr << 1 | 0x01;
  578. new_msgs[j].buf = p;
  579. new_msgs[j].len = 2;
  580. p += 2;
  581. j++;
  582. new_msgs[j].addr = state->i2c_client->addr;
  583. new_msgs[j].flags = msgs[i].flags;
  584. new_msgs[j].buf = msgs[i].buf;
  585. new_msgs[j].len = msgs[i].len;
  586. continue;
  587. }
  588. if (p + msgs[i].len + 2 > bufend)
  589. break;
  590. p[0] = TC90522_I2C_THRU_REG;
  591. p[1] = msgs[i].addr << 1;
  592. memcpy(p + 2, msgs[i].buf, msgs[i].len);
  593. new_msgs[j].buf = p;
  594. new_msgs[j].len = msgs[i].len + 2;
  595. p += new_msgs[j].len;
  596. }
  597. if (i < num)
  598. ret = -ENOMEM;
  599. else
  600. ret = i2c_transfer(state->i2c_client->adapter, new_msgs, j);
  601. if (ret >= 0 && ret < j)
  602. ret = -EIO;
  603. kfree(new_msgs);
  604. return (ret == j) ? num : ret;
  605. }
  606. static u32 tc90522_functionality(struct i2c_adapter *adap)
  607. {
  608. return I2C_FUNC_I2C;
  609. }
  610. static const struct i2c_algorithm tc90522_tuner_i2c_algo = {
  611. .master_xfer = &tc90522_master_xfer,
  612. .functionality = &tc90522_functionality,
  613. };
  614. /*
  615. * I2C driver functions
  616. */
  617. static const struct dvb_frontend_ops tc90522_ops_sat = {
  618. .delsys = { SYS_ISDBS },
  619. .info = {
  620. .name = "Toshiba TC90522 ISDB-S module",
  621. .frequency_min_hz = 950 * MHz,
  622. .frequency_max_hz = 2150 * MHz,
  623. .caps = FE_CAN_INVERSION_AUTO | FE_CAN_FEC_AUTO |
  624. FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO |
  625. FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO,
  626. },
  627. .init = tc90522_init,
  628. .sleep = tc90522_sleep,
  629. .set_frontend = tc90522_set_frontend,
  630. .get_tune_settings = tc90522_get_tune_settings,
  631. .get_frontend = tc90522s_get_frontend,
  632. .read_status = tc90522s_read_status,
  633. };
  634. static const struct dvb_frontend_ops tc90522_ops_ter = {
  635. .delsys = { SYS_ISDBT },
  636. .info = {
  637. .name = "Toshiba TC90522 ISDB-T module",
  638. .frequency_min_hz = 470 * MHz,
  639. .frequency_max_hz = 770 * MHz,
  640. .frequency_stepsize_hz = 142857,
  641. .caps = FE_CAN_INVERSION_AUTO |
  642. FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
  643. FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
  644. FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
  645. FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO |
  646. FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER |
  647. FE_CAN_HIERARCHY_AUTO,
  648. },
  649. .init = tc90522_init,
  650. .sleep = tc90522_sleep,
  651. .set_frontend = tc90522_set_frontend,
  652. .get_tune_settings = tc90522_get_tune_settings,
  653. .get_frontend = tc90522t_get_frontend,
  654. .read_status = tc90522t_read_status,
  655. };
  656. static int tc90522_probe(struct i2c_client *client,
  657. const struct i2c_device_id *id)
  658. {
  659. struct tc90522_state *state;
  660. struct tc90522_config *cfg;
  661. const struct dvb_frontend_ops *ops;
  662. struct i2c_adapter *adap;
  663. int ret;
  664. state = kzalloc(sizeof(*state), GFP_KERNEL);
  665. if (!state)
  666. return -ENOMEM;
  667. state->i2c_client = client;
  668. cfg = client->dev.platform_data;
  669. memcpy(&state->cfg, cfg, sizeof(state->cfg));
  670. cfg->fe = state->cfg.fe = &state->fe;
  671. ops = id->driver_data == 0 ? &tc90522_ops_sat : &tc90522_ops_ter;
  672. memcpy(&state->fe.ops, ops, sizeof(*ops));
  673. state->fe.demodulator_priv = state;
  674. adap = &state->tuner_i2c;
  675. adap->owner = THIS_MODULE;
  676. adap->algo = &tc90522_tuner_i2c_algo;
  677. adap->dev.parent = &client->dev;
  678. strscpy(adap->name, "tc90522_sub", sizeof(adap->name));
  679. i2c_set_adapdata(adap, state);
  680. ret = i2c_add_adapter(adap);
  681. if (ret < 0)
  682. goto free_state;
  683. cfg->tuner_i2c = state->cfg.tuner_i2c = adap;
  684. i2c_set_clientdata(client, &state->cfg);
  685. dev_info(&client->dev, "Toshiba TC90522 attached.\n");
  686. return 0;
  687. free_state:
  688. kfree(state);
  689. return ret;
  690. }
  691. static int tc90522_remove(struct i2c_client *client)
  692. {
  693. struct tc90522_state *state;
  694. state = cfg_to_state(i2c_get_clientdata(client));
  695. i2c_del_adapter(&state->tuner_i2c);
  696. kfree(state);
  697. return 0;
  698. }
  699. static const struct i2c_device_id tc90522_id[] = {
  700. { TC90522_I2C_DEV_SAT, 0 },
  701. { TC90522_I2C_DEV_TER, 1 },
  702. {}
  703. };
  704. MODULE_DEVICE_TABLE(i2c, tc90522_id);
  705. static struct i2c_driver tc90522_driver = {
  706. .driver = {
  707. .name = "tc90522",
  708. },
  709. .probe = tc90522_probe,
  710. .remove = tc90522_remove,
  711. .id_table = tc90522_id,
  712. };
  713. module_i2c_driver(tc90522_driver);
  714. MODULE_DESCRIPTION("Toshiba TC90522 frontend");
  715. MODULE_AUTHOR("Akihiro TSUKADA");
  716. MODULE_LICENSE("GPL");