stv0367.c 88 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * stv0367.c
  4. *
  5. * Driver for ST STV0367 DVB-T & DVB-C demodulator IC.
  6. *
  7. * Copyright (C) ST Microelectronics.
  8. * Copyright (C) 2010,2011 NetUP Inc.
  9. * Copyright (C) 2010,2011 Igor M. Liplianin <liplianin@netup.ru>
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/string.h>
  14. #include <linux/slab.h>
  15. #include <linux/i2c.h>
  16. #include <media/dvb_math.h>
  17. #include "stv0367.h"
  18. #include "stv0367_defs.h"
  19. #include "stv0367_regs.h"
  20. #include "stv0367_priv.h"
  21. /* Max transfer size done by I2C transfer functions */
  22. #define MAX_XFER_SIZE 64
  23. static int stvdebug;
  24. module_param_named(debug, stvdebug, int, 0644);
  25. static int i2cdebug;
  26. module_param_named(i2c_debug, i2cdebug, int, 0644);
  27. #define dprintk(args...) \
  28. do { \
  29. if (stvdebug) \
  30. printk(KERN_DEBUG args); \
  31. } while (0)
  32. /* DVB-C */
  33. enum active_demod_state { demod_none, demod_ter, demod_cab };
  34. struct stv0367cab_state {
  35. enum stv0367_cab_signal_type state;
  36. u32 mclk;
  37. u32 adc_clk;
  38. s32 search_range;
  39. s32 derot_offset;
  40. /* results */
  41. int locked; /* channel found */
  42. u32 freq_khz; /* found frequency (in kHz) */
  43. u32 symbol_rate; /* found symbol rate (in Bds) */
  44. enum fe_spectral_inversion spect_inv; /* Spectrum Inversion */
  45. u32 qamfec_status_reg; /* status reg to poll for FEC Lock */
  46. };
  47. struct stv0367ter_state {
  48. /* DVB-T */
  49. enum stv0367_ter_signal_type state;
  50. enum stv0367_ter_if_iq_mode if_iq_mode;
  51. enum stv0367_ter_mode mode;/* mode 2K or 8K */
  52. enum fe_guard_interval guard;
  53. enum stv0367_ter_hierarchy hierarchy;
  54. u32 frequency;
  55. enum fe_spectral_inversion sense; /* current search spectrum */
  56. u8 force; /* force mode/guard */
  57. u8 bw; /* channel width 6, 7 or 8 in MHz */
  58. u8 pBW; /* channel width used during previous lock */
  59. u32 pBER;
  60. u32 pPER;
  61. u32 ucblocks;
  62. s8 echo_pos; /* echo position */
  63. u8 first_lock;
  64. u8 unlock_counter;
  65. u32 agc_val;
  66. };
  67. struct stv0367_state {
  68. struct dvb_frontend fe;
  69. struct i2c_adapter *i2c;
  70. /* config settings */
  71. const struct stv0367_config *config;
  72. u8 chip_id;
  73. /* DVB-C */
  74. struct stv0367cab_state *cab_state;
  75. /* DVB-T */
  76. struct stv0367ter_state *ter_state;
  77. /* flags for operation control */
  78. u8 use_i2c_gatectrl;
  79. u8 deftabs;
  80. u8 reinit_on_setfrontend;
  81. u8 auto_if_khz;
  82. enum active_demod_state activedemod;
  83. };
  84. #define RF_LOOKUP_TABLE_SIZE 31
  85. #define RF_LOOKUP_TABLE2_SIZE 16
  86. /* RF Level (for RF AGC->AGC1) Lookup Table, depends on the board and tuner.*/
  87. static const s32 stv0367cab_RF_LookUp1[RF_LOOKUP_TABLE_SIZE][RF_LOOKUP_TABLE_SIZE] = {
  88. {/*AGC1*/
  89. 48, 50, 51, 53, 54, 56, 57, 58, 60, 61, 62, 63,
  90. 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,
  91. 76, 77, 78, 80, 83, 85, 88,
  92. }, {/*RF(dbm)*/
  93. 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
  94. 34, 35, 36, 37, 38, 39, 41, 42, 43, 44, 46, 47,
  95. 49, 50, 52, 53, 54, 55, 56,
  96. }
  97. };
  98. /* RF Level (for IF AGC->AGC2) Lookup Table, depends on the board and tuner.*/
  99. static const s32 stv0367cab_RF_LookUp2[RF_LOOKUP_TABLE2_SIZE][RF_LOOKUP_TABLE2_SIZE] = {
  100. {/*AGC2*/
  101. 28, 29, 31, 32, 34, 35, 36, 37,
  102. 38, 39, 40, 41, 42, 43, 44, 45,
  103. }, {/*RF(dbm)*/
  104. 57, 58, 59, 60, 61, 62, 63, 64,
  105. 65, 66, 67, 68, 69, 70, 71, 72,
  106. }
  107. };
  108. static
  109. int stv0367_writeregs(struct stv0367_state *state, u16 reg, u8 *data, int len)
  110. {
  111. u8 buf[MAX_XFER_SIZE];
  112. struct i2c_msg msg = {
  113. .addr = state->config->demod_address,
  114. .flags = 0,
  115. .buf = buf,
  116. .len = len + 2
  117. };
  118. int ret;
  119. if (2 + len > sizeof(buf)) {
  120. printk(KERN_WARNING
  121. "%s: i2c wr reg=%04x: len=%d is too big!\n",
  122. KBUILD_MODNAME, reg, len);
  123. return -EINVAL;
  124. }
  125. buf[0] = MSB(reg);
  126. buf[1] = LSB(reg);
  127. memcpy(buf + 2, data, len);
  128. if (i2cdebug)
  129. printk(KERN_DEBUG "%s: [%02x] %02x: %02x\n", __func__,
  130. state->config->demod_address, reg, buf[2]);
  131. ret = i2c_transfer(state->i2c, &msg, 1);
  132. if (ret != 1)
  133. printk(KERN_ERR "%s: i2c write error! ([%02x] %02x: %02x)\n",
  134. __func__, state->config->demod_address, reg, buf[2]);
  135. return (ret != 1) ? -EREMOTEIO : 0;
  136. }
  137. static int stv0367_writereg(struct stv0367_state *state, u16 reg, u8 data)
  138. {
  139. u8 tmp = data; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
  140. return stv0367_writeregs(state, reg, &tmp, 1);
  141. }
  142. static u8 stv0367_readreg(struct stv0367_state *state, u16 reg)
  143. {
  144. u8 b0[] = { 0, 0 };
  145. u8 b1[] = { 0 };
  146. struct i2c_msg msg[] = {
  147. {
  148. .addr = state->config->demod_address,
  149. .flags = 0,
  150. .buf = b0,
  151. .len = 2
  152. }, {
  153. .addr = state->config->demod_address,
  154. .flags = I2C_M_RD,
  155. .buf = b1,
  156. .len = 1
  157. }
  158. };
  159. int ret;
  160. b0[0] = MSB(reg);
  161. b0[1] = LSB(reg);
  162. ret = i2c_transfer(state->i2c, msg, 2);
  163. if (ret != 2)
  164. printk(KERN_ERR "%s: i2c read error ([%02x] %02x: %02x)\n",
  165. __func__, state->config->demod_address, reg, b1[0]);
  166. if (i2cdebug)
  167. printk(KERN_DEBUG "%s: [%02x] %02x: %02x\n", __func__,
  168. state->config->demod_address, reg, b1[0]);
  169. return b1[0];
  170. }
  171. static void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
  172. {
  173. u8 position = 0, i = 0;
  174. (*mask) = label & 0xff;
  175. while ((position == 0) && (i < 8)) {
  176. position = ((*mask) >> i) & 0x01;
  177. i++;
  178. }
  179. (*pos) = (i - 1);
  180. }
  181. static void stv0367_writebits(struct stv0367_state *state, u32 label, u8 val)
  182. {
  183. u8 reg, mask, pos;
  184. reg = stv0367_readreg(state, (label >> 16) & 0xffff);
  185. extract_mask_pos(label, &mask, &pos);
  186. val = mask & (val << pos);
  187. reg = (reg & (~mask)) | val;
  188. stv0367_writereg(state, (label >> 16) & 0xffff, reg);
  189. }
  190. static void stv0367_setbits(u8 *reg, u32 label, u8 val)
  191. {
  192. u8 mask, pos;
  193. extract_mask_pos(label, &mask, &pos);
  194. val = mask & (val << pos);
  195. (*reg) = ((*reg) & (~mask)) | val;
  196. }
  197. static u8 stv0367_readbits(struct stv0367_state *state, u32 label)
  198. {
  199. u8 val = 0xff;
  200. u8 mask, pos;
  201. extract_mask_pos(label, &mask, &pos);
  202. val = stv0367_readreg(state, label >> 16);
  203. val = (val & mask) >> pos;
  204. return val;
  205. }
  206. #if 0 /* Currently, unused */
  207. static u8 stv0367_getbits(u8 reg, u32 label)
  208. {
  209. u8 mask, pos;
  210. extract_mask_pos(label, &mask, &pos);
  211. return (reg & mask) >> pos;
  212. }
  213. #endif
  214. static void stv0367_write_table(struct stv0367_state *state,
  215. const struct st_register *deftab)
  216. {
  217. int i = 0;
  218. while (1) {
  219. if (!deftab[i].addr)
  220. break;
  221. stv0367_writereg(state, deftab[i].addr, deftab[i].value);
  222. i++;
  223. }
  224. }
  225. static void stv0367_pll_setup(struct stv0367_state *state,
  226. u32 icspeed, u32 xtal)
  227. {
  228. /* note on regs: R367TER_* and R367CAB_* defines each point to
  229. * 0xf0d8, so just use R367TER_ for both cases
  230. */
  231. switch (icspeed) {
  232. case STV0367_ICSPEED_58000:
  233. switch (xtal) {
  234. default:
  235. case 27000000:
  236. dprintk("STV0367 SetCLKgen for 58MHz IC and 27Mhz crystal\n");
  237. /* PLLMDIV: 27, PLLNDIV: 232 */
  238. stv0367_writereg(state, R367TER_PLLMDIV, 0x1b);
  239. stv0367_writereg(state, R367TER_PLLNDIV, 0xe8);
  240. break;
  241. }
  242. break;
  243. default:
  244. case STV0367_ICSPEED_53125:
  245. switch (xtal) {
  246. /* set internal freq to 53.125MHz */
  247. case 16000000:
  248. stv0367_writereg(state, R367TER_PLLMDIV, 0x2);
  249. stv0367_writereg(state, R367TER_PLLNDIV, 0x1b);
  250. break;
  251. case 25000000:
  252. stv0367_writereg(state, R367TER_PLLMDIV, 0xa);
  253. stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
  254. break;
  255. default:
  256. case 27000000:
  257. dprintk("FE_STV0367TER_SetCLKgen for 27Mhz\n");
  258. stv0367_writereg(state, R367TER_PLLMDIV, 0x1);
  259. stv0367_writereg(state, R367TER_PLLNDIV, 0x8);
  260. break;
  261. case 30000000:
  262. stv0367_writereg(state, R367TER_PLLMDIV, 0xc);
  263. stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
  264. break;
  265. }
  266. }
  267. stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
  268. }
  269. static int stv0367_get_if_khz(struct stv0367_state *state, u32 *ifkhz)
  270. {
  271. if (state->auto_if_khz && state->fe.ops.tuner_ops.get_if_frequency) {
  272. state->fe.ops.tuner_ops.get_if_frequency(&state->fe, ifkhz);
  273. *ifkhz = *ifkhz / 1000; /* hz -> khz */
  274. } else
  275. *ifkhz = state->config->if_khz;
  276. return 0;
  277. }
  278. static int stv0367ter_gate_ctrl(struct dvb_frontend *fe, int enable)
  279. {
  280. struct stv0367_state *state = fe->demodulator_priv;
  281. u8 tmp = stv0367_readreg(state, R367TER_I2CRPT);
  282. dprintk("%s:\n", __func__);
  283. if (enable) {
  284. stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 0);
  285. stv0367_setbits(&tmp, F367TER_I2CT_ON, 1);
  286. } else {
  287. stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 1);
  288. stv0367_setbits(&tmp, F367TER_I2CT_ON, 0);
  289. }
  290. stv0367_writereg(state, R367TER_I2CRPT, tmp);
  291. return 0;
  292. }
  293. static u32 stv0367_get_tuner_freq(struct dvb_frontend *fe)
  294. {
  295. struct dvb_frontend_ops *frontend_ops = &fe->ops;
  296. struct dvb_tuner_ops *tuner_ops = &frontend_ops->tuner_ops;
  297. u32 freq = 0;
  298. int err = 0;
  299. dprintk("%s:\n", __func__);
  300. if (tuner_ops->get_frequency) {
  301. err = tuner_ops->get_frequency(fe, &freq);
  302. if (err < 0) {
  303. printk(KERN_ERR "%s: Invalid parameter\n", __func__);
  304. return err;
  305. }
  306. dprintk("%s: frequency=%d\n", __func__, freq);
  307. } else
  308. return -1;
  309. return freq;
  310. }
  311. static u16 CellsCoeffs_8MHz_367cofdm[3][6][5] = {
  312. {
  313. {0x10EF, 0xE205, 0x10EF, 0xCE49, 0x6DA7}, /* CELL 1 COEFFS 27M*/
  314. {0x2151, 0xc557, 0x2151, 0xc705, 0x6f93}, /* CELL 2 COEFFS */
  315. {0x2503, 0xc000, 0x2503, 0xc375, 0x7194}, /* CELL 3 COEFFS */
  316. {0x20E9, 0xca94, 0x20e9, 0xc153, 0x7194}, /* CELL 4 COEFFS */
  317. {0x06EF, 0xF852, 0x06EF, 0xC057, 0x7207}, /* CELL 5 COEFFS */
  318. {0x0000, 0x0ECC, 0x0ECC, 0x0000, 0x3647} /* CELL 6 COEFFS */
  319. }, {
  320. {0x10A0, 0xE2AF, 0x10A1, 0xCE76, 0x6D6D}, /* CELL 1 COEFFS 25M*/
  321. {0x20DC, 0xC676, 0x20D9, 0xC80A, 0x6F29},
  322. {0x2532, 0xC000, 0x251D, 0xC391, 0x706F},
  323. {0x1F7A, 0xCD2B, 0x2032, 0xC15E, 0x711F},
  324. {0x0698, 0xFA5E, 0x0568, 0xC059, 0x7193},
  325. {0x0000, 0x0918, 0x149C, 0x0000, 0x3642} /* CELL 6 COEFFS */
  326. }, {
  327. {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
  328. {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
  329. {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
  330. {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
  331. {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
  332. {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
  333. }
  334. };
  335. static u16 CellsCoeffs_7MHz_367cofdm[3][6][5] = {
  336. {
  337. {0x12CA, 0xDDAF, 0x12CA, 0xCCEB, 0x6FB1}, /* CELL 1 COEFFS 27M*/
  338. {0x2329, 0xC000, 0x2329, 0xC6B0, 0x725F}, /* CELL 2 COEFFS */
  339. {0x2394, 0xC000, 0x2394, 0xC2C7, 0x7410}, /* CELL 3 COEFFS */
  340. {0x251C, 0xC000, 0x251C, 0xC103, 0x74D9}, /* CELL 4 COEFFS */
  341. {0x0804, 0xF546, 0x0804, 0xC040, 0x7544}, /* CELL 5 COEFFS */
  342. {0x0000, 0x0CD9, 0x0CD9, 0x0000, 0x370A} /* CELL 6 COEFFS */
  343. }, {
  344. {0x1285, 0xDE47, 0x1285, 0xCD17, 0x6F76}, /*25M*/
  345. {0x234C, 0xC000, 0x2348, 0xC6DA, 0x7206},
  346. {0x23B4, 0xC000, 0x23AC, 0xC2DB, 0x73B3},
  347. {0x253D, 0xC000, 0x25B6, 0xC10B, 0x747F},
  348. {0x0721, 0xF79C, 0x065F, 0xC041, 0x74EB},
  349. {0x0000, 0x08FA, 0x1162, 0x0000, 0x36FF}
  350. }, {
  351. {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
  352. {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
  353. {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
  354. {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
  355. {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
  356. {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
  357. }
  358. };
  359. static u16 CellsCoeffs_6MHz_367cofdm[3][6][5] = {
  360. {
  361. {0x1699, 0xD5B8, 0x1699, 0xCBC3, 0x713B}, /* CELL 1 COEFFS 27M*/
  362. {0x2245, 0xC000, 0x2245, 0xC568, 0x74D5}, /* CELL 2 COEFFS */
  363. {0x227F, 0xC000, 0x227F, 0xC1FC, 0x76C6}, /* CELL 3 COEFFS */
  364. {0x235E, 0xC000, 0x235E, 0xC0A7, 0x778A}, /* CELL 4 COEFFS */
  365. {0x0ECB, 0xEA0B, 0x0ECB, 0xC027, 0x77DD}, /* CELL 5 COEFFS */
  366. {0x0000, 0x0B68, 0x0B68, 0x0000, 0xC89A}, /* CELL 6 COEFFS */
  367. }, {
  368. {0x1655, 0xD64E, 0x1658, 0xCBEF, 0x70FE}, /*25M*/
  369. {0x225E, 0xC000, 0x2256, 0xC589, 0x7489},
  370. {0x2293, 0xC000, 0x2295, 0xC209, 0x767E},
  371. {0x2377, 0xC000, 0x23AA, 0xC0AB, 0x7746},
  372. {0x0DC7, 0xEBC8, 0x0D07, 0xC027, 0x7799},
  373. {0x0000, 0x0888, 0x0E9C, 0x0000, 0x3757}
  374. }, {
  375. {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
  376. {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
  377. {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
  378. {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
  379. {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
  380. {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
  381. }
  382. };
  383. static u32 stv0367ter_get_mclk(struct stv0367_state *state, u32 ExtClk_Hz)
  384. {
  385. u32 mclk_Hz = 0; /* master clock frequency (Hz) */
  386. u32 m, n, p;
  387. dprintk("%s:\n", __func__);
  388. if (stv0367_readbits(state, F367TER_BYPASS_PLLXN) == 0) {
  389. n = (u32)stv0367_readbits(state, F367TER_PLL_NDIV);
  390. if (n == 0)
  391. n = n + 1;
  392. m = (u32)stv0367_readbits(state, F367TER_PLL_MDIV);
  393. if (m == 0)
  394. m = m + 1;
  395. p = (u32)stv0367_readbits(state, F367TER_PLL_PDIV);
  396. if (p > 5)
  397. p = 5;
  398. mclk_Hz = ((ExtClk_Hz / 2) * n) / (m * (1 << p));
  399. dprintk("N=%d M=%d P=%d mclk_Hz=%d ExtClk_Hz=%d\n",
  400. n, m, p, mclk_Hz, ExtClk_Hz);
  401. } else
  402. mclk_Hz = ExtClk_Hz;
  403. dprintk("%s: mclk_Hz=%d\n", __func__, mclk_Hz);
  404. return mclk_Hz;
  405. }
  406. static int stv0367ter_filt_coeff_init(struct stv0367_state *state,
  407. u16 CellsCoeffs[3][6][5], u32 DemodXtal)
  408. {
  409. int i, j, k, freq;
  410. dprintk("%s:\n", __func__);
  411. freq = stv0367ter_get_mclk(state, DemodXtal);
  412. if (freq == 53125000)
  413. k = 1; /* equivalent to Xtal 25M on 362*/
  414. else if (freq == 54000000)
  415. k = 0; /* equivalent to Xtal 27M on 362*/
  416. else if (freq == 52500000)
  417. k = 2; /* equivalent to Xtal 30M on 362*/
  418. else
  419. return 0;
  420. for (i = 1; i <= 6; i++) {
  421. stv0367_writebits(state, F367TER_IIR_CELL_NB, i - 1);
  422. for (j = 1; j <= 5; j++) {
  423. stv0367_writereg(state,
  424. (R367TER_IIRCX_COEFF1_MSB + 2 * (j - 1)),
  425. MSB(CellsCoeffs[k][i-1][j-1]));
  426. stv0367_writereg(state,
  427. (R367TER_IIRCX_COEFF1_LSB + 2 * (j - 1)),
  428. LSB(CellsCoeffs[k][i-1][j-1]));
  429. }
  430. }
  431. return 1;
  432. }
  433. static void stv0367ter_agc_iir_lock_detect_set(struct stv0367_state *state)
  434. {
  435. dprintk("%s:\n", __func__);
  436. stv0367_writebits(state, F367TER_LOCK_DETECT_LSB, 0x00);
  437. /* Lock detect 1 */
  438. stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x00);
  439. stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
  440. stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
  441. /* Lock detect 2 */
  442. stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x01);
  443. stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
  444. stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
  445. /* Lock detect 3 */
  446. stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x02);
  447. stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
  448. stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
  449. /* Lock detect 4 */
  450. stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x03);
  451. stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
  452. stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
  453. }
  454. static int stv0367_iir_filt_init(struct stv0367_state *state, u8 Bandwidth,
  455. u32 DemodXtalValue)
  456. {
  457. dprintk("%s:\n", __func__);
  458. stv0367_writebits(state, F367TER_NRST_IIR, 0);
  459. switch (Bandwidth) {
  460. case 6:
  461. if (!stv0367ter_filt_coeff_init(state,
  462. CellsCoeffs_6MHz_367cofdm,
  463. DemodXtalValue))
  464. return 0;
  465. break;
  466. case 7:
  467. if (!stv0367ter_filt_coeff_init(state,
  468. CellsCoeffs_7MHz_367cofdm,
  469. DemodXtalValue))
  470. return 0;
  471. break;
  472. case 8:
  473. if (!stv0367ter_filt_coeff_init(state,
  474. CellsCoeffs_8MHz_367cofdm,
  475. DemodXtalValue))
  476. return 0;
  477. break;
  478. default:
  479. return 0;
  480. }
  481. stv0367_writebits(state, F367TER_NRST_IIR, 1);
  482. return 1;
  483. }
  484. static void stv0367ter_agc_iir_rst(struct stv0367_state *state)
  485. {
  486. u8 com_n;
  487. dprintk("%s:\n", __func__);
  488. com_n = stv0367_readbits(state, F367TER_COM_N);
  489. stv0367_writebits(state, F367TER_COM_N, 0x07);
  490. stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x00);
  491. stv0367_writebits(state, F367TER_COM_AGC_ON, 0x00);
  492. stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x01);
  493. stv0367_writebits(state, F367TER_COM_AGC_ON, 0x01);
  494. stv0367_writebits(state, F367TER_COM_N, com_n);
  495. }
  496. static int stv0367ter_duration(s32 mode, int tempo1, int tempo2, int tempo3)
  497. {
  498. int local_tempo = 0;
  499. switch (mode) {
  500. case 0:
  501. local_tempo = tempo1;
  502. break;
  503. case 1:
  504. local_tempo = tempo2;
  505. break ;
  506. case 2:
  507. local_tempo = tempo3;
  508. break;
  509. default:
  510. break;
  511. }
  512. /* msleep(local_tempo); */
  513. return local_tempo;
  514. }
  515. static enum
  516. stv0367_ter_signal_type stv0367ter_check_syr(struct stv0367_state *state)
  517. {
  518. int wd = 100;
  519. unsigned short int SYR_var;
  520. s32 SYRStatus;
  521. dprintk("%s:\n", __func__);
  522. SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
  523. while ((!SYR_var) && (wd > 0)) {
  524. usleep_range(2000, 3000);
  525. wd -= 2;
  526. SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
  527. }
  528. if (!SYR_var)
  529. SYRStatus = FE_TER_NOSYMBOL;
  530. else
  531. SYRStatus = FE_TER_SYMBOLOK;
  532. dprintk("stv0367ter_check_syr SYRStatus %s\n",
  533. SYR_var == 0 ? "No Symbol" : "OK");
  534. return SYRStatus;
  535. }
  536. static enum
  537. stv0367_ter_signal_type stv0367ter_check_cpamp(struct stv0367_state *state,
  538. s32 FFTmode)
  539. {
  540. s32 CPAMPvalue = 0, CPAMPStatus, CPAMPMin;
  541. int wd = 0;
  542. dprintk("%s:\n", __func__);
  543. switch (FFTmode) {
  544. case 0: /*2k mode*/
  545. CPAMPMin = 20;
  546. wd = 10;
  547. break;
  548. case 1: /*8k mode*/
  549. CPAMPMin = 80;
  550. wd = 55;
  551. break;
  552. case 2: /*4k mode*/
  553. CPAMPMin = 40;
  554. wd = 30;
  555. break;
  556. default:
  557. CPAMPMin = 0xffff; /*drives to NOCPAMP */
  558. break;
  559. }
  560. dprintk("%s: CPAMPMin=%d wd=%d\n", __func__, CPAMPMin, wd);
  561. CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
  562. while ((CPAMPvalue < CPAMPMin) && (wd > 0)) {
  563. usleep_range(1000, 2000);
  564. wd -= 1;
  565. CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
  566. /*dprintk("CPAMPvalue= %d at wd=%d\n",CPAMPvalue,wd); */
  567. }
  568. dprintk("******last CPAMPvalue= %d at wd=%d\n", CPAMPvalue, wd);
  569. if (CPAMPvalue < CPAMPMin) {
  570. CPAMPStatus = FE_TER_NOCPAMP;
  571. dprintk("%s: CPAMP failed\n", __func__);
  572. } else {
  573. dprintk("%s: CPAMP OK !\n", __func__);
  574. CPAMPStatus = FE_TER_CPAMPOK;
  575. }
  576. return CPAMPStatus;
  577. }
  578. static enum stv0367_ter_signal_type
  579. stv0367ter_lock_algo(struct stv0367_state *state)
  580. {
  581. enum stv0367_ter_signal_type ret_flag;
  582. short int wd, tempo;
  583. u8 try, u_var1 = 0, u_var2 = 0, u_var3 = 0, u_var4 = 0, mode, guard;
  584. u8 tmp, tmp2;
  585. dprintk("%s:\n", __func__);
  586. if (state == NULL)
  587. return FE_TER_SWNOK;
  588. try = 0;
  589. do {
  590. ret_flag = FE_TER_LOCKOK;
  591. stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
  592. if (state->config->if_iq_mode != 0)
  593. stv0367_writebits(state, F367TER_COM_N, 0x07);
  594. stv0367_writebits(state, F367TER_GUARD, 3);/* suggest 2k 1/4 */
  595. stv0367_writebits(state, F367TER_MODE, 0);
  596. stv0367_writebits(state, F367TER_SYR_TR_DIS, 0);
  597. usleep_range(5000, 10000);
  598. stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
  599. if (stv0367ter_check_syr(state) == FE_TER_NOSYMBOL)
  600. return FE_TER_NOSYMBOL;
  601. else { /*
  602. if chip locked on wrong mode first try,
  603. it must lock correctly second try */
  604. mode = stv0367_readbits(state, F367TER_SYR_MODE);
  605. if (stv0367ter_check_cpamp(state, mode) ==
  606. FE_TER_NOCPAMP) {
  607. if (try == 0)
  608. ret_flag = FE_TER_NOCPAMP;
  609. }
  610. }
  611. try++;
  612. } while ((try < 10) && (ret_flag != FE_TER_LOCKOK));
  613. tmp = stv0367_readreg(state, R367TER_SYR_STAT);
  614. tmp2 = stv0367_readreg(state, R367TER_STATUS);
  615. dprintk("state=%p\n", state);
  616. dprintk("LOCK OK! mode=%d SYR_STAT=0x%x R367TER_STATUS=0x%x\n",
  617. mode, tmp, tmp2);
  618. tmp = stv0367_readreg(state, R367TER_PRVIT);
  619. tmp2 = stv0367_readreg(state, R367TER_I2CRPT);
  620. dprintk("PRVIT=0x%x I2CRPT=0x%x\n", tmp, tmp2);
  621. tmp = stv0367_readreg(state, R367TER_GAIN_SRC1);
  622. dprintk("GAIN_SRC1=0x%x\n", tmp);
  623. if ((mode != 0) && (mode != 1) && (mode != 2))
  624. return FE_TER_SWNOK;
  625. /*guard=stv0367_readbits(state,F367TER_SYR_GUARD); */
  626. /*suppress EPQ auto for SYR_GARD 1/16 or 1/32
  627. and set channel predictor in automatic */
  628. #if 0
  629. switch (guard) {
  630. case 0:
  631. case 1:
  632. stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
  633. stv0367_writereg(state, R367TER_CHC_CTL, 0x01);
  634. break;
  635. case 2:
  636. case 3:
  637. stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
  638. stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
  639. break;
  640. default:
  641. return FE_TER_SWNOK;
  642. }
  643. #endif
  644. /*reset fec an reedsolo FOR 367 only*/
  645. stv0367_writebits(state, F367TER_RST_SFEC, 1);
  646. stv0367_writebits(state, F367TER_RST_REEDSOLO, 1);
  647. usleep_range(1000, 2000);
  648. stv0367_writebits(state, F367TER_RST_SFEC, 0);
  649. stv0367_writebits(state, F367TER_RST_REEDSOLO, 0);
  650. u_var1 = stv0367_readbits(state, F367TER_LK);
  651. u_var2 = stv0367_readbits(state, F367TER_PRF);
  652. u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
  653. /* u_var4=stv0367_readbits(state,F367TER_TSFIFO_LINEOK); */
  654. wd = stv0367ter_duration(mode, 125, 500, 250);
  655. tempo = stv0367ter_duration(mode, 4, 16, 8);
  656. /*while ( ((!u_var1)||(!u_var2)||(!u_var3)||(!u_var4)) && (wd>=0)) */
  657. while (((!u_var1) || (!u_var2) || (!u_var3)) && (wd >= 0)) {
  658. usleep_range(1000 * tempo, 1000 * (tempo + 1));
  659. wd -= tempo;
  660. u_var1 = stv0367_readbits(state, F367TER_LK);
  661. u_var2 = stv0367_readbits(state, F367TER_PRF);
  662. u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
  663. /*u_var4=stv0367_readbits(state, F367TER_TSFIFO_LINEOK); */
  664. }
  665. if (!u_var1)
  666. return FE_TER_NOLOCK;
  667. if (!u_var2)
  668. return FE_TER_NOPRFOUND;
  669. if (!u_var3)
  670. return FE_TER_NOTPS;
  671. guard = stv0367_readbits(state, F367TER_SYR_GUARD);
  672. stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
  673. switch (guard) {
  674. case 0:
  675. case 1:
  676. stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
  677. /*stv0367_writereg(state,R367TER_CHC_CTL, 0x1);*/
  678. stv0367_writebits(state, F367TER_SYR_FILTER, 0);
  679. break;
  680. case 2:
  681. case 3:
  682. stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
  683. /*stv0367_writereg(state,R367TER_CHC_CTL, 0x11);*/
  684. stv0367_writebits(state, F367TER_SYR_FILTER, 1);
  685. break;
  686. default:
  687. return FE_TER_SWNOK;
  688. }
  689. /* apply Sfec workaround if 8K 64QAM CR!=1/2*/
  690. if ((stv0367_readbits(state, F367TER_TPS_CONST) == 2) &&
  691. (mode == 1) &&
  692. (stv0367_readbits(state, F367TER_TPS_HPCODE) != 0)) {
  693. stv0367_writereg(state, R367TER_SFDLYSETH, 0xc0);
  694. stv0367_writereg(state, R367TER_SFDLYSETM, 0x60);
  695. stv0367_writereg(state, R367TER_SFDLYSETL, 0x0);
  696. } else
  697. stv0367_writereg(state, R367TER_SFDLYSETH, 0x0);
  698. wd = stv0367ter_duration(mode, 125, 500, 250);
  699. u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
  700. while ((!u_var4) && (wd >= 0)) {
  701. usleep_range(1000 * tempo, 1000 * (tempo + 1));
  702. wd -= tempo;
  703. u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
  704. }
  705. if (!u_var4)
  706. return FE_TER_NOLOCK;
  707. /* for 367 leave COM_N at 0x7 for IQ_mode*/
  708. /*if(ter_state->if_iq_mode!=FE_TER_NORMAL_IF_TUNER) {
  709. tempo=0;
  710. while ((stv0367_readbits(state,F367TER_COM_USEGAINTRK)!=1) &&
  711. (stv0367_readbits(state,F367TER_COM_AGCLOCK)!=1)&&(tempo<100)) {
  712. ChipWaitOrAbort(state,1);
  713. tempo+=1;
  714. }
  715. stv0367_writebits(state,F367TER_COM_N,0x17);
  716. } */
  717. stv0367_writebits(state, F367TER_SYR_TR_DIS, 1);
  718. dprintk("FE_TER_LOCKOK !!!\n");
  719. return FE_TER_LOCKOK;
  720. }
  721. static void stv0367ter_set_ts_mode(struct stv0367_state *state,
  722. enum stv0367_ts_mode PathTS)
  723. {
  724. dprintk("%s:\n", __func__);
  725. if (state == NULL)
  726. return;
  727. stv0367_writebits(state, F367TER_TS_DIS, 0);
  728. switch (PathTS) {
  729. default:
  730. /*for removing warning :default we can assume in parallel mode*/
  731. case STV0367_PARALLEL_PUNCT_CLOCK:
  732. stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 0);
  733. stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 0);
  734. break;
  735. case STV0367_SERIAL_PUNCT_CLOCK:
  736. stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 1);
  737. stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 1);
  738. break;
  739. }
  740. }
  741. static void stv0367ter_set_clk_pol(struct stv0367_state *state,
  742. enum stv0367_clk_pol clock)
  743. {
  744. dprintk("%s:\n", __func__);
  745. if (state == NULL)
  746. return;
  747. switch (clock) {
  748. case STV0367_RISINGEDGE_CLOCK:
  749. stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 1);
  750. break;
  751. case STV0367_FALLINGEDGE_CLOCK:
  752. stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
  753. break;
  754. /*case FE_TER_CLOCK_POLARITY_DEFAULT:*/
  755. default:
  756. stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
  757. break;
  758. }
  759. }
  760. #if 0
  761. static void stv0367ter_core_sw(struct stv0367_state *state)
  762. {
  763. dprintk("%s:\n", __func__);
  764. stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
  765. stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
  766. msleep(350);
  767. }
  768. #endif
  769. static int stv0367ter_standby(struct dvb_frontend *fe, u8 standby_on)
  770. {
  771. struct stv0367_state *state = fe->demodulator_priv;
  772. dprintk("%s:\n", __func__);
  773. if (standby_on) {
  774. stv0367_writebits(state, F367TER_STDBY, 1);
  775. stv0367_writebits(state, F367TER_STDBY_FEC, 1);
  776. stv0367_writebits(state, F367TER_STDBY_CORE, 1);
  777. } else {
  778. stv0367_writebits(state, F367TER_STDBY, 0);
  779. stv0367_writebits(state, F367TER_STDBY_FEC, 0);
  780. stv0367_writebits(state, F367TER_STDBY_CORE, 0);
  781. }
  782. return 0;
  783. }
  784. static int stv0367ter_sleep(struct dvb_frontend *fe)
  785. {
  786. return stv0367ter_standby(fe, 1);
  787. }
  788. static int stv0367ter_init(struct dvb_frontend *fe)
  789. {
  790. struct stv0367_state *state = fe->demodulator_priv;
  791. struct stv0367ter_state *ter_state = state->ter_state;
  792. dprintk("%s:\n", __func__);
  793. ter_state->pBER = 0;
  794. stv0367_write_table(state,
  795. stv0367_deftabs[state->deftabs][STV0367_TAB_TER]);
  796. stv0367_pll_setup(state, STV0367_ICSPEED_53125, state->config->xtal);
  797. stv0367_writereg(state, R367TER_I2CRPT, 0xa0);
  798. stv0367_writereg(state, R367TER_ANACTRL, 0x00);
  799. /*Set TS1 and TS2 to serial or parallel mode */
  800. stv0367ter_set_ts_mode(state, state->config->ts_mode);
  801. stv0367ter_set_clk_pol(state, state->config->clk_pol);
  802. state->chip_id = stv0367_readreg(state, R367TER_ID);
  803. ter_state->first_lock = 0;
  804. ter_state->unlock_counter = 2;
  805. return 0;
  806. }
  807. static int stv0367ter_algo(struct dvb_frontend *fe)
  808. {
  809. struct dtv_frontend_properties *p = &fe->dtv_property_cache;
  810. struct stv0367_state *state = fe->demodulator_priv;
  811. struct stv0367ter_state *ter_state = state->ter_state;
  812. int offset = 0, tempo = 0;
  813. u8 u_var;
  814. u8 /*constell,*/ counter;
  815. s8 step;
  816. s32 timing_offset = 0;
  817. u32 trl_nomrate = 0, InternalFreq = 0, temp = 0, ifkhz = 0;
  818. dprintk("%s:\n", __func__);
  819. stv0367_get_if_khz(state, &ifkhz);
  820. ter_state->frequency = p->frequency;
  821. ter_state->force = FE_TER_FORCENONE
  822. + stv0367_readbits(state, F367TER_FORCE) * 2;
  823. ter_state->if_iq_mode = state->config->if_iq_mode;
  824. switch (state->config->if_iq_mode) {
  825. case FE_TER_NORMAL_IF_TUNER: /* Normal IF mode */
  826. dprintk("ALGO: FE_TER_NORMAL_IF_TUNER selected\n");
  827. stv0367_writebits(state, F367TER_TUNER_BB, 0);
  828. stv0367_writebits(state, F367TER_LONGPATH_IF, 0);
  829. stv0367_writebits(state, F367TER_DEMUX_SWAP, 0);
  830. break;
  831. case FE_TER_LONGPATH_IF_TUNER: /* Long IF mode */
  832. dprintk("ALGO: FE_TER_LONGPATH_IF_TUNER selected\n");
  833. stv0367_writebits(state, F367TER_TUNER_BB, 0);
  834. stv0367_writebits(state, F367TER_LONGPATH_IF, 1);
  835. stv0367_writebits(state, F367TER_DEMUX_SWAP, 1);
  836. break;
  837. case FE_TER_IQ_TUNER: /* IQ mode */
  838. dprintk("ALGO: FE_TER_IQ_TUNER selected\n");
  839. stv0367_writebits(state, F367TER_TUNER_BB, 1);
  840. stv0367_writebits(state, F367TER_PPM_INVSEL, 0);
  841. break;
  842. default:
  843. printk(KERN_ERR "ALGO: wrong TUNER type selected\n");
  844. return -EINVAL;
  845. }
  846. usleep_range(5000, 7000);
  847. switch (p->inversion) {
  848. case INVERSION_AUTO:
  849. default:
  850. dprintk("%s: inversion AUTO\n", __func__);
  851. if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
  852. stv0367_writebits(state, F367TER_IQ_INVERT,
  853. ter_state->sense);
  854. else
  855. stv0367_writebits(state, F367TER_INV_SPECTR,
  856. ter_state->sense);
  857. break;
  858. case INVERSION_ON:
  859. case INVERSION_OFF:
  860. if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
  861. stv0367_writebits(state, F367TER_IQ_INVERT,
  862. p->inversion);
  863. else
  864. stv0367_writebits(state, F367TER_INV_SPECTR,
  865. p->inversion);
  866. break;
  867. }
  868. if ((ter_state->if_iq_mode != FE_TER_NORMAL_IF_TUNER) &&
  869. (ter_state->pBW != ter_state->bw)) {
  870. stv0367ter_agc_iir_lock_detect_set(state);
  871. /*set fine agc target to 180 for LPIF or IQ mode*/
  872. /* set Q_AGCTarget */
  873. stv0367_writebits(state, F367TER_SEL_IQNTAR, 1);
  874. stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
  875. /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
  876. /* set Q_AGCTarget */
  877. stv0367_writebits(state, F367TER_SEL_IQNTAR, 0);
  878. stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
  879. /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
  880. if (!stv0367_iir_filt_init(state, ter_state->bw,
  881. state->config->xtal))
  882. return -EINVAL;
  883. /*set IIR filter once for 6,7 or 8MHz BW*/
  884. ter_state->pBW = ter_state->bw;
  885. stv0367ter_agc_iir_rst(state);
  886. }
  887. if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
  888. stv0367_writebits(state, F367TER_BDI_LPSEL, 0x01);
  889. else
  890. stv0367_writebits(state, F367TER_BDI_LPSEL, 0x00);
  891. InternalFreq = stv0367ter_get_mclk(state, state->config->xtal) / 1000;
  892. temp = (int)
  893. ((((ter_state->bw * 64 * (1 << 15) * 100)
  894. / (InternalFreq)) * 10) / 7);
  895. stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB, temp % 2);
  896. temp = temp / 2;
  897. stv0367_writebits(state, F367TER_TRL_NOMRATE_HI, temp / 256);
  898. stv0367_writebits(state, F367TER_TRL_NOMRATE_LO, temp % 256);
  899. temp = stv0367_readbits(state, F367TER_TRL_NOMRATE_HI) * 512 +
  900. stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2 +
  901. stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB);
  902. temp = (int)(((1 << 17) * ter_state->bw * 1000) / (7 * (InternalFreq)));
  903. stv0367_writebits(state, F367TER_GAIN_SRC_HI, temp / 256);
  904. stv0367_writebits(state, F367TER_GAIN_SRC_LO, temp % 256);
  905. temp = stv0367_readbits(state, F367TER_GAIN_SRC_HI) * 256 +
  906. stv0367_readbits(state, F367TER_GAIN_SRC_LO);
  907. temp = (int)
  908. ((InternalFreq - ifkhz) * (1 << 16) / (InternalFreq));
  909. dprintk("DEROT temp=0x%x\n", temp);
  910. stv0367_writebits(state, F367TER_INC_DEROT_HI, temp / 256);
  911. stv0367_writebits(state, F367TER_INC_DEROT_LO, temp % 256);
  912. ter_state->echo_pos = 0;
  913. ter_state->ucblocks = 0; /* liplianin */
  914. ter_state->pBER = 0; /* liplianin */
  915. stv0367_writebits(state, F367TER_LONG_ECHO, ter_state->echo_pos);
  916. if (stv0367ter_lock_algo(state) != FE_TER_LOCKOK)
  917. return 0;
  918. ter_state->state = FE_TER_LOCKOK;
  919. ter_state->mode = stv0367_readbits(state, F367TER_SYR_MODE);
  920. ter_state->guard = stv0367_readbits(state, F367TER_SYR_GUARD);
  921. ter_state->first_lock = 1; /* we know sense now :) */
  922. ter_state->agc_val =
  923. (stv0367_readbits(state, F367TER_AGC1_VAL_LO) << 16) +
  924. (stv0367_readbits(state, F367TER_AGC1_VAL_HI) << 24) +
  925. stv0367_readbits(state, F367TER_AGC2_VAL_LO) +
  926. (stv0367_readbits(state, F367TER_AGC2_VAL_HI) << 8);
  927. /* Carrier offset calculation */
  928. stv0367_writebits(state, F367TER_FREEZE, 1);
  929. offset = (stv0367_readbits(state, F367TER_CRL_FOFFSET_VHI) << 16) ;
  930. offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_HI) << 8);
  931. offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_LO));
  932. stv0367_writebits(state, F367TER_FREEZE, 0);
  933. if (offset > 8388607)
  934. offset -= 16777216;
  935. offset = offset * 2 / 16384;
  936. if (ter_state->mode == FE_TER_MODE_2K)
  937. offset = (offset * 4464) / 1000;/*** 1 FFT BIN=4.464khz***/
  938. else if (ter_state->mode == FE_TER_MODE_4K)
  939. offset = (offset * 223) / 100;/*** 1 FFT BIN=2.23khz***/
  940. else if (ter_state->mode == FE_TER_MODE_8K)
  941. offset = (offset * 111) / 100;/*** 1 FFT BIN=1.1khz***/
  942. if (stv0367_readbits(state, F367TER_PPM_INVSEL) == 1) {
  943. if ((stv0367_readbits(state, F367TER_INV_SPECTR) ==
  944. (stv0367_readbits(state,
  945. F367TER_STATUS_INV_SPECRUM) == 1)))
  946. offset = offset * -1;
  947. }
  948. if (ter_state->bw == 6)
  949. offset = (offset * 6) / 8;
  950. else if (ter_state->bw == 7)
  951. offset = (offset * 7) / 8;
  952. ter_state->frequency += offset;
  953. tempo = 10; /* exit even if timing_offset stays null */
  954. while ((timing_offset == 0) && (tempo > 0)) {
  955. usleep_range(10000, 20000); /*was 20ms */
  956. /* fine tuning of timing offset if required */
  957. timing_offset = stv0367_readbits(state, F367TER_TRL_TOFFSET_LO)
  958. + 256 * stv0367_readbits(state,
  959. F367TER_TRL_TOFFSET_HI);
  960. if (timing_offset >= 32768)
  961. timing_offset -= 65536;
  962. trl_nomrate = (512 * stv0367_readbits(state,
  963. F367TER_TRL_NOMRATE_HI)
  964. + stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2
  965. + stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB));
  966. timing_offset = ((signed)(1000000 / trl_nomrate) *
  967. timing_offset) / 2048;
  968. tempo--;
  969. }
  970. if (timing_offset <= 0) {
  971. timing_offset = (timing_offset - 11) / 22;
  972. step = -1;
  973. } else {
  974. timing_offset = (timing_offset + 11) / 22;
  975. step = 1;
  976. }
  977. for (counter = 0; counter < abs(timing_offset); counter++) {
  978. trl_nomrate += step;
  979. stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB,
  980. trl_nomrate % 2);
  981. stv0367_writebits(state, F367TER_TRL_NOMRATE_LO,
  982. trl_nomrate / 2);
  983. usleep_range(1000, 2000);
  984. }
  985. usleep_range(5000, 6000);
  986. /* unlocks could happen in case of trl centring big step,
  987. then a core off/on restarts demod */
  988. u_var = stv0367_readbits(state, F367TER_LK);
  989. if (!u_var) {
  990. stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
  991. msleep(20);
  992. stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
  993. }
  994. return 0;
  995. }
  996. static int stv0367ter_set_frontend(struct dvb_frontend *fe)
  997. {
  998. struct dtv_frontend_properties *p = &fe->dtv_property_cache;
  999. struct stv0367_state *state = fe->demodulator_priv;
  1000. struct stv0367ter_state *ter_state = state->ter_state;
  1001. /*u8 trials[2]; */
  1002. s8 num_trials, index;
  1003. u8 SenseTrials[] = { INVERSION_ON, INVERSION_OFF };
  1004. if (state->reinit_on_setfrontend)
  1005. stv0367ter_init(fe);
  1006. if (fe->ops.tuner_ops.set_params) {
  1007. if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
  1008. fe->ops.i2c_gate_ctrl(fe, 1);
  1009. fe->ops.tuner_ops.set_params(fe);
  1010. if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
  1011. fe->ops.i2c_gate_ctrl(fe, 0);
  1012. }
  1013. switch (p->transmission_mode) {
  1014. default:
  1015. case TRANSMISSION_MODE_AUTO:
  1016. case TRANSMISSION_MODE_2K:
  1017. ter_state->mode = FE_TER_MODE_2K;
  1018. break;
  1019. /* case TRANSMISSION_MODE_4K:
  1020. pLook.mode = FE_TER_MODE_4K;
  1021. break;*/
  1022. case TRANSMISSION_MODE_8K:
  1023. ter_state->mode = FE_TER_MODE_8K;
  1024. break;
  1025. }
  1026. switch (p->guard_interval) {
  1027. default:
  1028. case GUARD_INTERVAL_1_32:
  1029. case GUARD_INTERVAL_1_16:
  1030. case GUARD_INTERVAL_1_8:
  1031. case GUARD_INTERVAL_1_4:
  1032. ter_state->guard = p->guard_interval;
  1033. break;
  1034. case GUARD_INTERVAL_AUTO:
  1035. ter_state->guard = GUARD_INTERVAL_1_32;
  1036. break;
  1037. }
  1038. switch (p->bandwidth_hz) {
  1039. case 6000000:
  1040. ter_state->bw = FE_TER_CHAN_BW_6M;
  1041. break;
  1042. case 7000000:
  1043. ter_state->bw = FE_TER_CHAN_BW_7M;
  1044. break;
  1045. case 8000000:
  1046. default:
  1047. ter_state->bw = FE_TER_CHAN_BW_8M;
  1048. }
  1049. ter_state->hierarchy = FE_TER_HIER_NONE;
  1050. switch (p->inversion) {
  1051. case INVERSION_OFF:
  1052. case INVERSION_ON:
  1053. num_trials = 1;
  1054. break;
  1055. default:
  1056. num_trials = 2;
  1057. if (ter_state->first_lock)
  1058. num_trials = 1;
  1059. break;
  1060. }
  1061. ter_state->state = FE_TER_NOLOCK;
  1062. index = 0;
  1063. while (((index) < num_trials) && (ter_state->state != FE_TER_LOCKOK)) {
  1064. if (!ter_state->first_lock) {
  1065. if (p->inversion == INVERSION_AUTO)
  1066. ter_state->sense = SenseTrials[index];
  1067. }
  1068. stv0367ter_algo(fe);
  1069. if ((ter_state->state == FE_TER_LOCKOK) &&
  1070. (p->inversion == INVERSION_AUTO) &&
  1071. (index == 1)) {
  1072. /* invert spectrum sense */
  1073. SenseTrials[index] = SenseTrials[0];
  1074. SenseTrials[(index + 1) % 2] = (SenseTrials[1] + 1) % 2;
  1075. }
  1076. index++;
  1077. }
  1078. return 0;
  1079. }
  1080. static int stv0367ter_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
  1081. {
  1082. struct stv0367_state *state = fe->demodulator_priv;
  1083. struct stv0367ter_state *ter_state = state->ter_state;
  1084. u32 errs = 0;
  1085. /*wait for counting completion*/
  1086. if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0) {
  1087. errs =
  1088. ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
  1089. * (1 << 16))
  1090. + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
  1091. * (1 << 8))
  1092. + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
  1093. ter_state->ucblocks = errs;
  1094. }
  1095. (*ucblocks) = ter_state->ucblocks;
  1096. return 0;
  1097. }
  1098. static int stv0367ter_get_frontend(struct dvb_frontend *fe,
  1099. struct dtv_frontend_properties *p)
  1100. {
  1101. struct stv0367_state *state = fe->demodulator_priv;
  1102. struct stv0367ter_state *ter_state = state->ter_state;
  1103. enum stv0367_ter_mode mode;
  1104. int constell = 0,/* snr = 0,*/ Data = 0;
  1105. p->frequency = stv0367_get_tuner_freq(fe);
  1106. if ((int)p->frequency < 0)
  1107. p->frequency = -p->frequency;
  1108. constell = stv0367_readbits(state, F367TER_TPS_CONST);
  1109. if (constell == 0)
  1110. p->modulation = QPSK;
  1111. else if (constell == 1)
  1112. p->modulation = QAM_16;
  1113. else
  1114. p->modulation = QAM_64;
  1115. p->inversion = stv0367_readbits(state, F367TER_INV_SPECTR);
  1116. /* Get the Hierarchical mode */
  1117. Data = stv0367_readbits(state, F367TER_TPS_HIERMODE);
  1118. switch (Data) {
  1119. case 0:
  1120. p->hierarchy = HIERARCHY_NONE;
  1121. break;
  1122. case 1:
  1123. p->hierarchy = HIERARCHY_1;
  1124. break;
  1125. case 2:
  1126. p->hierarchy = HIERARCHY_2;
  1127. break;
  1128. case 3:
  1129. p->hierarchy = HIERARCHY_4;
  1130. break;
  1131. default:
  1132. p->hierarchy = HIERARCHY_AUTO;
  1133. break; /* error */
  1134. }
  1135. /* Get the FEC Rate */
  1136. if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
  1137. Data = stv0367_readbits(state, F367TER_TPS_LPCODE);
  1138. else
  1139. Data = stv0367_readbits(state, F367TER_TPS_HPCODE);
  1140. switch (Data) {
  1141. case 0:
  1142. p->code_rate_HP = FEC_1_2;
  1143. break;
  1144. case 1:
  1145. p->code_rate_HP = FEC_2_3;
  1146. break;
  1147. case 2:
  1148. p->code_rate_HP = FEC_3_4;
  1149. break;
  1150. case 3:
  1151. p->code_rate_HP = FEC_5_6;
  1152. break;
  1153. case 4:
  1154. p->code_rate_HP = FEC_7_8;
  1155. break;
  1156. default:
  1157. p->code_rate_HP = FEC_AUTO;
  1158. break; /* error */
  1159. }
  1160. mode = stv0367_readbits(state, F367TER_SYR_MODE);
  1161. switch (mode) {
  1162. case FE_TER_MODE_2K:
  1163. p->transmission_mode = TRANSMISSION_MODE_2K;
  1164. break;
  1165. /* case FE_TER_MODE_4K:
  1166. p->transmission_mode = TRANSMISSION_MODE_4K;
  1167. break;*/
  1168. case FE_TER_MODE_8K:
  1169. p->transmission_mode = TRANSMISSION_MODE_8K;
  1170. break;
  1171. default:
  1172. p->transmission_mode = TRANSMISSION_MODE_AUTO;
  1173. }
  1174. p->guard_interval = stv0367_readbits(state, F367TER_SYR_GUARD);
  1175. return 0;
  1176. }
  1177. static u32 stv0367ter_snr_readreg(struct dvb_frontend *fe)
  1178. {
  1179. struct stv0367_state *state = fe->demodulator_priv;
  1180. u32 snru32 = 0;
  1181. int cpt = 0;
  1182. u8 cut = stv0367_readbits(state, F367TER_IDENTIFICATIONREG);
  1183. while (cpt < 10) {
  1184. usleep_range(2000, 3000);
  1185. if (cut == 0x50) /*cut 1.0 cut 1.1*/
  1186. snru32 += stv0367_readbits(state, F367TER_CHCSNR) / 4;
  1187. else /*cu2.0*/
  1188. snru32 += 125 * stv0367_readbits(state, F367TER_CHCSNR);
  1189. cpt++;
  1190. }
  1191. snru32 /= 10;/*average on 10 values*/
  1192. return snru32;
  1193. }
  1194. static int stv0367ter_read_snr(struct dvb_frontend *fe, u16 *snr)
  1195. {
  1196. u32 snrval = stv0367ter_snr_readreg(fe);
  1197. *snr = snrval / 1000;
  1198. return 0;
  1199. }
  1200. #if 0
  1201. static int stv0367ter_status(struct dvb_frontend *fe)
  1202. {
  1203. struct stv0367_state *state = fe->demodulator_priv;
  1204. struct stv0367ter_state *ter_state = state->ter_state;
  1205. int locked = FALSE;
  1206. locked = (stv0367_readbits(state, F367TER_LK));
  1207. if (!locked)
  1208. ter_state->unlock_counter += 1;
  1209. else
  1210. ter_state->unlock_counter = 0;
  1211. if (ter_state->unlock_counter > 2) {
  1212. if (!stv0367_readbits(state, F367TER_TPS_LOCK) ||
  1213. (!stv0367_readbits(state, F367TER_LK))) {
  1214. stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
  1215. usleep_range(2000, 3000);
  1216. stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
  1217. msleep(350);
  1218. locked = (stv0367_readbits(state, F367TER_TPS_LOCK)) &&
  1219. (stv0367_readbits(state, F367TER_LK));
  1220. }
  1221. }
  1222. return locked;
  1223. }
  1224. #endif
  1225. static int stv0367ter_read_status(struct dvb_frontend *fe,
  1226. enum fe_status *status)
  1227. {
  1228. struct stv0367_state *state = fe->demodulator_priv;
  1229. dprintk("%s:\n", __func__);
  1230. *status = 0;
  1231. if (stv0367_readbits(state, F367TER_LK)) {
  1232. *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI
  1233. | FE_HAS_SYNC | FE_HAS_LOCK;
  1234. dprintk("%s: stv0367 has locked\n", __func__);
  1235. }
  1236. return 0;
  1237. }
  1238. static int stv0367ter_read_ber(struct dvb_frontend *fe, u32 *ber)
  1239. {
  1240. struct stv0367_state *state = fe->demodulator_priv;
  1241. struct stv0367ter_state *ter_state = state->ter_state;
  1242. u32 Errors = 0, tber = 0, temporary = 0;
  1243. int abc = 0, def = 0;
  1244. /*wait for counting completion*/
  1245. if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0)
  1246. Errors = ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT)
  1247. * (1 << 16))
  1248. + ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT_HI)
  1249. * (1 << 8))
  1250. + ((u32)stv0367_readbits(state,
  1251. F367TER_SFEC_ERR_CNT_LO));
  1252. /*measurement not completed, load previous value*/
  1253. else {
  1254. tber = ter_state->pBER;
  1255. return 0;
  1256. }
  1257. abc = stv0367_readbits(state, F367TER_SFEC_ERR_SOURCE);
  1258. def = stv0367_readbits(state, F367TER_SFEC_NUM_EVENT);
  1259. if (Errors == 0) {
  1260. tber = 0;
  1261. } else if (abc == 0x7) {
  1262. if (Errors <= 4) {
  1263. temporary = (Errors * 1000000000) / (8 * (1 << 14));
  1264. } else if (Errors <= 42) {
  1265. temporary = (Errors * 100000000) / (8 * (1 << 14));
  1266. temporary = temporary * 10;
  1267. } else if (Errors <= 429) {
  1268. temporary = (Errors * 10000000) / (8 * (1 << 14));
  1269. temporary = temporary * 100;
  1270. } else if (Errors <= 4294) {
  1271. temporary = (Errors * 1000000) / (8 * (1 << 14));
  1272. temporary = temporary * 1000;
  1273. } else if (Errors <= 42949) {
  1274. temporary = (Errors * 100000) / (8 * (1 << 14));
  1275. temporary = temporary * 10000;
  1276. } else if (Errors <= 429496) {
  1277. temporary = (Errors * 10000) / (8 * (1 << 14));
  1278. temporary = temporary * 100000;
  1279. } else { /*if (Errors<4294967) 2^22 max error*/
  1280. temporary = (Errors * 1000) / (8 * (1 << 14));
  1281. temporary = temporary * 100000; /* still to *10 */
  1282. }
  1283. /* Byte error*/
  1284. if (def == 2)
  1285. /*tber=Errors/(8*(1 <<14));*/
  1286. tber = temporary;
  1287. else if (def == 3)
  1288. /*tber=Errors/(8*(1 <<16));*/
  1289. tber = temporary / 4;
  1290. else if (def == 4)
  1291. /*tber=Errors/(8*(1 <<18));*/
  1292. tber = temporary / 16;
  1293. else if (def == 5)
  1294. /*tber=Errors/(8*(1 <<20));*/
  1295. tber = temporary / 64;
  1296. else if (def == 6)
  1297. /*tber=Errors/(8*(1 <<22));*/
  1298. tber = temporary / 256;
  1299. else
  1300. /* should not pass here*/
  1301. tber = 0;
  1302. if ((Errors < 4294967) && (Errors > 429496))
  1303. tber *= 10;
  1304. }
  1305. /* save actual value */
  1306. ter_state->pBER = tber;
  1307. (*ber) = tber;
  1308. return 0;
  1309. }
  1310. #if 0
  1311. static u32 stv0367ter_get_per(struct stv0367_state *state)
  1312. {
  1313. struct stv0367ter_state *ter_state = state->ter_state;
  1314. u32 Errors = 0, Per = 0, temporary = 0;
  1315. int abc = 0, def = 0, cpt = 0;
  1316. while (((stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 1) &&
  1317. (cpt < 400)) || ((Errors == 0) && (cpt < 400))) {
  1318. usleep_range(1000, 2000);
  1319. Errors = ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
  1320. * (1 << 16))
  1321. + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
  1322. * (1 << 8))
  1323. + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
  1324. cpt++;
  1325. }
  1326. abc = stv0367_readbits(state, F367TER_ERR_SRC1);
  1327. def = stv0367_readbits(state, F367TER_NUM_EVT1);
  1328. if (Errors == 0)
  1329. Per = 0;
  1330. else if (abc == 0x9) {
  1331. if (Errors <= 4) {
  1332. temporary = (Errors * 1000000000) / (8 * (1 << 8));
  1333. } else if (Errors <= 42) {
  1334. temporary = (Errors * 100000000) / (8 * (1 << 8));
  1335. temporary = temporary * 10;
  1336. } else if (Errors <= 429) {
  1337. temporary = (Errors * 10000000) / (8 * (1 << 8));
  1338. temporary = temporary * 100;
  1339. } else if (Errors <= 4294) {
  1340. temporary = (Errors * 1000000) / (8 * (1 << 8));
  1341. temporary = temporary * 1000;
  1342. } else if (Errors <= 42949) {
  1343. temporary = (Errors * 100000) / (8 * (1 << 8));
  1344. temporary = temporary * 10000;
  1345. } else { /*if(Errors<=429496) 2^16 errors max*/
  1346. temporary = (Errors * 10000) / (8 * (1 << 8));
  1347. temporary = temporary * 100000;
  1348. }
  1349. /* pkt error*/
  1350. if (def == 2)
  1351. /*Per=Errors/(1 << 8);*/
  1352. Per = temporary;
  1353. else if (def == 3)
  1354. /*Per=Errors/(1 << 10);*/
  1355. Per = temporary / 4;
  1356. else if (def == 4)
  1357. /*Per=Errors/(1 << 12);*/
  1358. Per = temporary / 16;
  1359. else if (def == 5)
  1360. /*Per=Errors/(1 << 14);*/
  1361. Per = temporary / 64;
  1362. else if (def == 6)
  1363. /*Per=Errors/(1 << 16);*/
  1364. Per = temporary / 256;
  1365. else
  1366. Per = 0;
  1367. }
  1368. /* save actual value */
  1369. ter_state->pPER = Per;
  1370. return Per;
  1371. }
  1372. #endif
  1373. static int stv0367_get_tune_settings(struct dvb_frontend *fe,
  1374. struct dvb_frontend_tune_settings
  1375. *fe_tune_settings)
  1376. {
  1377. fe_tune_settings->min_delay_ms = 1000;
  1378. fe_tune_settings->step_size = 0;
  1379. fe_tune_settings->max_drift = 0;
  1380. return 0;
  1381. }
  1382. static void stv0367_release(struct dvb_frontend *fe)
  1383. {
  1384. struct stv0367_state *state = fe->demodulator_priv;
  1385. kfree(state->ter_state);
  1386. kfree(state->cab_state);
  1387. kfree(state);
  1388. }
  1389. static const struct dvb_frontend_ops stv0367ter_ops = {
  1390. .delsys = { SYS_DVBT },
  1391. .info = {
  1392. .name = "ST STV0367 DVB-T",
  1393. .frequency_min_hz = 47 * MHz,
  1394. .frequency_max_hz = 862 * MHz,
  1395. .frequency_stepsize_hz = 15625,
  1396. .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
  1397. FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
  1398. FE_CAN_FEC_AUTO |
  1399. FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
  1400. FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_QAM_AUTO |
  1401. FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
  1402. FE_CAN_INVERSION_AUTO |
  1403. FE_CAN_MUTE_TS
  1404. },
  1405. .release = stv0367_release,
  1406. .init = stv0367ter_init,
  1407. .sleep = stv0367ter_sleep,
  1408. .i2c_gate_ctrl = stv0367ter_gate_ctrl,
  1409. .set_frontend = stv0367ter_set_frontend,
  1410. .get_frontend = stv0367ter_get_frontend,
  1411. .get_tune_settings = stv0367_get_tune_settings,
  1412. .read_status = stv0367ter_read_status,
  1413. .read_ber = stv0367ter_read_ber,/* too slow */
  1414. /* .read_signal_strength = stv0367_read_signal_strength,*/
  1415. .read_snr = stv0367ter_read_snr,
  1416. .read_ucblocks = stv0367ter_read_ucblocks,
  1417. };
  1418. struct dvb_frontend *stv0367ter_attach(const struct stv0367_config *config,
  1419. struct i2c_adapter *i2c)
  1420. {
  1421. struct stv0367_state *state = NULL;
  1422. struct stv0367ter_state *ter_state = NULL;
  1423. /* allocate memory for the internal state */
  1424. state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
  1425. if (state == NULL)
  1426. goto error;
  1427. ter_state = kzalloc(sizeof(struct stv0367ter_state), GFP_KERNEL);
  1428. if (ter_state == NULL)
  1429. goto error;
  1430. /* setup the state */
  1431. state->i2c = i2c;
  1432. state->config = config;
  1433. state->ter_state = ter_state;
  1434. state->fe.ops = stv0367ter_ops;
  1435. state->fe.demodulator_priv = state;
  1436. state->chip_id = stv0367_readreg(state, 0xf000);
  1437. /* demod operation options */
  1438. state->use_i2c_gatectrl = 1;
  1439. state->deftabs = STV0367_DEFTAB_GENERIC;
  1440. state->reinit_on_setfrontend = 1;
  1441. state->auto_if_khz = 0;
  1442. dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
  1443. /* check if the demod is there */
  1444. if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
  1445. goto error;
  1446. return &state->fe;
  1447. error:
  1448. kfree(ter_state);
  1449. kfree(state);
  1450. return NULL;
  1451. }
  1452. EXPORT_SYMBOL(stv0367ter_attach);
  1453. static int stv0367cab_gate_ctrl(struct dvb_frontend *fe, int enable)
  1454. {
  1455. struct stv0367_state *state = fe->demodulator_priv;
  1456. dprintk("%s:\n", __func__);
  1457. stv0367_writebits(state, F367CAB_I2CT_ON, (enable > 0) ? 1 : 0);
  1458. return 0;
  1459. }
  1460. static u32 stv0367cab_get_mclk(struct dvb_frontend *fe, u32 ExtClk_Hz)
  1461. {
  1462. struct stv0367_state *state = fe->demodulator_priv;
  1463. u32 mclk_Hz = 0;/* master clock frequency (Hz) */
  1464. u32 M, N, P;
  1465. if (stv0367_readbits(state, F367CAB_BYPASS_PLLXN) == 0) {
  1466. N = (u32)stv0367_readbits(state, F367CAB_PLL_NDIV);
  1467. if (N == 0)
  1468. N = N + 1;
  1469. M = (u32)stv0367_readbits(state, F367CAB_PLL_MDIV);
  1470. if (M == 0)
  1471. M = M + 1;
  1472. P = (u32)stv0367_readbits(state, F367CAB_PLL_PDIV);
  1473. if (P > 5)
  1474. P = 5;
  1475. mclk_Hz = ((ExtClk_Hz / 2) * N) / (M * (1 << P));
  1476. dprintk("stv0367cab_get_mclk BYPASS_PLLXN mclk_Hz=%d\n",
  1477. mclk_Hz);
  1478. } else
  1479. mclk_Hz = ExtClk_Hz;
  1480. dprintk("stv0367cab_get_mclk final mclk_Hz=%d\n", mclk_Hz);
  1481. return mclk_Hz;
  1482. }
  1483. static u32 stv0367cab_get_adc_freq(struct dvb_frontend *fe, u32 ExtClk_Hz)
  1484. {
  1485. u32 ADCClk_Hz = ExtClk_Hz;
  1486. ADCClk_Hz = stv0367cab_get_mclk(fe, ExtClk_Hz);
  1487. return ADCClk_Hz;
  1488. }
  1489. static enum stv0367cab_mod stv0367cab_SetQamSize(struct stv0367_state *state,
  1490. u32 SymbolRate,
  1491. enum stv0367cab_mod QAMSize)
  1492. {
  1493. /* Set QAM size */
  1494. stv0367_writebits(state, F367CAB_QAM_MODE, QAMSize);
  1495. /* Set Registers settings specific to the QAM size */
  1496. switch (QAMSize) {
  1497. case FE_CAB_MOD_QAM4:
  1498. stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
  1499. break;
  1500. case FE_CAB_MOD_QAM16:
  1501. stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x64);
  1502. stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
  1503. stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
  1504. stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
  1505. stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
  1506. stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
  1507. stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
  1508. stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x8a);
  1509. break;
  1510. case FE_CAB_MOD_QAM32:
  1511. stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
  1512. stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x6e);
  1513. stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
  1514. stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
  1515. stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xb7);
  1516. stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x9d);
  1517. stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
  1518. stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
  1519. break;
  1520. case FE_CAB_MOD_QAM64:
  1521. stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x82);
  1522. stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
  1523. if (SymbolRate > 4500000) {
  1524. stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
  1525. stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
  1526. stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa5);
  1527. } else if (SymbolRate > 2500000) {
  1528. stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
  1529. stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
  1530. stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
  1531. } else {
  1532. stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
  1533. stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
  1534. stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
  1535. }
  1536. stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
  1537. stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
  1538. stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x99);
  1539. break;
  1540. case FE_CAB_MOD_QAM128:
  1541. stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
  1542. stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x76);
  1543. stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
  1544. stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xb1);
  1545. if (SymbolRate > 4500000)
  1546. stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
  1547. else if (SymbolRate > 2500000)
  1548. stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
  1549. else
  1550. stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0x97);
  1551. stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x8e);
  1552. stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
  1553. stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
  1554. break;
  1555. case FE_CAB_MOD_QAM256:
  1556. stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x94);
  1557. stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
  1558. stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
  1559. if (SymbolRate > 4500000)
  1560. stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
  1561. else if (SymbolRate > 2500000)
  1562. stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
  1563. else
  1564. stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
  1565. stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
  1566. stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x85);
  1567. stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
  1568. stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
  1569. break;
  1570. case FE_CAB_MOD_QAM512:
  1571. stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
  1572. break;
  1573. case FE_CAB_MOD_QAM1024:
  1574. stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
  1575. break;
  1576. default:
  1577. break;
  1578. }
  1579. return QAMSize;
  1580. }
  1581. static u32 stv0367cab_set_derot_freq(struct stv0367_state *state,
  1582. u32 adc_hz, s32 derot_hz)
  1583. {
  1584. u32 sampled_if = 0;
  1585. u32 adc_khz;
  1586. adc_khz = adc_hz / 1000;
  1587. dprintk("%s: adc_hz=%d derot_hz=%d\n", __func__, adc_hz, derot_hz);
  1588. if (adc_khz != 0) {
  1589. if (derot_hz < 1000000)
  1590. derot_hz = adc_hz / 4; /* ZIF operation */
  1591. if (derot_hz > adc_hz)
  1592. derot_hz = derot_hz - adc_hz;
  1593. sampled_if = (u32)derot_hz / 1000;
  1594. sampled_if *= 32768;
  1595. sampled_if /= adc_khz;
  1596. sampled_if *= 256;
  1597. }
  1598. if (sampled_if > 8388607)
  1599. sampled_if = 8388607;
  1600. dprintk("%s: sampled_if=0x%x\n", __func__, sampled_if);
  1601. stv0367_writereg(state, R367CAB_MIX_NCO_LL, sampled_if);
  1602. stv0367_writereg(state, R367CAB_MIX_NCO_HL, (sampled_if >> 8));
  1603. stv0367_writebits(state, F367CAB_MIX_NCO_INC_HH, (sampled_if >> 16));
  1604. return derot_hz;
  1605. }
  1606. static u32 stv0367cab_get_derot_freq(struct stv0367_state *state, u32 adc_hz)
  1607. {
  1608. u32 sampled_if;
  1609. sampled_if = stv0367_readbits(state, F367CAB_MIX_NCO_INC_LL) +
  1610. (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HL) << 8) +
  1611. (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HH) << 16);
  1612. sampled_if /= 256;
  1613. sampled_if *= (adc_hz / 1000);
  1614. sampled_if += 1;
  1615. sampled_if /= 32768;
  1616. return sampled_if;
  1617. }
  1618. static u32 stv0367cab_set_srate(struct stv0367_state *state, u32 adc_hz,
  1619. u32 mclk_hz, u32 SymbolRate,
  1620. enum stv0367cab_mod QAMSize)
  1621. {
  1622. u32 QamSizeCorr = 0;
  1623. u32 u32_tmp = 0, u32_tmp1 = 0;
  1624. u32 adp_khz;
  1625. dprintk("%s:\n", __func__);
  1626. /* Set Correction factor of SRC gain */
  1627. switch (QAMSize) {
  1628. case FE_CAB_MOD_QAM4:
  1629. QamSizeCorr = 1110;
  1630. break;
  1631. case FE_CAB_MOD_QAM16:
  1632. QamSizeCorr = 1032;
  1633. break;
  1634. case FE_CAB_MOD_QAM32:
  1635. QamSizeCorr = 954;
  1636. break;
  1637. case FE_CAB_MOD_QAM64:
  1638. QamSizeCorr = 983;
  1639. break;
  1640. case FE_CAB_MOD_QAM128:
  1641. QamSizeCorr = 957;
  1642. break;
  1643. case FE_CAB_MOD_QAM256:
  1644. QamSizeCorr = 948;
  1645. break;
  1646. case FE_CAB_MOD_QAM512:
  1647. QamSizeCorr = 0;
  1648. break;
  1649. case FE_CAB_MOD_QAM1024:
  1650. QamSizeCorr = 944;
  1651. break;
  1652. default:
  1653. break;
  1654. }
  1655. /* Transfer ratio calculation */
  1656. if (adc_hz != 0) {
  1657. u32_tmp = 256 * SymbolRate;
  1658. u32_tmp = u32_tmp / adc_hz;
  1659. }
  1660. stv0367_writereg(state, R367CAB_EQU_CRL_TFR, (u8)u32_tmp);
  1661. /* Symbol rate and SRC gain calculation */
  1662. adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
  1663. if (adp_khz != 0) {
  1664. u32_tmp = SymbolRate;
  1665. u32_tmp1 = SymbolRate;
  1666. if (u32_tmp < 2097152) { /* 2097152 = 2^21 */
  1667. /* Symbol rate calculation */
  1668. u32_tmp *= 2048; /* 2048 = 2^11 */
  1669. u32_tmp = u32_tmp / adp_khz;
  1670. u32_tmp = u32_tmp * 16384; /* 16384 = 2^14 */
  1671. u32_tmp /= 125 ; /* 125 = 1000/2^3 */
  1672. u32_tmp = u32_tmp * 8; /* 8 = 2^3 */
  1673. /* SRC Gain Calculation */
  1674. u32_tmp1 *= 2048; /* *2*2^10 */
  1675. u32_tmp1 /= 439; /* *2/878 */
  1676. u32_tmp1 *= 256; /* *2^8 */
  1677. u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
  1678. u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
  1679. u32_tmp1 = u32_tmp1 / 10000000;
  1680. } else if (u32_tmp < 4194304) { /* 4194304 = 2**22 */
  1681. /* Symbol rate calculation */
  1682. u32_tmp *= 1024 ; /* 1024 = 2**10 */
  1683. u32_tmp = u32_tmp / adp_khz;
  1684. u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
  1685. u32_tmp /= 125 ; /* 125 = 1000/2**3 */
  1686. u32_tmp = u32_tmp * 16; /* 16 = 2**4 */
  1687. /* SRC Gain Calculation */
  1688. u32_tmp1 *= 1024; /* *2*2^9 */
  1689. u32_tmp1 /= 439; /* *2/878 */
  1690. u32_tmp1 *= 256; /* *2^8 */
  1691. u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz)*/
  1692. u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
  1693. u32_tmp1 = u32_tmp1 / 5000000;
  1694. } else if (u32_tmp < 8388607) { /* 8388607 = 2**23 */
  1695. /* Symbol rate calculation */
  1696. u32_tmp *= 512 ; /* 512 = 2**9 */
  1697. u32_tmp = u32_tmp / adp_khz;
  1698. u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
  1699. u32_tmp /= 125 ; /* 125 = 1000/2**3 */
  1700. u32_tmp = u32_tmp * 32; /* 32 = 2**5 */
  1701. /* SRC Gain Calculation */
  1702. u32_tmp1 *= 512; /* *2*2^8 */
  1703. u32_tmp1 /= 439; /* *2/878 */
  1704. u32_tmp1 *= 256; /* *2^8 */
  1705. u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
  1706. u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
  1707. u32_tmp1 = u32_tmp1 / 2500000;
  1708. } else {
  1709. /* Symbol rate calculation */
  1710. u32_tmp *= 256 ; /* 256 = 2**8 */
  1711. u32_tmp = u32_tmp / adp_khz;
  1712. u32_tmp = u32_tmp * 16384; /* 16384 = 2**13 */
  1713. u32_tmp /= 125 ; /* 125 = 1000/2**3 */
  1714. u32_tmp = u32_tmp * 64; /* 64 = 2**6 */
  1715. /* SRC Gain Calculation */
  1716. u32_tmp1 *= 256; /* 2*2^7 */
  1717. u32_tmp1 /= 439; /* *2/878 */
  1718. u32_tmp1 *= 256; /* *2^8 */
  1719. u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
  1720. u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
  1721. u32_tmp1 = u32_tmp1 / 1250000;
  1722. }
  1723. }
  1724. #if 0
  1725. /* Filters' coefficients are calculated and written
  1726. into registers only if the filters are enabled */
  1727. if (stv0367_readbits(state, F367CAB_ADJ_EN)) {
  1728. stv0367cab_SetIirAdjacentcoefficient(state, mclk_hz,
  1729. SymbolRate);
  1730. /* AllPass filter must be enabled
  1731. when the adjacents filter is used */
  1732. stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 1);
  1733. stv0367cab_SetAllPasscoefficient(state, mclk_hz, SymbolRate);
  1734. } else
  1735. /* AllPass filter must be disabled
  1736. when the adjacents filter is not used */
  1737. #endif
  1738. stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
  1739. stv0367_writereg(state, R367CAB_SRC_NCO_LL, u32_tmp);
  1740. stv0367_writereg(state, R367CAB_SRC_NCO_LH, (u32_tmp >> 8));
  1741. stv0367_writereg(state, R367CAB_SRC_NCO_HL, (u32_tmp >> 16));
  1742. stv0367_writereg(state, R367CAB_SRC_NCO_HH, (u32_tmp >> 24));
  1743. stv0367_writereg(state, R367CAB_IQDEM_GAIN_SRC_L, u32_tmp1 & 0x00ff);
  1744. stv0367_writebits(state, F367CAB_GAIN_SRC_HI, (u32_tmp1 >> 8) & 0x00ff);
  1745. return SymbolRate ;
  1746. }
  1747. static u32 stv0367cab_GetSymbolRate(struct stv0367_state *state, u32 mclk_hz)
  1748. {
  1749. u32 regsym;
  1750. u32 adp_khz;
  1751. regsym = stv0367_readreg(state, R367CAB_SRC_NCO_LL) +
  1752. (stv0367_readreg(state, R367CAB_SRC_NCO_LH) << 8) +
  1753. (stv0367_readreg(state, R367CAB_SRC_NCO_HL) << 16) +
  1754. (stv0367_readreg(state, R367CAB_SRC_NCO_HH) << 24);
  1755. adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
  1756. if (regsym < 134217728) { /* 134217728L = 2**27*/
  1757. regsym = regsym * 32; /* 32 = 2**5 */
  1758. regsym = regsym / 32768; /* 32768L = 2**15 */
  1759. regsym = adp_khz * regsym; /* AdpClk in kHz */
  1760. regsym = regsym / 128; /* 128 = 2**7 */
  1761. regsym *= 125 ; /* 125 = 1000/2**3 */
  1762. regsym /= 2048 ; /* 2048 = 2**11 */
  1763. } else if (regsym < 268435456) { /* 268435456L = 2**28 */
  1764. regsym = regsym * 16; /* 16 = 2**4 */
  1765. regsym = regsym / 32768; /* 32768L = 2**15 */
  1766. regsym = adp_khz * regsym; /* AdpClk in kHz */
  1767. regsym = regsym / 128; /* 128 = 2**7 */
  1768. regsym *= 125 ; /* 125 = 1000/2**3*/
  1769. regsym /= 1024 ; /* 256 = 2**10*/
  1770. } else if (regsym < 536870912) { /* 536870912L = 2**29*/
  1771. regsym = regsym * 8; /* 8 = 2**3 */
  1772. regsym = regsym / 32768; /* 32768L = 2**15 */
  1773. regsym = adp_khz * regsym; /* AdpClk in kHz */
  1774. regsym = regsym / 128; /* 128 = 2**7 */
  1775. regsym *= 125 ; /* 125 = 1000/2**3 */
  1776. regsym /= 512 ; /* 128 = 2**9 */
  1777. } else {
  1778. regsym = regsym * 4; /* 4 = 2**2 */
  1779. regsym = regsym / 32768; /* 32768L = 2**15 */
  1780. regsym = adp_khz * regsym; /* AdpClk in kHz */
  1781. regsym = regsym / 128; /* 128 = 2**7 */
  1782. regsym *= 125 ; /* 125 = 1000/2**3 */
  1783. regsym /= 256 ; /* 64 = 2**8 */
  1784. }
  1785. return regsym;
  1786. }
  1787. static u32 stv0367cab_fsm_status(struct stv0367_state *state)
  1788. {
  1789. return stv0367_readbits(state, F367CAB_FSM_STATUS);
  1790. }
  1791. static u32 stv0367cab_qamfec_lock(struct stv0367_state *state)
  1792. {
  1793. return stv0367_readbits(state,
  1794. (state->cab_state->qamfec_status_reg ?
  1795. state->cab_state->qamfec_status_reg :
  1796. F367CAB_QAMFEC_LOCK));
  1797. }
  1798. static
  1799. enum stv0367_cab_signal_type stv0367cab_fsm_signaltype(u32 qam_fsm_status)
  1800. {
  1801. enum stv0367_cab_signal_type signaltype = FE_CAB_NOAGC;
  1802. switch (qam_fsm_status) {
  1803. case 1:
  1804. signaltype = FE_CAB_NOAGC;
  1805. break;
  1806. case 2:
  1807. signaltype = FE_CAB_NOTIMING;
  1808. break;
  1809. case 3:
  1810. signaltype = FE_CAB_TIMINGOK;
  1811. break;
  1812. case 4:
  1813. signaltype = FE_CAB_NOCARRIER;
  1814. break;
  1815. case 5:
  1816. signaltype = FE_CAB_CARRIEROK;
  1817. break;
  1818. case 7:
  1819. signaltype = FE_CAB_NOBLIND;
  1820. break;
  1821. case 8:
  1822. signaltype = FE_CAB_BLINDOK;
  1823. break;
  1824. case 10:
  1825. signaltype = FE_CAB_NODEMOD;
  1826. break;
  1827. case 11:
  1828. signaltype = FE_CAB_DEMODOK;
  1829. break;
  1830. case 12:
  1831. signaltype = FE_CAB_DEMODOK;
  1832. break;
  1833. case 13:
  1834. signaltype = FE_CAB_NODEMOD;
  1835. break;
  1836. case 14:
  1837. signaltype = FE_CAB_NOBLIND;
  1838. break;
  1839. case 15:
  1840. signaltype = FE_CAB_NOSIGNAL;
  1841. break;
  1842. default:
  1843. break;
  1844. }
  1845. return signaltype;
  1846. }
  1847. static int stv0367cab_read_status(struct dvb_frontend *fe,
  1848. enum fe_status *status)
  1849. {
  1850. struct stv0367_state *state = fe->demodulator_priv;
  1851. dprintk("%s:\n", __func__);
  1852. *status = 0;
  1853. /* update cab_state->state from QAM_FSM_STATUS */
  1854. state->cab_state->state = stv0367cab_fsm_signaltype(
  1855. stv0367cab_fsm_status(state));
  1856. if (stv0367cab_qamfec_lock(state)) {
  1857. *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI
  1858. | FE_HAS_SYNC | FE_HAS_LOCK;
  1859. dprintk("%s: stv0367 has locked\n", __func__);
  1860. } else {
  1861. if (state->cab_state->state > FE_CAB_NOSIGNAL)
  1862. *status |= FE_HAS_SIGNAL;
  1863. if (state->cab_state->state > FE_CAB_NOCARRIER)
  1864. *status |= FE_HAS_CARRIER;
  1865. if (state->cab_state->state >= FE_CAB_DEMODOK)
  1866. *status |= FE_HAS_VITERBI;
  1867. if (state->cab_state->state >= FE_CAB_DATAOK)
  1868. *status |= FE_HAS_SYNC;
  1869. }
  1870. return 0;
  1871. }
  1872. static int stv0367cab_standby(struct dvb_frontend *fe, u8 standby_on)
  1873. {
  1874. struct stv0367_state *state = fe->demodulator_priv;
  1875. dprintk("%s:\n", __func__);
  1876. if (standby_on) {
  1877. stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x03);
  1878. stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x01);
  1879. stv0367_writebits(state, F367CAB_STDBY, 1);
  1880. stv0367_writebits(state, F367CAB_STDBY_CORE, 1);
  1881. stv0367_writebits(state, F367CAB_EN_BUFFER_I, 0);
  1882. stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 0);
  1883. stv0367_writebits(state, F367CAB_POFFQ, 1);
  1884. stv0367_writebits(state, F367CAB_POFFI, 1);
  1885. } else {
  1886. stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x00);
  1887. stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x00);
  1888. stv0367_writebits(state, F367CAB_STDBY, 0);
  1889. stv0367_writebits(state, F367CAB_STDBY_CORE, 0);
  1890. stv0367_writebits(state, F367CAB_EN_BUFFER_I, 1);
  1891. stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 1);
  1892. stv0367_writebits(state, F367CAB_POFFQ, 0);
  1893. stv0367_writebits(state, F367CAB_POFFI, 0);
  1894. }
  1895. return 0;
  1896. }
  1897. static int stv0367cab_sleep(struct dvb_frontend *fe)
  1898. {
  1899. return stv0367cab_standby(fe, 1);
  1900. }
  1901. static int stv0367cab_init(struct dvb_frontend *fe)
  1902. {
  1903. struct stv0367_state *state = fe->demodulator_priv;
  1904. struct stv0367cab_state *cab_state = state->cab_state;
  1905. dprintk("%s:\n", __func__);
  1906. stv0367_write_table(state,
  1907. stv0367_deftabs[state->deftabs][STV0367_TAB_CAB]);
  1908. switch (state->config->ts_mode) {
  1909. case STV0367_DVBCI_CLOCK:
  1910. dprintk("Setting TSMode = STV0367_DVBCI_CLOCK\n");
  1911. stv0367_writebits(state, F367CAB_OUTFORMAT, 0x03);
  1912. break;
  1913. case STV0367_SERIAL_PUNCT_CLOCK:
  1914. case STV0367_SERIAL_CONT_CLOCK:
  1915. stv0367_writebits(state, F367CAB_OUTFORMAT, 0x01);
  1916. break;
  1917. case STV0367_PARALLEL_PUNCT_CLOCK:
  1918. case STV0367_OUTPUTMODE_DEFAULT:
  1919. stv0367_writebits(state, F367CAB_OUTFORMAT, 0x00);
  1920. break;
  1921. }
  1922. switch (state->config->clk_pol) {
  1923. case STV0367_RISINGEDGE_CLOCK:
  1924. stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x00);
  1925. break;
  1926. case STV0367_FALLINGEDGE_CLOCK:
  1927. case STV0367_CLOCKPOLARITY_DEFAULT:
  1928. stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x01);
  1929. break;
  1930. }
  1931. stv0367_writebits(state, F367CAB_SYNC_STRIP, 0x00);
  1932. stv0367_writebits(state, F367CAB_CT_NBST, 0x01);
  1933. stv0367_writebits(state, F367CAB_TS_SWAP, 0x01);
  1934. stv0367_writebits(state, F367CAB_FIFO_BYPASS, 0x00);
  1935. stv0367_writereg(state, R367CAB_ANACTRL, 0x00);/*PLL enabled and used */
  1936. cab_state->mclk = stv0367cab_get_mclk(fe, state->config->xtal);
  1937. cab_state->adc_clk = stv0367cab_get_adc_freq(fe, state->config->xtal);
  1938. return 0;
  1939. }
  1940. static
  1941. enum stv0367_cab_signal_type stv0367cab_algo(struct stv0367_state *state,
  1942. struct dtv_frontend_properties *p)
  1943. {
  1944. struct stv0367cab_state *cab_state = state->cab_state;
  1945. enum stv0367_cab_signal_type signalType = FE_CAB_NOAGC;
  1946. u32 QAMFEC_Lock, QAM_Lock, u32_tmp, ifkhz,
  1947. LockTime, TRLTimeOut, AGCTimeOut, CRLSymbols,
  1948. CRLTimeOut, EQLTimeOut, DemodTimeOut, FECTimeOut;
  1949. u8 TrackAGCAccum;
  1950. s32 tmp;
  1951. dprintk("%s:\n", __func__);
  1952. stv0367_get_if_khz(state, &ifkhz);
  1953. /* Timeouts calculation */
  1954. /* A max lock time of 25 ms is allowed for delayed AGC */
  1955. AGCTimeOut = 25;
  1956. /* 100000 symbols needed by the TRL as a maximum value */
  1957. TRLTimeOut = 100000000 / p->symbol_rate;
  1958. /* CRLSymbols is the needed number of symbols to achieve a lock
  1959. within [-4%, +4%] of the symbol rate.
  1960. CRL timeout is calculated
  1961. for a lock within [-search_range, +search_range].
  1962. EQL timeout can be changed depending on
  1963. the micro-reflections we want to handle.
  1964. A characterization must be performed
  1965. with these echoes to get new timeout values.
  1966. */
  1967. switch (p->modulation) {
  1968. case QAM_16:
  1969. CRLSymbols = 150000;
  1970. EQLTimeOut = 100;
  1971. break;
  1972. case QAM_32:
  1973. CRLSymbols = 250000;
  1974. EQLTimeOut = 100;
  1975. break;
  1976. case QAM_64:
  1977. CRLSymbols = 200000;
  1978. EQLTimeOut = 100;
  1979. break;
  1980. case QAM_128:
  1981. CRLSymbols = 250000;
  1982. EQLTimeOut = 100;
  1983. break;
  1984. case QAM_256:
  1985. CRLSymbols = 250000;
  1986. EQLTimeOut = 100;
  1987. break;
  1988. default:
  1989. CRLSymbols = 200000;
  1990. EQLTimeOut = 100;
  1991. break;
  1992. }
  1993. #if 0
  1994. if (pIntParams->search_range < 0) {
  1995. CRLTimeOut = (25 * CRLSymbols *
  1996. (-pIntParams->search_range / 1000)) /
  1997. (pIntParams->symbol_rate / 1000);
  1998. } else
  1999. #endif
  2000. CRLTimeOut = (25 * CRLSymbols * (cab_state->search_range / 1000)) /
  2001. (p->symbol_rate / 1000);
  2002. CRLTimeOut = (1000 * CRLTimeOut) / p->symbol_rate;
  2003. /* Timeouts below 50ms are coerced */
  2004. if (CRLTimeOut < 50)
  2005. CRLTimeOut = 50;
  2006. /* A maximum of 100 TS packets is needed to get FEC lock even in case
  2007. the spectrum inversion needs to be changed.
  2008. This is equal to 20 ms in case of the lowest symbol rate of 0.87Msps
  2009. */
  2010. FECTimeOut = 20;
  2011. DemodTimeOut = AGCTimeOut + TRLTimeOut + CRLTimeOut + EQLTimeOut;
  2012. dprintk("%s: DemodTimeOut=%d\n", __func__, DemodTimeOut);
  2013. /* Reset the TRL to ensure nothing starts until the
  2014. AGC is stable which ensures a better lock time
  2015. */
  2016. stv0367_writereg(state, R367CAB_CTRL_1, 0x04);
  2017. /* Set AGC accumulation time to minimum and lock threshold to maximum
  2018. in order to speed up the AGC lock */
  2019. TrackAGCAccum = stv0367_readbits(state, F367CAB_AGC_ACCUMRSTSEL);
  2020. stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, 0x0);
  2021. /* Modulus Mapper is disabled */
  2022. stv0367_writebits(state, F367CAB_MODULUSMAP_EN, 0);
  2023. /* Disable the sweep function */
  2024. stv0367_writebits(state, F367CAB_SWEEP_EN, 0);
  2025. /* The sweep function is never used, Sweep rate must be set to 0 */
  2026. /* Set the derotator frequency in Hz */
  2027. stv0367cab_set_derot_freq(state, cab_state->adc_clk,
  2028. (1000 * (s32)ifkhz + cab_state->derot_offset));
  2029. /* Disable the Allpass Filter when the symbol rate is out of range */
  2030. if ((p->symbol_rate > 10800000) | (p->symbol_rate < 1800000)) {
  2031. stv0367_writebits(state, F367CAB_ADJ_EN, 0);
  2032. stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
  2033. }
  2034. #if 0
  2035. /* Check if the tuner is locked */
  2036. tuner_lock = stv0367cab_tuner_get_status(fe);
  2037. if (tuner_lock == 0)
  2038. return FE_367CAB_NOTUNER;
  2039. #endif
  2040. /* Release the TRL to start demodulator acquisition */
  2041. /* Wait for QAM lock */
  2042. LockTime = 0;
  2043. stv0367_writereg(state, R367CAB_CTRL_1, 0x00);
  2044. do {
  2045. QAM_Lock = stv0367cab_fsm_status(state);
  2046. if ((LockTime >= (DemodTimeOut - EQLTimeOut)) &&
  2047. (QAM_Lock == 0x04))
  2048. /*
  2049. * We don't wait longer, the frequency/phase offset
  2050. * must be too big
  2051. */
  2052. LockTime = DemodTimeOut;
  2053. else if ((LockTime >= (AGCTimeOut + TRLTimeOut)) &&
  2054. (QAM_Lock == 0x02))
  2055. /*
  2056. * We don't wait longer, either there is no signal or
  2057. * it is not the right symbol rate or it is an analog
  2058. * carrier
  2059. */
  2060. {
  2061. LockTime = DemodTimeOut;
  2062. u32_tmp = stv0367_readbits(state,
  2063. F367CAB_AGC_PWR_WORD_LO) +
  2064. (stv0367_readbits(state,
  2065. F367CAB_AGC_PWR_WORD_ME) << 8) +
  2066. (stv0367_readbits(state,
  2067. F367CAB_AGC_PWR_WORD_HI) << 16);
  2068. if (u32_tmp >= 131072)
  2069. u32_tmp = 262144 - u32_tmp;
  2070. u32_tmp = u32_tmp / (1 << (11 - stv0367_readbits(state,
  2071. F367CAB_AGC_IF_BWSEL)));
  2072. if (u32_tmp < stv0367_readbits(state,
  2073. F367CAB_AGC_PWRREF_LO) +
  2074. 256 * stv0367_readbits(state,
  2075. F367CAB_AGC_PWRREF_HI) - 10)
  2076. QAM_Lock = 0x0f;
  2077. } else {
  2078. usleep_range(10000, 20000);
  2079. LockTime += 10;
  2080. }
  2081. dprintk("QAM_Lock=0x%x LockTime=%d\n", QAM_Lock, LockTime);
  2082. tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
  2083. dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
  2084. } while (((QAM_Lock != 0x0c) && (QAM_Lock != 0x0b)) &&
  2085. (LockTime < DemodTimeOut));
  2086. dprintk("QAM_Lock=0x%x\n", QAM_Lock);
  2087. tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
  2088. dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
  2089. tmp = stv0367_readreg(state, R367CAB_IT_STATUS2);
  2090. dprintk("R367CAB_IT_STATUS2=0x%x\n", tmp);
  2091. tmp = stv0367cab_get_derot_freq(state, cab_state->adc_clk);
  2092. dprintk("stv0367cab_get_derot_freq=0x%x\n", tmp);
  2093. if ((QAM_Lock == 0x0c) || (QAM_Lock == 0x0b)) {
  2094. /* Wait for FEC lock */
  2095. LockTime = 0;
  2096. do {
  2097. usleep_range(5000, 7000);
  2098. LockTime += 5;
  2099. QAMFEC_Lock = stv0367cab_qamfec_lock(state);
  2100. } while (!QAMFEC_Lock && (LockTime < FECTimeOut));
  2101. } else
  2102. QAMFEC_Lock = 0;
  2103. if (QAMFEC_Lock) {
  2104. signalType = FE_CAB_DATAOK;
  2105. cab_state->spect_inv = stv0367_readbits(state,
  2106. F367CAB_QUAD_INV);
  2107. #if 0
  2108. /* not clear for me */
  2109. if (ifkhz != 0) {
  2110. if (ifkhz > cab_state->adc_clk / 1000) {
  2111. cab_state->freq_khz =
  2112. FE_Cab_TunerGetFrequency(pIntParams->hTuner)
  2113. - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
  2114. - cab_state->adc_clk / 1000 + ifkhz;
  2115. } else {
  2116. cab_state->freq_khz =
  2117. FE_Cab_TunerGetFrequency(pIntParams->hTuner)
  2118. - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
  2119. + ifkhz;
  2120. }
  2121. } else {
  2122. cab_state->freq_khz =
  2123. FE_Cab_TunerGetFrequency(pIntParams->hTuner) +
  2124. stv0367cab_get_derot_freq(state,
  2125. cab_state->adc_clk) -
  2126. cab_state->adc_clk / 4000;
  2127. }
  2128. #endif
  2129. cab_state->symbol_rate = stv0367cab_GetSymbolRate(state,
  2130. cab_state->mclk);
  2131. cab_state->locked = 1;
  2132. /* stv0367_setbits(state, F367CAB_AGC_ACCUMRSTSEL,7);*/
  2133. } else
  2134. signalType = stv0367cab_fsm_signaltype(QAM_Lock);
  2135. /* Set the AGC control values to tracking values */
  2136. stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, TrackAGCAccum);
  2137. return signalType;
  2138. }
  2139. static int stv0367cab_set_frontend(struct dvb_frontend *fe)
  2140. {
  2141. struct dtv_frontend_properties *p = &fe->dtv_property_cache;
  2142. struct stv0367_state *state = fe->demodulator_priv;
  2143. struct stv0367cab_state *cab_state = state->cab_state;
  2144. enum stv0367cab_mod QAMSize = 0;
  2145. dprintk("%s: freq = %d, srate = %d\n", __func__,
  2146. p->frequency, p->symbol_rate);
  2147. cab_state->derot_offset = 0;
  2148. switch (p->modulation) {
  2149. case QAM_16:
  2150. QAMSize = FE_CAB_MOD_QAM16;
  2151. break;
  2152. case QAM_32:
  2153. QAMSize = FE_CAB_MOD_QAM32;
  2154. break;
  2155. case QAM_64:
  2156. QAMSize = FE_CAB_MOD_QAM64;
  2157. break;
  2158. case QAM_128:
  2159. QAMSize = FE_CAB_MOD_QAM128;
  2160. break;
  2161. case QAM_256:
  2162. QAMSize = FE_CAB_MOD_QAM256;
  2163. break;
  2164. default:
  2165. break;
  2166. }
  2167. if (state->reinit_on_setfrontend)
  2168. stv0367cab_init(fe);
  2169. /* Tuner Frequency Setting */
  2170. if (fe->ops.tuner_ops.set_params) {
  2171. if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
  2172. fe->ops.i2c_gate_ctrl(fe, 1);
  2173. fe->ops.tuner_ops.set_params(fe);
  2174. if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
  2175. fe->ops.i2c_gate_ctrl(fe, 0);
  2176. }
  2177. stv0367cab_SetQamSize(
  2178. state,
  2179. p->symbol_rate,
  2180. QAMSize);
  2181. stv0367cab_set_srate(state,
  2182. cab_state->adc_clk,
  2183. cab_state->mclk,
  2184. p->symbol_rate,
  2185. QAMSize);
  2186. /* Search algorithm launch, [-1.1*RangeOffset, +1.1*RangeOffset] scan */
  2187. cab_state->state = stv0367cab_algo(state, p);
  2188. return 0;
  2189. }
  2190. static int stv0367cab_get_frontend(struct dvb_frontend *fe,
  2191. struct dtv_frontend_properties *p)
  2192. {
  2193. struct stv0367_state *state = fe->demodulator_priv;
  2194. struct stv0367cab_state *cab_state = state->cab_state;
  2195. u32 ifkhz = 0;
  2196. enum stv0367cab_mod QAMSize;
  2197. dprintk("%s:\n", __func__);
  2198. stv0367_get_if_khz(state, &ifkhz);
  2199. p->symbol_rate = stv0367cab_GetSymbolRate(state, cab_state->mclk);
  2200. QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
  2201. switch (QAMSize) {
  2202. case FE_CAB_MOD_QAM16:
  2203. p->modulation = QAM_16;
  2204. break;
  2205. case FE_CAB_MOD_QAM32:
  2206. p->modulation = QAM_32;
  2207. break;
  2208. case FE_CAB_MOD_QAM64:
  2209. p->modulation = QAM_64;
  2210. break;
  2211. case FE_CAB_MOD_QAM128:
  2212. p->modulation = QAM_128;
  2213. break;
  2214. case FE_CAB_MOD_QAM256:
  2215. p->modulation = QAM_256;
  2216. break;
  2217. default:
  2218. break;
  2219. }
  2220. p->frequency = stv0367_get_tuner_freq(fe);
  2221. dprintk("%s: tuner frequency = %d\n", __func__, p->frequency);
  2222. if (ifkhz == 0) {
  2223. p->frequency +=
  2224. (stv0367cab_get_derot_freq(state, cab_state->adc_clk) -
  2225. cab_state->adc_clk / 4000);
  2226. return 0;
  2227. }
  2228. if (ifkhz > cab_state->adc_clk / 1000)
  2229. p->frequency += (ifkhz
  2230. - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
  2231. - cab_state->adc_clk / 1000);
  2232. else
  2233. p->frequency += (ifkhz
  2234. - stv0367cab_get_derot_freq(state, cab_state->adc_clk));
  2235. return 0;
  2236. }
  2237. #if 0
  2238. void stv0367cab_GetErrorCount(state, enum stv0367cab_mod QAMSize,
  2239. u32 symbol_rate, FE_367qam_Monitor *Monitor_results)
  2240. {
  2241. stv0367cab_OptimiseNByteAndGetBER(state, QAMSize, symbol_rate, Monitor_results);
  2242. stv0367cab_GetPacketsCount(state, Monitor_results);
  2243. return;
  2244. }
  2245. static int stv0367cab_read_ber(struct dvb_frontend *fe, u32 *ber)
  2246. {
  2247. struct stv0367_state *state = fe->demodulator_priv;
  2248. return 0;
  2249. }
  2250. #endif
  2251. static s32 stv0367cab_get_rf_lvl(struct stv0367_state *state)
  2252. {
  2253. s32 rfLevel = 0;
  2254. s32 RfAgcPwm = 0, IfAgcPwm = 0;
  2255. u8 i;
  2256. stv0367_writebits(state, F367CAB_STDBY_ADCGP, 0x0);
  2257. RfAgcPwm =
  2258. (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_LO) & 0x03) +
  2259. (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_HI) << 2);
  2260. RfAgcPwm = 100 * RfAgcPwm / 1023;
  2261. IfAgcPwm =
  2262. stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_LO) +
  2263. (stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_HI) << 8);
  2264. if (IfAgcPwm >= 2048)
  2265. IfAgcPwm -= 2048;
  2266. else
  2267. IfAgcPwm += 2048;
  2268. IfAgcPwm = 100 * IfAgcPwm / 4095;
  2269. /* For DTT75467 on NIM */
  2270. if (RfAgcPwm < 90 && IfAgcPwm < 28) {
  2271. for (i = 0; i < RF_LOOKUP_TABLE_SIZE; i++) {
  2272. if (RfAgcPwm <= stv0367cab_RF_LookUp1[0][i]) {
  2273. rfLevel = (-1) * stv0367cab_RF_LookUp1[1][i];
  2274. break;
  2275. }
  2276. }
  2277. if (i == RF_LOOKUP_TABLE_SIZE)
  2278. rfLevel = -56;
  2279. } else { /*if IF AGC>10*/
  2280. for (i = 0; i < RF_LOOKUP_TABLE2_SIZE; i++) {
  2281. if (IfAgcPwm <= stv0367cab_RF_LookUp2[0][i]) {
  2282. rfLevel = (-1) * stv0367cab_RF_LookUp2[1][i];
  2283. break;
  2284. }
  2285. }
  2286. if (i == RF_LOOKUP_TABLE2_SIZE)
  2287. rfLevel = -72;
  2288. }
  2289. return rfLevel;
  2290. }
  2291. static int stv0367cab_read_strength(struct dvb_frontend *fe, u16 *strength)
  2292. {
  2293. struct stv0367_state *state = fe->demodulator_priv;
  2294. s32 signal = stv0367cab_get_rf_lvl(state);
  2295. dprintk("%s: signal=%d dBm\n", __func__, signal);
  2296. if (signal <= -72)
  2297. *strength = 65535;
  2298. else
  2299. *strength = (22 + signal) * (-1311);
  2300. dprintk("%s: strength=%d\n", __func__, (*strength));
  2301. return 0;
  2302. }
  2303. static int stv0367cab_snr_power(struct dvb_frontend *fe)
  2304. {
  2305. struct stv0367_state *state = fe->demodulator_priv;
  2306. enum stv0367cab_mod QAMSize;
  2307. QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
  2308. switch (QAMSize) {
  2309. case FE_CAB_MOD_QAM4:
  2310. return 21904;
  2311. case FE_CAB_MOD_QAM16:
  2312. return 20480;
  2313. case FE_CAB_MOD_QAM32:
  2314. return 23040;
  2315. case FE_CAB_MOD_QAM64:
  2316. return 21504;
  2317. case FE_CAB_MOD_QAM128:
  2318. return 23616;
  2319. case FE_CAB_MOD_QAM256:
  2320. return 21760;
  2321. case FE_CAB_MOD_QAM1024:
  2322. return 21280;
  2323. default:
  2324. break;
  2325. }
  2326. return 1;
  2327. }
  2328. static int stv0367cab_snr_readreg(struct dvb_frontend *fe, int avgdiv)
  2329. {
  2330. struct stv0367_state *state = fe->demodulator_priv;
  2331. u32 regval = 0;
  2332. int i;
  2333. for (i = 0; i < 10; i++) {
  2334. regval += (stv0367_readbits(state, F367CAB_SNR_LO)
  2335. + 256 * stv0367_readbits(state, F367CAB_SNR_HI));
  2336. }
  2337. if (avgdiv)
  2338. regval /= 10;
  2339. return regval;
  2340. }
  2341. static int stv0367cab_read_snr(struct dvb_frontend *fe, u16 *snr)
  2342. {
  2343. struct stv0367_state *state = fe->demodulator_priv;
  2344. u32 noisepercentage;
  2345. u32 regval = 0, temp = 0;
  2346. int power;
  2347. power = stv0367cab_snr_power(fe);
  2348. regval = stv0367cab_snr_readreg(fe, 1);
  2349. if (regval != 0) {
  2350. temp = power
  2351. * (1 << (3 + stv0367_readbits(state, F367CAB_SNR_PER)));
  2352. temp /= regval;
  2353. }
  2354. /* table values, not needed to calculate logarithms */
  2355. if (temp >= 5012)
  2356. noisepercentage = 100;
  2357. else if (temp >= 3981)
  2358. noisepercentage = 93;
  2359. else if (temp >= 3162)
  2360. noisepercentage = 86;
  2361. else if (temp >= 2512)
  2362. noisepercentage = 79;
  2363. else if (temp >= 1995)
  2364. noisepercentage = 72;
  2365. else if (temp >= 1585)
  2366. noisepercentage = 65;
  2367. else if (temp >= 1259)
  2368. noisepercentage = 58;
  2369. else if (temp >= 1000)
  2370. noisepercentage = 50;
  2371. else if (temp >= 794)
  2372. noisepercentage = 43;
  2373. else if (temp >= 501)
  2374. noisepercentage = 36;
  2375. else if (temp >= 316)
  2376. noisepercentage = 29;
  2377. else if (temp >= 200)
  2378. noisepercentage = 22;
  2379. else if (temp >= 158)
  2380. noisepercentage = 14;
  2381. else if (temp >= 126)
  2382. noisepercentage = 7;
  2383. else
  2384. noisepercentage = 0;
  2385. dprintk("%s: noisepercentage=%d\n", __func__, noisepercentage);
  2386. *snr = (noisepercentage * 65535) / 100;
  2387. return 0;
  2388. }
  2389. static int stv0367cab_read_ucblcks(struct dvb_frontend *fe, u32 *ucblocks)
  2390. {
  2391. struct stv0367_state *state = fe->demodulator_priv;
  2392. int corrected, tscount;
  2393. *ucblocks = (stv0367_readreg(state, R367CAB_RS_COUNTER_5) << 8)
  2394. | stv0367_readreg(state, R367CAB_RS_COUNTER_4);
  2395. corrected = (stv0367_readreg(state, R367CAB_RS_COUNTER_3) << 8)
  2396. | stv0367_readreg(state, R367CAB_RS_COUNTER_2);
  2397. tscount = (stv0367_readreg(state, R367CAB_RS_COUNTER_2) << 8)
  2398. | stv0367_readreg(state, R367CAB_RS_COUNTER_1);
  2399. dprintk("%s: uncorrected blocks=%d corrected blocks=%d tscount=%d\n",
  2400. __func__, *ucblocks, corrected, tscount);
  2401. return 0;
  2402. };
  2403. static const struct dvb_frontend_ops stv0367cab_ops = {
  2404. .delsys = { SYS_DVBC_ANNEX_A },
  2405. .info = {
  2406. .name = "ST STV0367 DVB-C",
  2407. .frequency_min_hz = 47 * MHz,
  2408. .frequency_max_hz = 862 * MHz,
  2409. .frequency_stepsize_hz = 62500,
  2410. .symbol_rate_min = 870000,
  2411. .symbol_rate_max = 11700000,
  2412. .caps = 0x400 |/* FE_CAN_QAM_4 */
  2413. FE_CAN_QAM_16 | FE_CAN_QAM_32 |
  2414. FE_CAN_QAM_64 | FE_CAN_QAM_128 |
  2415. FE_CAN_QAM_256 | FE_CAN_FEC_AUTO
  2416. },
  2417. .release = stv0367_release,
  2418. .init = stv0367cab_init,
  2419. .sleep = stv0367cab_sleep,
  2420. .i2c_gate_ctrl = stv0367cab_gate_ctrl,
  2421. .set_frontend = stv0367cab_set_frontend,
  2422. .get_frontend = stv0367cab_get_frontend,
  2423. .read_status = stv0367cab_read_status,
  2424. /* .read_ber = stv0367cab_read_ber, */
  2425. .read_signal_strength = stv0367cab_read_strength,
  2426. .read_snr = stv0367cab_read_snr,
  2427. .read_ucblocks = stv0367cab_read_ucblcks,
  2428. .get_tune_settings = stv0367_get_tune_settings,
  2429. };
  2430. struct dvb_frontend *stv0367cab_attach(const struct stv0367_config *config,
  2431. struct i2c_adapter *i2c)
  2432. {
  2433. struct stv0367_state *state = NULL;
  2434. struct stv0367cab_state *cab_state = NULL;
  2435. /* allocate memory for the internal state */
  2436. state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
  2437. if (state == NULL)
  2438. goto error;
  2439. cab_state = kzalloc(sizeof(struct stv0367cab_state), GFP_KERNEL);
  2440. if (cab_state == NULL)
  2441. goto error;
  2442. /* setup the state */
  2443. state->i2c = i2c;
  2444. state->config = config;
  2445. cab_state->search_range = 280000;
  2446. cab_state->qamfec_status_reg = F367CAB_QAMFEC_LOCK;
  2447. state->cab_state = cab_state;
  2448. state->fe.ops = stv0367cab_ops;
  2449. state->fe.demodulator_priv = state;
  2450. state->chip_id = stv0367_readreg(state, 0xf000);
  2451. /* demod operation options */
  2452. state->use_i2c_gatectrl = 1;
  2453. state->deftabs = STV0367_DEFTAB_GENERIC;
  2454. state->reinit_on_setfrontend = 1;
  2455. state->auto_if_khz = 0;
  2456. dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
  2457. /* check if the demod is there */
  2458. if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
  2459. goto error;
  2460. return &state->fe;
  2461. error:
  2462. kfree(cab_state);
  2463. kfree(state);
  2464. return NULL;
  2465. }
  2466. EXPORT_SYMBOL(stv0367cab_attach);
  2467. /*
  2468. * Functions for operation on Digital Devices hardware
  2469. */
  2470. static void stv0367ddb_setup_ter(struct stv0367_state *state)
  2471. {
  2472. stv0367_writereg(state, R367TER_DEBUG_LT4, 0x00);
  2473. stv0367_writereg(state, R367TER_DEBUG_LT5, 0x00);
  2474. stv0367_writereg(state, R367TER_DEBUG_LT6, 0x00); /* R367CAB_CTRL_1 */
  2475. stv0367_writereg(state, R367TER_DEBUG_LT7, 0x00); /* R367CAB_CTRL_2 */
  2476. stv0367_writereg(state, R367TER_DEBUG_LT8, 0x00);
  2477. stv0367_writereg(state, R367TER_DEBUG_LT9, 0x00);
  2478. /* Tuner Setup */
  2479. /* Buffer Q disabled, I Enabled, unsigned ADC */
  2480. stv0367_writereg(state, R367TER_ANADIGCTRL, 0x89);
  2481. stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); /* ADCQ disabled */
  2482. /* Clock setup */
  2483. /* PLL bypassed and disabled */
  2484. stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
  2485. stv0367_writereg(state, R367TER_TOPCTRL, 0x00); /* Set OFDM */
  2486. /* IC runs at 54 MHz with a 27 MHz crystal */
  2487. stv0367_pll_setup(state, STV0367_ICSPEED_53125, state->config->xtal);
  2488. msleep(50);
  2489. /* PLL enabled and used */
  2490. stv0367_writereg(state, R367TER_ANACTRL, 0x00);
  2491. state->activedemod = demod_ter;
  2492. }
  2493. static void stv0367ddb_setup_cab(struct stv0367_state *state)
  2494. {
  2495. stv0367_writereg(state, R367TER_DEBUG_LT4, 0x00);
  2496. stv0367_writereg(state, R367TER_DEBUG_LT5, 0x01);
  2497. stv0367_writereg(state, R367TER_DEBUG_LT6, 0x06); /* R367CAB_CTRL_1 */
  2498. stv0367_writereg(state, R367TER_DEBUG_LT7, 0x03); /* R367CAB_CTRL_2 */
  2499. stv0367_writereg(state, R367TER_DEBUG_LT8, 0x00);
  2500. stv0367_writereg(state, R367TER_DEBUG_LT9, 0x00);
  2501. /* Tuner Setup */
  2502. /* Buffer Q disabled, I Enabled, signed ADC */
  2503. stv0367_writereg(state, R367TER_ANADIGCTRL, 0x8B);
  2504. /* ADCQ disabled */
  2505. stv0367_writereg(state, R367TER_DUAL_AD12, 0x04);
  2506. /* Clock setup */
  2507. /* PLL bypassed and disabled */
  2508. stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
  2509. /* Set QAM */
  2510. stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
  2511. /* IC runs at 58 MHz with a 27 MHz crystal */
  2512. stv0367_pll_setup(state, STV0367_ICSPEED_58000, state->config->xtal);
  2513. msleep(50);
  2514. /* PLL enabled and used */
  2515. stv0367_writereg(state, R367TER_ANACTRL, 0x00);
  2516. state->cab_state->mclk = stv0367cab_get_mclk(&state->fe,
  2517. state->config->xtal);
  2518. state->cab_state->adc_clk = stv0367cab_get_adc_freq(&state->fe,
  2519. state->config->xtal);
  2520. state->activedemod = demod_cab;
  2521. }
  2522. static int stv0367ddb_set_frontend(struct dvb_frontend *fe)
  2523. {
  2524. struct stv0367_state *state = fe->demodulator_priv;
  2525. switch (fe->dtv_property_cache.delivery_system) {
  2526. case SYS_DVBT:
  2527. if (state->activedemod != demod_ter)
  2528. stv0367ddb_setup_ter(state);
  2529. return stv0367ter_set_frontend(fe);
  2530. case SYS_DVBC_ANNEX_A:
  2531. if (state->activedemod != demod_cab)
  2532. stv0367ddb_setup_cab(state);
  2533. /* protect against division error oopses */
  2534. if (fe->dtv_property_cache.symbol_rate == 0) {
  2535. printk(KERN_ERR "Invalid symbol rate\n");
  2536. return -EINVAL;
  2537. }
  2538. return stv0367cab_set_frontend(fe);
  2539. default:
  2540. break;
  2541. }
  2542. return -EINVAL;
  2543. }
  2544. static void stv0367ddb_read_signal_strength(struct dvb_frontend *fe)
  2545. {
  2546. struct stv0367_state *state = fe->demodulator_priv;
  2547. struct dtv_frontend_properties *p = &fe->dtv_property_cache;
  2548. s32 signalstrength;
  2549. switch (state->activedemod) {
  2550. case demod_cab:
  2551. signalstrength = stv0367cab_get_rf_lvl(state) * 1000;
  2552. break;
  2553. default:
  2554. p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
  2555. return;
  2556. }
  2557. p->strength.stat[0].scale = FE_SCALE_DECIBEL;
  2558. p->strength.stat[0].uvalue = signalstrength;
  2559. }
  2560. static void stv0367ddb_read_snr(struct dvb_frontend *fe)
  2561. {
  2562. struct stv0367_state *state = fe->demodulator_priv;
  2563. struct dtv_frontend_properties *p = &fe->dtv_property_cache;
  2564. int cab_pwr;
  2565. u32 regval, tmpval, snrval = 0;
  2566. switch (state->activedemod) {
  2567. case demod_ter:
  2568. snrval = stv0367ter_snr_readreg(fe);
  2569. break;
  2570. case demod_cab:
  2571. cab_pwr = stv0367cab_snr_power(fe);
  2572. regval = stv0367cab_snr_readreg(fe, 0);
  2573. /* prevent division by zero */
  2574. if (!regval) {
  2575. snrval = 0;
  2576. break;
  2577. }
  2578. tmpval = (cab_pwr * 320) / regval;
  2579. snrval = ((tmpval != 0) ? (intlog2(tmpval) / 5581) : 0);
  2580. break;
  2581. default:
  2582. p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
  2583. return;
  2584. }
  2585. p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
  2586. p->cnr.stat[0].uvalue = snrval;
  2587. }
  2588. static void stv0367ddb_read_ucblocks(struct dvb_frontend *fe)
  2589. {
  2590. struct stv0367_state *state = fe->demodulator_priv;
  2591. struct dtv_frontend_properties *p = &fe->dtv_property_cache;
  2592. u32 ucblocks = 0;
  2593. switch (state->activedemod) {
  2594. case demod_ter:
  2595. stv0367ter_read_ucblocks(fe, &ucblocks);
  2596. break;
  2597. case demod_cab:
  2598. stv0367cab_read_ucblcks(fe, &ucblocks);
  2599. break;
  2600. default:
  2601. p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
  2602. return;
  2603. }
  2604. p->block_error.stat[0].scale = FE_SCALE_COUNTER;
  2605. p->block_error.stat[0].uvalue = ucblocks;
  2606. }
  2607. static int stv0367ddb_read_status(struct dvb_frontend *fe,
  2608. enum fe_status *status)
  2609. {
  2610. struct stv0367_state *state = fe->demodulator_priv;
  2611. struct dtv_frontend_properties *p = &fe->dtv_property_cache;
  2612. int ret = 0;
  2613. switch (state->activedemod) {
  2614. case demod_ter:
  2615. ret = stv0367ter_read_status(fe, status);
  2616. break;
  2617. case demod_cab:
  2618. ret = stv0367cab_read_status(fe, status);
  2619. break;
  2620. default:
  2621. break;
  2622. }
  2623. /* stop and report on *_read_status failure */
  2624. if (ret)
  2625. return ret;
  2626. stv0367ddb_read_signal_strength(fe);
  2627. /* read carrier/noise when a carrier is detected */
  2628. if (*status & FE_HAS_CARRIER)
  2629. stv0367ddb_read_snr(fe);
  2630. else
  2631. p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
  2632. /* read uncorrected blocks on FE_HAS_LOCK */
  2633. if (*status & FE_HAS_LOCK)
  2634. stv0367ddb_read_ucblocks(fe);
  2635. else
  2636. p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
  2637. return 0;
  2638. }
  2639. static int stv0367ddb_get_frontend(struct dvb_frontend *fe,
  2640. struct dtv_frontend_properties *p)
  2641. {
  2642. struct stv0367_state *state = fe->demodulator_priv;
  2643. switch (state->activedemod) {
  2644. case demod_ter:
  2645. return stv0367ter_get_frontend(fe, p);
  2646. case demod_cab:
  2647. return stv0367cab_get_frontend(fe, p);
  2648. default:
  2649. break;
  2650. }
  2651. return 0;
  2652. }
  2653. static int stv0367ddb_sleep(struct dvb_frontend *fe)
  2654. {
  2655. struct stv0367_state *state = fe->demodulator_priv;
  2656. switch (state->activedemod) {
  2657. case demod_ter:
  2658. state->activedemod = demod_none;
  2659. return stv0367ter_sleep(fe);
  2660. case demod_cab:
  2661. state->activedemod = demod_none;
  2662. return stv0367cab_sleep(fe);
  2663. default:
  2664. break;
  2665. }
  2666. return -EINVAL;
  2667. }
  2668. static int stv0367ddb_init(struct stv0367_state *state)
  2669. {
  2670. struct stv0367ter_state *ter_state = state->ter_state;
  2671. struct dtv_frontend_properties *p = &state->fe.dtv_property_cache;
  2672. stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
  2673. if (stv0367_deftabs[state->deftabs][STV0367_TAB_BASE])
  2674. stv0367_write_table(state,
  2675. stv0367_deftabs[state->deftabs][STV0367_TAB_BASE]);
  2676. stv0367_write_table(state,
  2677. stv0367_deftabs[state->deftabs][STV0367_TAB_CAB]);
  2678. stv0367_writereg(state, R367TER_TOPCTRL, 0x00);
  2679. stv0367_write_table(state,
  2680. stv0367_deftabs[state->deftabs][STV0367_TAB_TER]);
  2681. stv0367_writereg(state, R367TER_GAIN_SRC1, 0x2A);
  2682. stv0367_writereg(state, R367TER_GAIN_SRC2, 0xD6);
  2683. stv0367_writereg(state, R367TER_INC_DEROT1, 0x55);
  2684. stv0367_writereg(state, R367TER_INC_DEROT2, 0x55);
  2685. stv0367_writereg(state, R367TER_TRL_CTL, 0x14);
  2686. stv0367_writereg(state, R367TER_TRL_NOMRATE1, 0xAE);
  2687. stv0367_writereg(state, R367TER_TRL_NOMRATE2, 0x56);
  2688. stv0367_writereg(state, R367TER_FEPATH_CFG, 0x0);
  2689. /* OFDM TS Setup */
  2690. stv0367_writereg(state, R367TER_TSCFGH, 0x70);
  2691. stv0367_writereg(state, R367TER_TSCFGM, 0xC0);
  2692. stv0367_writereg(state, R367TER_TSCFGL, 0x20);
  2693. stv0367_writereg(state, R367TER_TSSPEED, 0x40); /* Fixed at 54 MHz */
  2694. stv0367_writereg(state, R367TER_TSCFGH, 0x71);
  2695. stv0367_writereg(state, R367TER_TSCFGH, 0x70);
  2696. stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
  2697. /* Also needed for QAM */
  2698. stv0367_writereg(state, R367TER_AGC12C, 0x01); /* AGC Pin setup */
  2699. stv0367_writereg(state, R367TER_AGCCTRL1, 0x8A);
  2700. /* QAM TS setup, note exact format also depends on descrambler */
  2701. /* settings */
  2702. /* Inverted Clock, Swap, serial */
  2703. stv0367_writereg(state, R367CAB_OUTFORMAT_0, 0x85);
  2704. /* Clock setup (PLL bypassed and disabled) */
  2705. stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
  2706. /* IC runs at 58 MHz with a 27 MHz crystal */
  2707. stv0367_pll_setup(state, STV0367_ICSPEED_58000, state->config->xtal);
  2708. /* Tuner setup */
  2709. /* Buffer Q disabled, I Enabled, signed ADC */
  2710. stv0367_writereg(state, R367TER_ANADIGCTRL, 0x8b);
  2711. stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); /* ADCQ disabled */
  2712. /* Improves the C/N lock limit */
  2713. stv0367_writereg(state, R367CAB_FSM_SNR2_HTH, 0x23);
  2714. /* ZIF/IF Automatic mode */
  2715. stv0367_writereg(state, R367CAB_IQ_QAM, 0x01);
  2716. /* Improving burst noise performances */
  2717. stv0367_writereg(state, R367CAB_EQU_FFE_LEAKAGE, 0x83);
  2718. /* Improving ACI performances */
  2719. stv0367_writereg(state, R367CAB_IQDEM_ADJ_EN, 0x05);
  2720. /* PLL enabled and used */
  2721. stv0367_writereg(state, R367TER_ANACTRL, 0x00);
  2722. stv0367_writereg(state, R367TER_I2CRPT, (0x08 | ((5 & 0x07) << 4)));
  2723. ter_state->pBER = 0;
  2724. ter_state->first_lock = 0;
  2725. ter_state->unlock_counter = 2;
  2726. p->strength.len = 1;
  2727. p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
  2728. p->cnr.len = 1;
  2729. p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
  2730. p->block_error.len = 1;
  2731. p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
  2732. return 0;
  2733. }
  2734. static const struct dvb_frontend_ops stv0367ddb_ops = {
  2735. .delsys = { SYS_DVBC_ANNEX_A, SYS_DVBT },
  2736. .info = {
  2737. .name = "ST STV0367 DDB DVB-C/T",
  2738. .frequency_min_hz = 47 * MHz,
  2739. .frequency_max_hz = 865 * MHz,
  2740. .frequency_stepsize_hz = 166667,
  2741. .symbol_rate_min = 870000,
  2742. .symbol_rate_max = 11700000,
  2743. .caps = /* DVB-C */
  2744. 0x400 |/* FE_CAN_QAM_4 */
  2745. FE_CAN_QAM_16 | FE_CAN_QAM_32 |
  2746. FE_CAN_QAM_64 | FE_CAN_QAM_128 |
  2747. FE_CAN_QAM_256 |
  2748. /* DVB-T */
  2749. FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
  2750. FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
  2751. FE_CAN_QPSK | FE_CAN_TRANSMISSION_MODE_AUTO |
  2752. FE_CAN_RECOVER | FE_CAN_INVERSION_AUTO |
  2753. FE_CAN_MUTE_TS
  2754. },
  2755. .release = stv0367_release,
  2756. .sleep = stv0367ddb_sleep,
  2757. .i2c_gate_ctrl = stv0367cab_gate_ctrl, /* valid for TER and CAB */
  2758. .set_frontend = stv0367ddb_set_frontend,
  2759. .get_frontend = stv0367ddb_get_frontend,
  2760. .get_tune_settings = stv0367_get_tune_settings,
  2761. .read_status = stv0367ddb_read_status,
  2762. };
  2763. struct dvb_frontend *stv0367ddb_attach(const struct stv0367_config *config,
  2764. struct i2c_adapter *i2c)
  2765. {
  2766. struct stv0367_state *state = NULL;
  2767. struct stv0367ter_state *ter_state = NULL;
  2768. struct stv0367cab_state *cab_state = NULL;
  2769. /* allocate memory for the internal state */
  2770. state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
  2771. if (state == NULL)
  2772. goto error;
  2773. ter_state = kzalloc(sizeof(struct stv0367ter_state), GFP_KERNEL);
  2774. if (ter_state == NULL)
  2775. goto error;
  2776. cab_state = kzalloc(sizeof(struct stv0367cab_state), GFP_KERNEL);
  2777. if (cab_state == NULL)
  2778. goto error;
  2779. /* setup the state */
  2780. state->i2c = i2c;
  2781. state->config = config;
  2782. state->ter_state = ter_state;
  2783. cab_state->search_range = 280000;
  2784. cab_state->qamfec_status_reg = F367CAB_DESCR_SYNCSTATE;
  2785. state->cab_state = cab_state;
  2786. state->fe.ops = stv0367ddb_ops;
  2787. state->fe.demodulator_priv = state;
  2788. state->chip_id = stv0367_readreg(state, R367TER_ID);
  2789. /* demod operation options */
  2790. state->use_i2c_gatectrl = 0;
  2791. state->deftabs = STV0367_DEFTAB_DDB;
  2792. state->reinit_on_setfrontend = 0;
  2793. state->auto_if_khz = 1;
  2794. state->activedemod = demod_none;
  2795. dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
  2796. /* check if the demod is there */
  2797. if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
  2798. goto error;
  2799. dev_info(&i2c->dev, "Found %s with ChipID %02X at adr %02X\n",
  2800. state->fe.ops.info.name, state->chip_id,
  2801. config->demod_address);
  2802. stv0367ddb_init(state);
  2803. return &state->fe;
  2804. error:
  2805. kfree(cab_state);
  2806. kfree(ter_state);
  2807. kfree(state);
  2808. return NULL;
  2809. }
  2810. EXPORT_SYMBOL(stv0367ddb_attach);
  2811. MODULE_PARM_DESC(debug, "Set debug");
  2812. MODULE_PARM_DESC(i2c_debug, "Set i2c debug");
  2813. MODULE_AUTHOR("Igor M. Liplianin");
  2814. MODULE_DESCRIPTION("ST STV0367 DVB-C/T demodulator driver");
  2815. MODULE_LICENSE("GPL");