sp887x.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. Driver for the Spase sp887x demodulator
  4. */
  5. /*
  6. * This driver needs external firmware. Please use the command
  7. * "<kerneldir>/scripts/get_dvb_firmware sp887x" to
  8. * download/extract it, and then copy it to /usr/lib/hotplug/firmware
  9. * or /lib/firmware (depending on configuration of firmware hotplug).
  10. */
  11. #define SP887X_DEFAULT_FIRMWARE "dvb-fe-sp887x.fw"
  12. #include <linux/init.h>
  13. #include <linux/module.h>
  14. #include <linux/device.h>
  15. #include <linux/firmware.h>
  16. #include <linux/string.h>
  17. #include <linux/slab.h>
  18. #include <media/dvb_frontend.h>
  19. #include "sp887x.h"
  20. struct sp887x_state {
  21. struct i2c_adapter* i2c;
  22. const struct sp887x_config* config;
  23. struct dvb_frontend frontend;
  24. /* demodulator private data */
  25. u8 initialised:1;
  26. };
  27. static int debug;
  28. #define dprintk(args...) \
  29. do { \
  30. if (debug) printk(KERN_DEBUG "sp887x: " args); \
  31. } while (0)
  32. static int i2c_writebytes (struct sp887x_state* state, u8 *buf, u8 len)
  33. {
  34. struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = len };
  35. int err;
  36. if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
  37. printk ("%s: i2c write error (addr %02x, err == %i)\n",
  38. __func__, state->config->demod_address, err);
  39. return -EREMOTEIO;
  40. }
  41. return 0;
  42. }
  43. static int sp887x_writereg (struct sp887x_state* state, u16 reg, u16 data)
  44. {
  45. u8 b0 [] = { reg >> 8 , reg & 0xff, data >> 8, data & 0xff };
  46. struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 4 };
  47. int ret;
  48. if ((ret = i2c_transfer(state->i2c, &msg, 1)) != 1) {
  49. /*
  50. * in case of soft reset we ignore ACK errors...
  51. */
  52. if (!(reg == 0xf1a && data == 0x000 &&
  53. (ret == -EREMOTEIO || ret == -EFAULT)))
  54. {
  55. printk("%s: writereg error (reg %03x, data %03x, ret == %i)\n",
  56. __func__, reg & 0xffff, data & 0xffff, ret);
  57. return ret;
  58. }
  59. }
  60. return 0;
  61. }
  62. static int sp887x_readreg (struct sp887x_state* state, u16 reg)
  63. {
  64. u8 b0 [] = { reg >> 8 , reg & 0xff };
  65. u8 b1 [2];
  66. int ret;
  67. struct i2c_msg msg[] = {{ .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 2 },
  68. { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 2 }};
  69. if ((ret = i2c_transfer(state->i2c, msg, 2)) != 2) {
  70. printk("%s: readreg error (ret == %i)\n", __func__, ret);
  71. return -1;
  72. }
  73. return (((b1[0] << 8) | b1[1]) & 0xfff);
  74. }
  75. static void sp887x_microcontroller_stop (struct sp887x_state* state)
  76. {
  77. dprintk("%s\n", __func__);
  78. sp887x_writereg(state, 0xf08, 0x000);
  79. sp887x_writereg(state, 0xf09, 0x000);
  80. /* microcontroller STOP */
  81. sp887x_writereg(state, 0xf00, 0x000);
  82. }
  83. static void sp887x_microcontroller_start (struct sp887x_state* state)
  84. {
  85. dprintk("%s\n", __func__);
  86. sp887x_writereg(state, 0xf08, 0x000);
  87. sp887x_writereg(state, 0xf09, 0x000);
  88. /* microcontroller START */
  89. sp887x_writereg(state, 0xf00, 0x001);
  90. }
  91. static void sp887x_setup_agc (struct sp887x_state* state)
  92. {
  93. /* setup AGC parameters */
  94. dprintk("%s\n", __func__);
  95. sp887x_writereg(state, 0x33c, 0x054);
  96. sp887x_writereg(state, 0x33b, 0x04c);
  97. sp887x_writereg(state, 0x328, 0x000);
  98. sp887x_writereg(state, 0x327, 0x005);
  99. sp887x_writereg(state, 0x326, 0x001);
  100. sp887x_writereg(state, 0x325, 0x001);
  101. sp887x_writereg(state, 0x324, 0x001);
  102. sp887x_writereg(state, 0x318, 0x050);
  103. sp887x_writereg(state, 0x317, 0x3fe);
  104. sp887x_writereg(state, 0x316, 0x001);
  105. sp887x_writereg(state, 0x313, 0x005);
  106. sp887x_writereg(state, 0x312, 0x002);
  107. sp887x_writereg(state, 0x306, 0x000);
  108. sp887x_writereg(state, 0x303, 0x000);
  109. }
  110. #define BLOCKSIZE 30
  111. #define FW_SIZE 0x4000
  112. /*
  113. * load firmware and setup MPEG interface...
  114. */
  115. static int sp887x_initial_setup (struct dvb_frontend* fe, const struct firmware *fw)
  116. {
  117. struct sp887x_state* state = fe->demodulator_priv;
  118. u8 buf [BLOCKSIZE + 2];
  119. int i;
  120. int fw_size = fw->size;
  121. const unsigned char *mem = fw->data;
  122. dprintk("%s\n", __func__);
  123. /* ignore the first 10 bytes, then we expect 0x4000 bytes of firmware */
  124. if (fw_size < FW_SIZE + 10)
  125. return -ENODEV;
  126. mem = fw->data + 10;
  127. /* soft reset */
  128. sp887x_writereg(state, 0xf1a, 0x000);
  129. sp887x_microcontroller_stop (state);
  130. printk ("%s: firmware upload... ", __func__);
  131. /* setup write pointer to -1 (end of memory) */
  132. /* bit 0x8000 in address is set to enable 13bit mode */
  133. sp887x_writereg(state, 0x8f08, 0x1fff);
  134. /* dummy write (wrap around to start of memory) */
  135. sp887x_writereg(state, 0x8f0a, 0x0000);
  136. for (i = 0; i < FW_SIZE; i += BLOCKSIZE) {
  137. int c = BLOCKSIZE;
  138. int err;
  139. if (c > FW_SIZE - i)
  140. c = FW_SIZE - i;
  141. /* bit 0x8000 in address is set to enable 13bit mode */
  142. /* bit 0x4000 enables multibyte read/write transfers */
  143. /* write register is 0xf0a */
  144. buf[0] = 0xcf;
  145. buf[1] = 0x0a;
  146. memcpy(&buf[2], mem + i, c);
  147. if ((err = i2c_writebytes (state, buf, c+2)) < 0) {
  148. printk ("failed.\n");
  149. printk ("%s: i2c error (err == %i)\n", __func__, err);
  150. return err;
  151. }
  152. }
  153. /* don't write RS bytes between packets */
  154. sp887x_writereg(state, 0xc13, 0x001);
  155. /* suppress clock if (!data_valid) */
  156. sp887x_writereg(state, 0xc14, 0x000);
  157. /* setup MPEG interface... */
  158. sp887x_writereg(state, 0xc1a, 0x872);
  159. sp887x_writereg(state, 0xc1b, 0x001);
  160. sp887x_writereg(state, 0xc1c, 0x000); /* parallel mode (serial mode == 1) */
  161. sp887x_writereg(state, 0xc1a, 0x871);
  162. /* ADC mode, 2 for MT8872, 3 for SP8870/SP8871 */
  163. sp887x_writereg(state, 0x301, 0x002);
  164. sp887x_setup_agc(state);
  165. /* bit 0x010: enable data valid signal */
  166. sp887x_writereg(state, 0xd00, 0x010);
  167. sp887x_writereg(state, 0x0d1, 0x000);
  168. return 0;
  169. };
  170. static int configure_reg0xc05(struct dtv_frontend_properties *p, u16 *reg0xc05)
  171. {
  172. int known_parameters = 1;
  173. *reg0xc05 = 0x000;
  174. switch (p->modulation) {
  175. case QPSK:
  176. break;
  177. case QAM_16:
  178. *reg0xc05 |= (1 << 10);
  179. break;
  180. case QAM_64:
  181. *reg0xc05 |= (2 << 10);
  182. break;
  183. case QAM_AUTO:
  184. known_parameters = 0;
  185. break;
  186. default:
  187. return -EINVAL;
  188. }
  189. switch (p->hierarchy) {
  190. case HIERARCHY_NONE:
  191. break;
  192. case HIERARCHY_1:
  193. *reg0xc05 |= (1 << 7);
  194. break;
  195. case HIERARCHY_2:
  196. *reg0xc05 |= (2 << 7);
  197. break;
  198. case HIERARCHY_4:
  199. *reg0xc05 |= (3 << 7);
  200. break;
  201. case HIERARCHY_AUTO:
  202. known_parameters = 0;
  203. break;
  204. default:
  205. return -EINVAL;
  206. }
  207. switch (p->code_rate_HP) {
  208. case FEC_1_2:
  209. break;
  210. case FEC_2_3:
  211. *reg0xc05 |= (1 << 3);
  212. break;
  213. case FEC_3_4:
  214. *reg0xc05 |= (2 << 3);
  215. break;
  216. case FEC_5_6:
  217. *reg0xc05 |= (3 << 3);
  218. break;
  219. case FEC_7_8:
  220. *reg0xc05 |= (4 << 3);
  221. break;
  222. case FEC_AUTO:
  223. known_parameters = 0;
  224. break;
  225. default:
  226. return -EINVAL;
  227. }
  228. if (known_parameters)
  229. *reg0xc05 |= (2 << 1); /* use specified parameters */
  230. else
  231. *reg0xc05 |= (1 << 1); /* enable autoprobing */
  232. return 0;
  233. }
  234. /*
  235. * estimates division of two 24bit numbers,
  236. * derived from the ves1820/stv0299 driver code
  237. */
  238. static void divide (int n, int d, int *quotient_i, int *quotient_f)
  239. {
  240. unsigned int q, r;
  241. r = (n % d) << 8;
  242. q = (r / d);
  243. if (quotient_i)
  244. *quotient_i = q;
  245. if (quotient_f) {
  246. r = (r % d) << 8;
  247. q = (q << 8) | (r / d);
  248. r = (r % d) << 8;
  249. *quotient_f = (q << 8) | (r / d);
  250. }
  251. }
  252. static void sp887x_correct_offsets (struct sp887x_state* state,
  253. struct dtv_frontend_properties *p,
  254. int actual_freq)
  255. {
  256. static const u32 srate_correction [] = { 1879617, 4544878, 8098561 };
  257. int bw_index;
  258. int freq_offset = actual_freq - p->frequency;
  259. int sysclock = 61003; //[kHz]
  260. int ifreq = 36000000;
  261. int freq;
  262. int frequency_shift;
  263. switch (p->bandwidth_hz) {
  264. default:
  265. case 8000000:
  266. bw_index = 0;
  267. break;
  268. case 7000000:
  269. bw_index = 1;
  270. break;
  271. case 6000000:
  272. bw_index = 2;
  273. break;
  274. }
  275. if (p->inversion == INVERSION_ON)
  276. freq = ifreq - freq_offset;
  277. else
  278. freq = ifreq + freq_offset;
  279. divide(freq / 333, sysclock, NULL, &frequency_shift);
  280. if (p->inversion == INVERSION_ON)
  281. frequency_shift = -frequency_shift;
  282. /* sample rate correction */
  283. sp887x_writereg(state, 0x319, srate_correction[bw_index] >> 12);
  284. sp887x_writereg(state, 0x31a, srate_correction[bw_index] & 0xfff);
  285. /* carrier offset correction */
  286. sp887x_writereg(state, 0x309, frequency_shift >> 12);
  287. sp887x_writereg(state, 0x30a, frequency_shift & 0xfff);
  288. }
  289. static int sp887x_setup_frontend_parameters(struct dvb_frontend *fe)
  290. {
  291. struct dtv_frontend_properties *p = &fe->dtv_property_cache;
  292. struct sp887x_state* state = fe->demodulator_priv;
  293. unsigned actual_freq;
  294. int err;
  295. u16 val, reg0xc05;
  296. if (p->bandwidth_hz != 8000000 &&
  297. p->bandwidth_hz != 7000000 &&
  298. p->bandwidth_hz != 6000000)
  299. return -EINVAL;
  300. if ((err = configure_reg0xc05(p, &reg0xc05)))
  301. return err;
  302. sp887x_microcontroller_stop(state);
  303. /* setup the PLL */
  304. if (fe->ops.tuner_ops.set_params) {
  305. fe->ops.tuner_ops.set_params(fe);
  306. if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
  307. }
  308. if (fe->ops.tuner_ops.get_frequency) {
  309. fe->ops.tuner_ops.get_frequency(fe, &actual_freq);
  310. if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
  311. } else {
  312. actual_freq = p->frequency;
  313. }
  314. /* read status reg in order to clear <pending irqs */
  315. sp887x_readreg(state, 0x200);
  316. sp887x_correct_offsets(state, p, actual_freq);
  317. /* filter for 6/7/8 Mhz channel */
  318. if (p->bandwidth_hz == 6000000)
  319. val = 2;
  320. else if (p->bandwidth_hz == 7000000)
  321. val = 1;
  322. else
  323. val = 0;
  324. sp887x_writereg(state, 0x311, val);
  325. /* scan order: 2k first = 0, 8k first = 1 */
  326. if (p->transmission_mode == TRANSMISSION_MODE_2K)
  327. sp887x_writereg(state, 0x338, 0x000);
  328. else
  329. sp887x_writereg(state, 0x338, 0x001);
  330. sp887x_writereg(state, 0xc05, reg0xc05);
  331. if (p->bandwidth_hz == 6000000)
  332. val = 2 << 3;
  333. else if (p->bandwidth_hz == 7000000)
  334. val = 3 << 3;
  335. else
  336. val = 0 << 3;
  337. /* enable OFDM and SAW bits as lock indicators in sync register 0xf17,
  338. * optimize algorithm for given bandwidth...
  339. */
  340. sp887x_writereg(state, 0xf14, 0x160 | val);
  341. sp887x_writereg(state, 0xf15, 0x000);
  342. sp887x_microcontroller_start(state);
  343. return 0;
  344. }
  345. static int sp887x_read_status(struct dvb_frontend *fe, enum fe_status *status)
  346. {
  347. struct sp887x_state* state = fe->demodulator_priv;
  348. u16 snr12 = sp887x_readreg(state, 0xf16);
  349. u16 sync0x200 = sp887x_readreg(state, 0x200);
  350. u16 sync0xf17 = sp887x_readreg(state, 0xf17);
  351. *status = 0;
  352. if (snr12 > 0x00f)
  353. *status |= FE_HAS_SIGNAL;
  354. //if (sync0x200 & 0x004)
  355. // *status |= FE_HAS_SYNC | FE_HAS_CARRIER;
  356. //if (sync0x200 & 0x008)
  357. // *status |= FE_HAS_VITERBI;
  358. if ((sync0xf17 & 0x00f) == 0x002) {
  359. *status |= FE_HAS_LOCK;
  360. *status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_CARRIER;
  361. }
  362. if (sync0x200 & 0x001) { /* tuner adjustment requested...*/
  363. int steps = (sync0x200 >> 4) & 0x00f;
  364. if (steps & 0x008)
  365. steps = -steps;
  366. dprintk("sp887x: implement tuner adjustment (%+i steps)!!\n",
  367. steps);
  368. }
  369. return 0;
  370. }
  371. static int sp887x_read_ber(struct dvb_frontend* fe, u32* ber)
  372. {
  373. struct sp887x_state* state = fe->demodulator_priv;
  374. *ber = (sp887x_readreg(state, 0xc08) & 0x3f) |
  375. (sp887x_readreg(state, 0xc07) << 6);
  376. sp887x_writereg(state, 0xc08, 0x000);
  377. sp887x_writereg(state, 0xc07, 0x000);
  378. if (*ber >= 0x3fff0)
  379. *ber = ~0;
  380. return 0;
  381. }
  382. static int sp887x_read_signal_strength(struct dvb_frontend* fe, u16* strength)
  383. {
  384. struct sp887x_state* state = fe->demodulator_priv;
  385. u16 snr12 = sp887x_readreg(state, 0xf16);
  386. u32 signal = 3 * (snr12 << 4);
  387. *strength = (signal < 0xffff) ? signal : 0xffff;
  388. return 0;
  389. }
  390. static int sp887x_read_snr(struct dvb_frontend* fe, u16* snr)
  391. {
  392. struct sp887x_state* state = fe->demodulator_priv;
  393. u16 snr12 = sp887x_readreg(state, 0xf16);
  394. *snr = (snr12 << 4) | (snr12 >> 8);
  395. return 0;
  396. }
  397. static int sp887x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
  398. {
  399. struct sp887x_state* state = fe->demodulator_priv;
  400. *ucblocks = sp887x_readreg(state, 0xc0c);
  401. if (*ucblocks == 0xfff)
  402. *ucblocks = ~0;
  403. return 0;
  404. }
  405. static int sp887x_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
  406. {
  407. struct sp887x_state* state = fe->demodulator_priv;
  408. if (enable) {
  409. return sp887x_writereg(state, 0x206, 0x001);
  410. } else {
  411. return sp887x_writereg(state, 0x206, 0x000);
  412. }
  413. }
  414. static int sp887x_sleep(struct dvb_frontend* fe)
  415. {
  416. struct sp887x_state* state = fe->demodulator_priv;
  417. /* tristate TS output and disable interface pins */
  418. sp887x_writereg(state, 0xc18, 0x000);
  419. return 0;
  420. }
  421. static int sp887x_init(struct dvb_frontend* fe)
  422. {
  423. struct sp887x_state* state = fe->demodulator_priv;
  424. const struct firmware *fw = NULL;
  425. int ret;
  426. if (!state->initialised) {
  427. /* request the firmware, this will block until someone uploads it */
  428. printk("sp887x: waiting for firmware upload (%s)...\n", SP887X_DEFAULT_FIRMWARE);
  429. ret = state->config->request_firmware(fe, &fw, SP887X_DEFAULT_FIRMWARE);
  430. if (ret) {
  431. printk("sp887x: no firmware upload (timeout or file not found?)\n");
  432. return ret;
  433. }
  434. ret = sp887x_initial_setup(fe, fw);
  435. release_firmware(fw);
  436. if (ret) {
  437. printk("sp887x: writing firmware to device failed\n");
  438. return ret;
  439. }
  440. printk("sp887x: firmware upload complete\n");
  441. state->initialised = 1;
  442. }
  443. /* enable TS output and interface pins */
  444. sp887x_writereg(state, 0xc18, 0x00d);
  445. return 0;
  446. }
  447. static int sp887x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
  448. {
  449. fesettings->min_delay_ms = 350;
  450. fesettings->step_size = 166666*2;
  451. fesettings->max_drift = (166666*2)+1;
  452. return 0;
  453. }
  454. static void sp887x_release(struct dvb_frontend* fe)
  455. {
  456. struct sp887x_state* state = fe->demodulator_priv;
  457. kfree(state);
  458. }
  459. static const struct dvb_frontend_ops sp887x_ops;
  460. struct dvb_frontend* sp887x_attach(const struct sp887x_config* config,
  461. struct i2c_adapter* i2c)
  462. {
  463. struct sp887x_state* state = NULL;
  464. /* allocate memory for the internal state */
  465. state = kzalloc(sizeof(struct sp887x_state), GFP_KERNEL);
  466. if (state == NULL) goto error;
  467. /* setup the state */
  468. state->config = config;
  469. state->i2c = i2c;
  470. state->initialised = 0;
  471. /* check if the demod is there */
  472. if (sp887x_readreg(state, 0x0200) < 0) goto error;
  473. /* create dvb_frontend */
  474. memcpy(&state->frontend.ops, &sp887x_ops, sizeof(struct dvb_frontend_ops));
  475. state->frontend.demodulator_priv = state;
  476. return &state->frontend;
  477. error:
  478. kfree(state);
  479. return NULL;
  480. }
  481. static const struct dvb_frontend_ops sp887x_ops = {
  482. .delsys = { SYS_DVBT },
  483. .info = {
  484. .name = "Spase SP887x DVB-T",
  485. .frequency_min_hz = 50500 * kHz,
  486. .frequency_max_hz = 858000 * kHz,
  487. .frequency_stepsize_hz = 166666,
  488. .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
  489. FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
  490. FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
  491. FE_CAN_RECOVER
  492. },
  493. .release = sp887x_release,
  494. .init = sp887x_init,
  495. .sleep = sp887x_sleep,
  496. .i2c_gate_ctrl = sp887x_i2c_gate_ctrl,
  497. .set_frontend = sp887x_setup_frontend_parameters,
  498. .get_tune_settings = sp887x_get_tune_settings,
  499. .read_status = sp887x_read_status,
  500. .read_ber = sp887x_read_ber,
  501. .read_signal_strength = sp887x_read_signal_strength,
  502. .read_snr = sp887x_read_snr,
  503. .read_ucblocks = sp887x_read_ucblocks,
  504. };
  505. module_param(debug, int, 0644);
  506. MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
  507. MODULE_DESCRIPTION("Spase sp887x DVB-T demodulator driver");
  508. MODULE_LICENSE("GPL");
  509. EXPORT_SYMBOL(sp887x_attach);