rtl2832_priv.h 11 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Realtek RTL2832 DVB-T demodulator driver
  4. *
  5. * Copyright (C) 2012 Thomas Mair <thomas.mair86@gmail.com>
  6. * Copyright (C) 2012-2014 Antti Palosaari <crope@iki.fi>
  7. */
  8. #ifndef RTL2832_PRIV_H
  9. #define RTL2832_PRIV_H
  10. #include <linux/regmap.h>
  11. #include <linux/math64.h>
  12. #include <linux/bitops.h>
  13. #include <media/dvb_frontend.h>
  14. #include <media/dvb_math.h>
  15. #include "rtl2832.h"
  16. struct rtl2832_dev {
  17. struct rtl2832_platform_data *pdata;
  18. struct i2c_client *client;
  19. struct regmap_config regmap_config;
  20. struct regmap *regmap;
  21. struct i2c_mux_core *muxc;
  22. struct dvb_frontend fe;
  23. enum fe_status fe_status;
  24. u64 post_bit_error_prev; /* for old DVBv3 read_ber() calculation */
  25. u64 post_bit_error;
  26. u64 post_bit_count;
  27. bool sleeping;
  28. struct delayed_work i2c_gate_work;
  29. unsigned long filters; /* PID filter */
  30. bool slave_ts;
  31. };
  32. struct rtl2832_reg_entry {
  33. u16 start_address;
  34. u8 msb;
  35. u8 lsb;
  36. };
  37. struct rtl2832_reg_value {
  38. int reg;
  39. u32 value;
  40. };
  41. /* Demod register bit names */
  42. enum DVBT_REG_BIT_NAME {
  43. DVBT_SOFT_RST,
  44. DVBT_IIC_REPEAT,
  45. DVBT_TR_WAIT_MIN_8K,
  46. DVBT_RSD_BER_FAIL_VAL,
  47. DVBT_EN_BK_TRK,
  48. DVBT_REG_PI,
  49. DVBT_REG_PFREQ_1_0,
  50. DVBT_PD_DA8,
  51. DVBT_LOCK_TH,
  52. DVBT_BER_PASS_SCAL,
  53. DVBT_CE_FFSM_BYPASS,
  54. DVBT_ALPHAIIR_N,
  55. DVBT_ALPHAIIR_DIF,
  56. DVBT_EN_TRK_SPAN,
  57. DVBT_LOCK_TH_LEN,
  58. DVBT_CCI_THRE,
  59. DVBT_CCI_MON_SCAL,
  60. DVBT_CCI_M0,
  61. DVBT_CCI_M1,
  62. DVBT_CCI_M2,
  63. DVBT_CCI_M3,
  64. DVBT_SPEC_INIT_0,
  65. DVBT_SPEC_INIT_1,
  66. DVBT_SPEC_INIT_2,
  67. DVBT_AD_EN_REG,
  68. DVBT_AD_EN_REG1,
  69. DVBT_EN_BBIN,
  70. DVBT_MGD_THD0,
  71. DVBT_MGD_THD1,
  72. DVBT_MGD_THD2,
  73. DVBT_MGD_THD3,
  74. DVBT_MGD_THD4,
  75. DVBT_MGD_THD5,
  76. DVBT_MGD_THD6,
  77. DVBT_MGD_THD7,
  78. DVBT_EN_CACQ_NOTCH,
  79. DVBT_AD_AV_REF,
  80. DVBT_PIP_ON,
  81. DVBT_SCALE1_B92,
  82. DVBT_SCALE1_B93,
  83. DVBT_SCALE1_BA7,
  84. DVBT_SCALE1_BA9,
  85. DVBT_SCALE1_BAA,
  86. DVBT_SCALE1_BAB,
  87. DVBT_SCALE1_BAC,
  88. DVBT_SCALE1_BB0,
  89. DVBT_SCALE1_BB1,
  90. DVBT_KB_P1,
  91. DVBT_KB_P2,
  92. DVBT_KB_P3,
  93. DVBT_OPT_ADC_IQ,
  94. DVBT_AD_AVI,
  95. DVBT_AD_AVQ,
  96. DVBT_K1_CR_STEP12,
  97. DVBT_TRK_KS_P2,
  98. DVBT_TRK_KS_I2,
  99. DVBT_TR_THD_SET2,
  100. DVBT_TRK_KC_P2,
  101. DVBT_TRK_KC_I2,
  102. DVBT_CR_THD_SET2,
  103. DVBT_PSET_IFFREQ,
  104. DVBT_SPEC_INV,
  105. DVBT_BW_INDEX,
  106. DVBT_RSAMP_RATIO,
  107. DVBT_CFREQ_OFF_RATIO,
  108. DVBT_FSM_STAGE,
  109. DVBT_RX_CONSTEL,
  110. DVBT_RX_HIER,
  111. DVBT_RX_C_RATE_LP,
  112. DVBT_RX_C_RATE_HP,
  113. DVBT_GI_IDX,
  114. DVBT_FFT_MODE_IDX,
  115. DVBT_RSD_BER_EST,
  116. DVBT_CE_EST_EVM,
  117. DVBT_RF_AGC_VAL,
  118. DVBT_IF_AGC_VAL,
  119. DVBT_DAGC_VAL,
  120. DVBT_SFREQ_OFF,
  121. DVBT_CFREQ_OFF,
  122. DVBT_POLAR_RF_AGC,
  123. DVBT_POLAR_IF_AGC,
  124. DVBT_AAGC_HOLD,
  125. DVBT_EN_RF_AGC,
  126. DVBT_EN_IF_AGC,
  127. DVBT_IF_AGC_MIN,
  128. DVBT_IF_AGC_MAX,
  129. DVBT_RF_AGC_MIN,
  130. DVBT_RF_AGC_MAX,
  131. DVBT_IF_AGC_MAN,
  132. DVBT_IF_AGC_MAN_VAL,
  133. DVBT_RF_AGC_MAN,
  134. DVBT_RF_AGC_MAN_VAL,
  135. DVBT_DAGC_TRG_VAL,
  136. DVBT_AGC_TARG_VAL,
  137. DVBT_LOOP_GAIN_3_0,
  138. DVBT_LOOP_GAIN_4,
  139. DVBT_VTOP,
  140. DVBT_KRF,
  141. DVBT_AGC_TARG_VAL_0,
  142. DVBT_AGC_TARG_VAL_8_1,
  143. DVBT_AAGC_LOOP_GAIN,
  144. DVBT_LOOP_GAIN2_3_0,
  145. DVBT_LOOP_GAIN2_4,
  146. DVBT_LOOP_GAIN3,
  147. DVBT_VTOP1,
  148. DVBT_VTOP2,
  149. DVBT_VTOP3,
  150. DVBT_KRF1,
  151. DVBT_KRF2,
  152. DVBT_KRF3,
  153. DVBT_KRF4,
  154. DVBT_EN_GI_PGA,
  155. DVBT_THD_LOCK_UP,
  156. DVBT_THD_LOCK_DW,
  157. DVBT_THD_UP1,
  158. DVBT_THD_DW1,
  159. DVBT_INTER_CNT_LEN,
  160. DVBT_GI_PGA_STATE,
  161. DVBT_EN_AGC_PGA,
  162. DVBT_CKOUTPAR,
  163. DVBT_CKOUT_PWR,
  164. DVBT_SYNC_DUR,
  165. DVBT_ERR_DUR,
  166. DVBT_SYNC_LVL,
  167. DVBT_ERR_LVL,
  168. DVBT_VAL_LVL,
  169. DVBT_SERIAL,
  170. DVBT_SER_LSB,
  171. DVBT_CDIV_PH0,
  172. DVBT_CDIV_PH1,
  173. DVBT_MPEG_IO_OPT_2_2,
  174. DVBT_MPEG_IO_OPT_1_0,
  175. DVBT_CKOUTPAR_PIP,
  176. DVBT_CKOUT_PWR_PIP,
  177. DVBT_SYNC_LVL_PIP,
  178. DVBT_ERR_LVL_PIP,
  179. DVBT_VAL_LVL_PIP,
  180. DVBT_CKOUTPAR_PID,
  181. DVBT_CKOUT_PWR_PID,
  182. DVBT_SYNC_LVL_PID,
  183. DVBT_ERR_LVL_PID,
  184. DVBT_VAL_LVL_PID,
  185. DVBT_SM_PASS,
  186. DVBT_UPDATE_REG_2,
  187. DVBT_BTHD_P3,
  188. DVBT_BTHD_D3,
  189. DVBT_FUNC4_REG0,
  190. DVBT_FUNC4_REG1,
  191. DVBT_FUNC4_REG2,
  192. DVBT_FUNC4_REG3,
  193. DVBT_FUNC4_REG4,
  194. DVBT_FUNC4_REG5,
  195. DVBT_FUNC4_REG6,
  196. DVBT_FUNC4_REG7,
  197. DVBT_FUNC4_REG8,
  198. DVBT_FUNC4_REG9,
  199. DVBT_FUNC4_REG10,
  200. DVBT_FUNC5_REG0,
  201. DVBT_FUNC5_REG1,
  202. DVBT_FUNC5_REG2,
  203. DVBT_FUNC5_REG3,
  204. DVBT_FUNC5_REG4,
  205. DVBT_FUNC5_REG5,
  206. DVBT_FUNC5_REG6,
  207. DVBT_FUNC5_REG7,
  208. DVBT_FUNC5_REG8,
  209. DVBT_FUNC5_REG9,
  210. DVBT_FUNC5_REG10,
  211. DVBT_FUNC5_REG11,
  212. DVBT_FUNC5_REG12,
  213. DVBT_FUNC5_REG13,
  214. DVBT_FUNC5_REG14,
  215. DVBT_FUNC5_REG15,
  216. DVBT_FUNC5_REG16,
  217. DVBT_FUNC5_REG17,
  218. DVBT_FUNC5_REG18,
  219. DVBT_AD7_SETTING,
  220. DVBT_RSSI_R,
  221. DVBT_ACI_DET_IND,
  222. DVBT_REG_MON,
  223. DVBT_REG_MONSEL,
  224. DVBT_REG_GPE,
  225. DVBT_REG_GPO,
  226. DVBT_REG_4MSEL,
  227. DVBT_TEST_REG_1,
  228. DVBT_TEST_REG_2,
  229. DVBT_TEST_REG_3,
  230. DVBT_TEST_REG_4,
  231. DVBT_REG_BIT_NAME_ITEM_TERMINATOR,
  232. };
  233. static const struct rtl2832_reg_value rtl2832_tuner_init_fc2580[] = {
  234. {DVBT_DAGC_TRG_VAL, 0x39},
  235. {DVBT_AGC_TARG_VAL_0, 0x0},
  236. {DVBT_AGC_TARG_VAL_8_1, 0x5a},
  237. {DVBT_AAGC_LOOP_GAIN, 0x16},
  238. {DVBT_LOOP_GAIN2_3_0, 0x6},
  239. {DVBT_LOOP_GAIN2_4, 0x1},
  240. {DVBT_LOOP_GAIN3, 0x16},
  241. {DVBT_VTOP1, 0x35},
  242. {DVBT_VTOP2, 0x21},
  243. {DVBT_VTOP3, 0x21},
  244. {DVBT_KRF1, 0x0},
  245. {DVBT_KRF2, 0x40},
  246. {DVBT_KRF3, 0x10},
  247. {DVBT_KRF4, 0x10},
  248. {DVBT_IF_AGC_MIN, 0x80},
  249. {DVBT_IF_AGC_MAX, 0x7f},
  250. {DVBT_RF_AGC_MIN, 0x9c},
  251. {DVBT_RF_AGC_MAX, 0x7f},
  252. {DVBT_POLAR_RF_AGC, 0x0},
  253. {DVBT_POLAR_IF_AGC, 0x0},
  254. {DVBT_AD7_SETTING, 0xe9f4},
  255. };
  256. static const struct rtl2832_reg_value rtl2832_tuner_init_tua9001[] = {
  257. {DVBT_DAGC_TRG_VAL, 0x39},
  258. {DVBT_AGC_TARG_VAL_0, 0x0},
  259. {DVBT_AGC_TARG_VAL_8_1, 0x5a},
  260. {DVBT_AAGC_LOOP_GAIN, 0x16},
  261. {DVBT_LOOP_GAIN2_3_0, 0x6},
  262. {DVBT_LOOP_GAIN2_4, 0x1},
  263. {DVBT_LOOP_GAIN3, 0x16},
  264. {DVBT_VTOP1, 0x35},
  265. {DVBT_VTOP2, 0x21},
  266. {DVBT_VTOP3, 0x21},
  267. {DVBT_KRF1, 0x0},
  268. {DVBT_KRF2, 0x40},
  269. {DVBT_KRF3, 0x10},
  270. {DVBT_KRF4, 0x10},
  271. {DVBT_IF_AGC_MIN, 0x80},
  272. {DVBT_IF_AGC_MAX, 0x7f},
  273. {DVBT_RF_AGC_MIN, 0x9c},
  274. {DVBT_RF_AGC_MAX, 0x7f},
  275. {DVBT_POLAR_RF_AGC, 0x0},
  276. {DVBT_POLAR_IF_AGC, 0x0},
  277. {DVBT_AD7_SETTING, 0xe9f4},
  278. {DVBT_OPT_ADC_IQ, 0x1},
  279. {DVBT_AD_AVI, 0x0},
  280. {DVBT_AD_AVQ, 0x0},
  281. {DVBT_SPEC_INV, 0x0},
  282. };
  283. static const struct rtl2832_reg_value rtl2832_tuner_init_fc0012[] = {
  284. {DVBT_DAGC_TRG_VAL, 0x5a},
  285. {DVBT_AGC_TARG_VAL_0, 0x0},
  286. {DVBT_AGC_TARG_VAL_8_1, 0x5a},
  287. {DVBT_AAGC_LOOP_GAIN, 0x16},
  288. {DVBT_LOOP_GAIN2_3_0, 0x6},
  289. {DVBT_LOOP_GAIN2_4, 0x1},
  290. {DVBT_LOOP_GAIN3, 0x16},
  291. {DVBT_VTOP1, 0x35},
  292. {DVBT_VTOP2, 0x21},
  293. {DVBT_VTOP3, 0x21},
  294. {DVBT_KRF1, 0x0},
  295. {DVBT_KRF2, 0x40},
  296. {DVBT_KRF3, 0x10},
  297. {DVBT_KRF4, 0x10},
  298. {DVBT_IF_AGC_MIN, 0x80},
  299. {DVBT_IF_AGC_MAX, 0x7f},
  300. {DVBT_RF_AGC_MIN, 0x80},
  301. {DVBT_RF_AGC_MAX, 0x7f},
  302. {DVBT_POLAR_RF_AGC, 0x0},
  303. {DVBT_POLAR_IF_AGC, 0x0},
  304. {DVBT_AD7_SETTING, 0xe9bf},
  305. {DVBT_EN_GI_PGA, 0x0},
  306. {DVBT_THD_LOCK_UP, 0x0},
  307. {DVBT_THD_LOCK_DW, 0x0},
  308. {DVBT_THD_UP1, 0x11},
  309. {DVBT_THD_DW1, 0xef},
  310. {DVBT_INTER_CNT_LEN, 0xc},
  311. {DVBT_GI_PGA_STATE, 0x0},
  312. {DVBT_EN_AGC_PGA, 0x1},
  313. {DVBT_IF_AGC_MAN, 0x0},
  314. {DVBT_SPEC_INV, 0x0},
  315. };
  316. static const struct rtl2832_reg_value rtl2832_tuner_init_e4000[] = {
  317. {DVBT_DAGC_TRG_VAL, 0x5a},
  318. {DVBT_AGC_TARG_VAL_0, 0x0},
  319. {DVBT_AGC_TARG_VAL_8_1, 0x5a},
  320. {DVBT_AAGC_LOOP_GAIN, 0x18},
  321. {DVBT_LOOP_GAIN2_3_0, 0x8},
  322. {DVBT_LOOP_GAIN2_4, 0x1},
  323. {DVBT_LOOP_GAIN3, 0x18},
  324. {DVBT_VTOP1, 0x35},
  325. {DVBT_VTOP2, 0x21},
  326. {DVBT_VTOP3, 0x21},
  327. {DVBT_KRF1, 0x0},
  328. {DVBT_KRF2, 0x40},
  329. {DVBT_KRF3, 0x10},
  330. {DVBT_KRF4, 0x10},
  331. {DVBT_IF_AGC_MIN, 0x80},
  332. {DVBT_IF_AGC_MAX, 0x7f},
  333. {DVBT_RF_AGC_MIN, 0x80},
  334. {DVBT_RF_AGC_MAX, 0x7f},
  335. {DVBT_POLAR_RF_AGC, 0x0},
  336. {DVBT_POLAR_IF_AGC, 0x0},
  337. {DVBT_AD7_SETTING, 0xe9d4},
  338. {DVBT_EN_GI_PGA, 0x0},
  339. {DVBT_THD_LOCK_UP, 0x0},
  340. {DVBT_THD_LOCK_DW, 0x0},
  341. {DVBT_THD_UP1, 0x14},
  342. {DVBT_THD_DW1, 0xec},
  343. {DVBT_INTER_CNT_LEN, 0xc},
  344. {DVBT_GI_PGA_STATE, 0x0},
  345. {DVBT_EN_AGC_PGA, 0x1},
  346. {DVBT_REG_GPE, 0x1},
  347. {DVBT_REG_GPO, 0x1},
  348. {DVBT_REG_MONSEL, 0x1},
  349. {DVBT_REG_MON, 0x1},
  350. {DVBT_REG_4MSEL, 0x0},
  351. {DVBT_SPEC_INV, 0x0},
  352. };
  353. static const struct rtl2832_reg_value rtl2832_tuner_init_r820t[] = {
  354. {DVBT_DAGC_TRG_VAL, 0x39},
  355. {DVBT_AGC_TARG_VAL_0, 0x0},
  356. {DVBT_AGC_TARG_VAL_8_1, 0x40},
  357. {DVBT_AAGC_LOOP_GAIN, 0x16},
  358. {DVBT_LOOP_GAIN2_3_0, 0x8},
  359. {DVBT_LOOP_GAIN2_4, 0x1},
  360. {DVBT_LOOP_GAIN3, 0x18},
  361. {DVBT_VTOP1, 0x35},
  362. {DVBT_VTOP2, 0x21},
  363. {DVBT_VTOP3, 0x21},
  364. {DVBT_KRF1, 0x0},
  365. {DVBT_KRF2, 0x40},
  366. {DVBT_KRF3, 0x10},
  367. {DVBT_KRF4, 0x10},
  368. {DVBT_IF_AGC_MIN, 0x80},
  369. {DVBT_IF_AGC_MAX, 0x7f},
  370. {DVBT_RF_AGC_MIN, 0x80},
  371. {DVBT_RF_AGC_MAX, 0x7f},
  372. {DVBT_POLAR_RF_AGC, 0x0},
  373. {DVBT_POLAR_IF_AGC, 0x0},
  374. {DVBT_AD7_SETTING, 0xe9f4},
  375. {DVBT_SPEC_INV, 0x1},
  376. };
  377. static const struct rtl2832_reg_value rtl2832_tuner_init_si2157[] = {
  378. {DVBT_DAGC_TRG_VAL, 0x39},
  379. {DVBT_AGC_TARG_VAL_0, 0x0},
  380. {DVBT_AGC_TARG_VAL_8_1, 0x40},
  381. {DVBT_AAGC_LOOP_GAIN, 0x16},
  382. {DVBT_LOOP_GAIN2_3_0, 0x8},
  383. {DVBT_LOOP_GAIN2_4, 0x1},
  384. {DVBT_LOOP_GAIN3, 0x18},
  385. {DVBT_VTOP1, 0x35},
  386. {DVBT_VTOP2, 0x21},
  387. {DVBT_VTOP3, 0x21},
  388. {DVBT_KRF1, 0x0},
  389. {DVBT_KRF2, 0x40},
  390. {DVBT_KRF3, 0x10},
  391. {DVBT_KRF4, 0x10},
  392. {DVBT_IF_AGC_MIN, 0x80},
  393. {DVBT_IF_AGC_MAX, 0x7f},
  394. {DVBT_RF_AGC_MIN, 0x80},
  395. {DVBT_RF_AGC_MAX, 0x7f},
  396. {DVBT_POLAR_RF_AGC, 0x0},
  397. {DVBT_POLAR_IF_AGC, 0x0},
  398. {DVBT_AD7_SETTING, 0xe9f4},
  399. {DVBT_SPEC_INV, 0x0},
  400. };
  401. #endif /* RTL2832_PRIV_H */