mt352.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Driver for Zarlink DVB-T MT352 demodulator
  4. *
  5. * Written by Holger Waechtler <holger@qanu.de>
  6. * and Daniel Mack <daniel@qanu.de>
  7. *
  8. * AVerMedia AVerTV DVB-T 771 support by
  9. * Wolfram Joost <dbox2@frokaschwei.de>
  10. *
  11. * Support for Samsung TDTC9251DH01C(M) tuner
  12. * Copyright (C) 2004 Antonio Mancuso <antonio.mancuso@digitaltelevision.it>
  13. * Amauri Celani <acelani@essegi.net>
  14. *
  15. * DVICO FusionHDTV DVB-T1 and DVICO FusionHDTV DVB-T Lite support by
  16. * Christopher Pascoe <c.pascoe@itee.uq.edu.au>
  17. */
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/init.h>
  21. #include <linux/delay.h>
  22. #include <linux/string.h>
  23. #include <linux/slab.h>
  24. #include <media/dvb_frontend.h>
  25. #include "mt352_priv.h"
  26. #include "mt352.h"
  27. struct mt352_state {
  28. struct i2c_adapter* i2c;
  29. struct dvb_frontend frontend;
  30. /* configuration settings */
  31. struct mt352_config config;
  32. };
  33. static int debug;
  34. #define dprintk(args...) \
  35. do { \
  36. if (debug) printk(KERN_DEBUG "mt352: " args); \
  37. } while (0)
  38. static int mt352_single_write(struct dvb_frontend *fe, u8 reg, u8 val)
  39. {
  40. struct mt352_state* state = fe->demodulator_priv;
  41. u8 buf[2] = { reg, val };
  42. struct i2c_msg msg = { .addr = state->config.demod_address, .flags = 0,
  43. .buf = buf, .len = 2 };
  44. int err = i2c_transfer(state->i2c, &msg, 1);
  45. if (err != 1) {
  46. printk("mt352_write() to reg %x failed (err = %d)!\n", reg, err);
  47. return err;
  48. }
  49. return 0;
  50. }
  51. static int _mt352_write(struct dvb_frontend* fe, const u8 ibuf[], int ilen)
  52. {
  53. int err,i;
  54. for (i=0; i < ilen-1; i++)
  55. if ((err = mt352_single_write(fe,ibuf[0]+i,ibuf[i+1])))
  56. return err;
  57. return 0;
  58. }
  59. static int mt352_read_register(struct mt352_state* state, u8 reg)
  60. {
  61. int ret;
  62. u8 b0 [] = { reg };
  63. u8 b1 [] = { 0 };
  64. struct i2c_msg msg [] = { { .addr = state->config.demod_address,
  65. .flags = 0,
  66. .buf = b0, .len = 1 },
  67. { .addr = state->config.demod_address,
  68. .flags = I2C_M_RD,
  69. .buf = b1, .len = 1 } };
  70. ret = i2c_transfer(state->i2c, msg, 2);
  71. if (ret != 2) {
  72. printk("%s: readreg error (reg=%d, ret==%i)\n",
  73. __func__, reg, ret);
  74. return ret;
  75. }
  76. return b1[0];
  77. }
  78. static int mt352_sleep(struct dvb_frontend* fe)
  79. {
  80. static u8 mt352_softdown[] = { CLOCK_CTL, 0x20, 0x08 };
  81. _mt352_write(fe, mt352_softdown, sizeof(mt352_softdown));
  82. return 0;
  83. }
  84. static void mt352_calc_nominal_rate(struct mt352_state* state,
  85. u32 bandwidth,
  86. unsigned char *buf)
  87. {
  88. u32 adc_clock = 20480; /* 20.340 MHz */
  89. u32 bw,value;
  90. switch (bandwidth) {
  91. case 6000000:
  92. bw = 6;
  93. break;
  94. case 7000000:
  95. bw = 7;
  96. break;
  97. case 8000000:
  98. default:
  99. bw = 8;
  100. break;
  101. }
  102. if (state->config.adc_clock)
  103. adc_clock = state->config.adc_clock;
  104. value = 64 * bw * (1<<16) / (7 * 8);
  105. value = value * 1000 / adc_clock;
  106. dprintk("%s: bw %d, adc_clock %d => 0x%x\n",
  107. __func__, bw, adc_clock, value);
  108. buf[0] = msb(value);
  109. buf[1] = lsb(value);
  110. }
  111. static void mt352_calc_input_freq(struct mt352_state* state,
  112. unsigned char *buf)
  113. {
  114. int adc_clock = 20480; /* 20.480000 MHz */
  115. int if2 = 36167; /* 36.166667 MHz */
  116. int ife,value;
  117. if (state->config.adc_clock)
  118. adc_clock = state->config.adc_clock;
  119. if (state->config.if2)
  120. if2 = state->config.if2;
  121. if (adc_clock >= if2 * 2)
  122. ife = if2;
  123. else {
  124. ife = adc_clock - (if2 % adc_clock);
  125. if (ife > adc_clock / 2)
  126. ife = adc_clock - ife;
  127. }
  128. value = -16374 * ife / adc_clock;
  129. dprintk("%s: if2 %d, ife %d, adc_clock %d => %d / 0x%x\n",
  130. __func__, if2, ife, adc_clock, value, value & 0x3fff);
  131. buf[0] = msb(value);
  132. buf[1] = lsb(value);
  133. }
  134. static int mt352_set_parameters(struct dvb_frontend *fe)
  135. {
  136. struct dtv_frontend_properties *op = &fe->dtv_property_cache;
  137. struct mt352_state* state = fe->demodulator_priv;
  138. unsigned char buf[13];
  139. static unsigned char tuner_go[] = { 0x5d, 0x01 };
  140. static unsigned char fsm_go[] = { 0x5e, 0x01 };
  141. unsigned int tps = 0;
  142. switch (op->code_rate_HP) {
  143. case FEC_2_3:
  144. tps |= (1 << 7);
  145. break;
  146. case FEC_3_4:
  147. tps |= (2 << 7);
  148. break;
  149. case FEC_5_6:
  150. tps |= (3 << 7);
  151. break;
  152. case FEC_7_8:
  153. tps |= (4 << 7);
  154. break;
  155. case FEC_1_2:
  156. case FEC_AUTO:
  157. break;
  158. default:
  159. return -EINVAL;
  160. }
  161. switch (op->code_rate_LP) {
  162. case FEC_2_3:
  163. tps |= (1 << 4);
  164. break;
  165. case FEC_3_4:
  166. tps |= (2 << 4);
  167. break;
  168. case FEC_5_6:
  169. tps |= (3 << 4);
  170. break;
  171. case FEC_7_8:
  172. tps |= (4 << 4);
  173. break;
  174. case FEC_1_2:
  175. case FEC_AUTO:
  176. break;
  177. case FEC_NONE:
  178. if (op->hierarchy == HIERARCHY_AUTO ||
  179. op->hierarchy == HIERARCHY_NONE)
  180. break;
  181. /* fall through */
  182. default:
  183. return -EINVAL;
  184. }
  185. switch (op->modulation) {
  186. case QPSK:
  187. break;
  188. case QAM_AUTO:
  189. case QAM_16:
  190. tps |= (1 << 13);
  191. break;
  192. case QAM_64:
  193. tps |= (2 << 13);
  194. break;
  195. default:
  196. return -EINVAL;
  197. }
  198. switch (op->transmission_mode) {
  199. case TRANSMISSION_MODE_2K:
  200. case TRANSMISSION_MODE_AUTO:
  201. break;
  202. case TRANSMISSION_MODE_8K:
  203. tps |= (1 << 0);
  204. break;
  205. default:
  206. return -EINVAL;
  207. }
  208. switch (op->guard_interval) {
  209. case GUARD_INTERVAL_1_32:
  210. case GUARD_INTERVAL_AUTO:
  211. break;
  212. case GUARD_INTERVAL_1_16:
  213. tps |= (1 << 2);
  214. break;
  215. case GUARD_INTERVAL_1_8:
  216. tps |= (2 << 2);
  217. break;
  218. case GUARD_INTERVAL_1_4:
  219. tps |= (3 << 2);
  220. break;
  221. default:
  222. return -EINVAL;
  223. }
  224. switch (op->hierarchy) {
  225. case HIERARCHY_AUTO:
  226. case HIERARCHY_NONE:
  227. break;
  228. case HIERARCHY_1:
  229. tps |= (1 << 10);
  230. break;
  231. case HIERARCHY_2:
  232. tps |= (2 << 10);
  233. break;
  234. case HIERARCHY_4:
  235. tps |= (3 << 10);
  236. break;
  237. default:
  238. return -EINVAL;
  239. }
  240. buf[0] = TPS_GIVEN_1; /* TPS_GIVEN_1 and following registers */
  241. buf[1] = msb(tps); /* TPS_GIVEN_(1|0) */
  242. buf[2] = lsb(tps);
  243. buf[3] = 0x50; // old
  244. // buf[3] = 0xf4; // pinnacle
  245. mt352_calc_nominal_rate(state, op->bandwidth_hz, buf+4);
  246. mt352_calc_input_freq(state, buf+6);
  247. if (state->config.no_tuner) {
  248. if (fe->ops.tuner_ops.set_params) {
  249. fe->ops.tuner_ops.set_params(fe);
  250. if (fe->ops.i2c_gate_ctrl)
  251. fe->ops.i2c_gate_ctrl(fe, 0);
  252. }
  253. _mt352_write(fe, buf, 8);
  254. _mt352_write(fe, fsm_go, 2);
  255. } else {
  256. if (fe->ops.tuner_ops.calc_regs) {
  257. fe->ops.tuner_ops.calc_regs(fe, buf+8, 5);
  258. buf[8] <<= 1;
  259. _mt352_write(fe, buf, sizeof(buf));
  260. _mt352_write(fe, tuner_go, 2);
  261. }
  262. }
  263. return 0;
  264. }
  265. static int mt352_get_parameters(struct dvb_frontend* fe,
  266. struct dtv_frontend_properties *op)
  267. {
  268. struct mt352_state* state = fe->demodulator_priv;
  269. u16 tps;
  270. u16 div;
  271. u8 trl;
  272. static const u8 tps_fec_to_api[8] =
  273. {
  274. FEC_1_2,
  275. FEC_2_3,
  276. FEC_3_4,
  277. FEC_5_6,
  278. FEC_7_8,
  279. FEC_AUTO,
  280. FEC_AUTO,
  281. FEC_AUTO
  282. };
  283. if ( (mt352_read_register(state,0x00) & 0xC0) != 0xC0 )
  284. return -EINVAL;
  285. /* Use TPS_RECEIVED-registers, not the TPS_CURRENT-registers because
  286. * the mt352 sometimes works with the wrong parameters
  287. */
  288. tps = (mt352_read_register(state, TPS_RECEIVED_1) << 8) | mt352_read_register(state, TPS_RECEIVED_0);
  289. div = (mt352_read_register(state, CHAN_START_1) << 8) | mt352_read_register(state, CHAN_START_0);
  290. trl = mt352_read_register(state, TRL_NOMINAL_RATE_1);
  291. op->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7];
  292. op->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7];
  293. switch ( (tps >> 13) & 3)
  294. {
  295. case 0:
  296. op->modulation = QPSK;
  297. break;
  298. case 1:
  299. op->modulation = QAM_16;
  300. break;
  301. case 2:
  302. op->modulation = QAM_64;
  303. break;
  304. default:
  305. op->modulation = QAM_AUTO;
  306. break;
  307. }
  308. op->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K : TRANSMISSION_MODE_2K;
  309. switch ( (tps >> 2) & 3)
  310. {
  311. case 0:
  312. op->guard_interval = GUARD_INTERVAL_1_32;
  313. break;
  314. case 1:
  315. op->guard_interval = GUARD_INTERVAL_1_16;
  316. break;
  317. case 2:
  318. op->guard_interval = GUARD_INTERVAL_1_8;
  319. break;
  320. case 3:
  321. op->guard_interval = GUARD_INTERVAL_1_4;
  322. break;
  323. default:
  324. op->guard_interval = GUARD_INTERVAL_AUTO;
  325. break;
  326. }
  327. switch ( (tps >> 10) & 7)
  328. {
  329. case 0:
  330. op->hierarchy = HIERARCHY_NONE;
  331. break;
  332. case 1:
  333. op->hierarchy = HIERARCHY_1;
  334. break;
  335. case 2:
  336. op->hierarchy = HIERARCHY_2;
  337. break;
  338. case 3:
  339. op->hierarchy = HIERARCHY_4;
  340. break;
  341. default:
  342. op->hierarchy = HIERARCHY_AUTO;
  343. break;
  344. }
  345. op->frequency = (500 * (div - IF_FREQUENCYx6)) / 3 * 1000;
  346. if (trl == 0x72)
  347. op->bandwidth_hz = 8000000;
  348. else if (trl == 0x64)
  349. op->bandwidth_hz = 7000000;
  350. else
  351. op->bandwidth_hz = 6000000;
  352. if (mt352_read_register(state, STATUS_2) & 0x02)
  353. op->inversion = INVERSION_OFF;
  354. else
  355. op->inversion = INVERSION_ON;
  356. return 0;
  357. }
  358. static int mt352_read_status(struct dvb_frontend *fe, enum fe_status *status)
  359. {
  360. struct mt352_state* state = fe->demodulator_priv;
  361. int s0, s1, s3;
  362. /* FIXME:
  363. *
  364. * The MT352 design manual from Zarlink states (page 46-47):
  365. *
  366. * Notes about the TUNER_GO register:
  367. *
  368. * If the Read_Tuner_Byte (bit-1) is activated, then the tuner status
  369. * byte is copied from the tuner to the STATUS_3 register and
  370. * completion of the read operation is indicated by bit-5 of the
  371. * INTERRUPT_3 register.
  372. */
  373. if ((s0 = mt352_read_register(state, STATUS_0)) < 0)
  374. return -EREMOTEIO;
  375. if ((s1 = mt352_read_register(state, STATUS_1)) < 0)
  376. return -EREMOTEIO;
  377. if ((s3 = mt352_read_register(state, STATUS_3)) < 0)
  378. return -EREMOTEIO;
  379. *status = 0;
  380. if (s0 & (1 << 4))
  381. *status |= FE_HAS_CARRIER;
  382. if (s0 & (1 << 1))
  383. *status |= FE_HAS_VITERBI;
  384. if (s0 & (1 << 5))
  385. *status |= FE_HAS_LOCK;
  386. if (s1 & (1 << 1))
  387. *status |= FE_HAS_SYNC;
  388. if (s3 & (1 << 6))
  389. *status |= FE_HAS_SIGNAL;
  390. if ((*status & (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)) !=
  391. (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC))
  392. *status &= ~FE_HAS_LOCK;
  393. return 0;
  394. }
  395. static int mt352_read_ber(struct dvb_frontend* fe, u32* ber)
  396. {
  397. struct mt352_state* state = fe->demodulator_priv;
  398. *ber = (mt352_read_register (state, RS_ERR_CNT_2) << 16) |
  399. (mt352_read_register (state, RS_ERR_CNT_1) << 8) |
  400. (mt352_read_register (state, RS_ERR_CNT_0));
  401. return 0;
  402. }
  403. static int mt352_read_signal_strength(struct dvb_frontend* fe, u16* strength)
  404. {
  405. struct mt352_state* state = fe->demodulator_priv;
  406. /* align the 12 bit AGC gain with the most significant bits */
  407. u16 signal = ((mt352_read_register(state, AGC_GAIN_1) & 0x0f) << 12) |
  408. (mt352_read_register(state, AGC_GAIN_0) << 4);
  409. /* inverse of gain is signal strength */
  410. *strength = ~signal;
  411. return 0;
  412. }
  413. static int mt352_read_snr(struct dvb_frontend* fe, u16* snr)
  414. {
  415. struct mt352_state* state = fe->demodulator_priv;
  416. u8 _snr = mt352_read_register (state, SNR);
  417. *snr = (_snr << 8) | _snr;
  418. return 0;
  419. }
  420. static int mt352_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
  421. {
  422. struct mt352_state* state = fe->demodulator_priv;
  423. *ucblocks = (mt352_read_register (state, RS_UBC_1) << 8) |
  424. (mt352_read_register (state, RS_UBC_0));
  425. return 0;
  426. }
  427. static int mt352_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fe_tune_settings)
  428. {
  429. fe_tune_settings->min_delay_ms = 800;
  430. fe_tune_settings->step_size = 0;
  431. fe_tune_settings->max_drift = 0;
  432. return 0;
  433. }
  434. static int mt352_init(struct dvb_frontend* fe)
  435. {
  436. struct mt352_state* state = fe->demodulator_priv;
  437. static u8 mt352_reset_attach [] = { RESET, 0xC0 };
  438. dprintk("%s: hello\n",__func__);
  439. if ((mt352_read_register(state, CLOCK_CTL) & 0x10) == 0 ||
  440. (mt352_read_register(state, CONFIG) & 0x20) == 0) {
  441. /* Do a "hard" reset */
  442. _mt352_write(fe, mt352_reset_attach, sizeof(mt352_reset_attach));
  443. return state->config.demod_init(fe);
  444. }
  445. return 0;
  446. }
  447. static void mt352_release(struct dvb_frontend* fe)
  448. {
  449. struct mt352_state* state = fe->demodulator_priv;
  450. kfree(state);
  451. }
  452. static const struct dvb_frontend_ops mt352_ops;
  453. struct dvb_frontend* mt352_attach(const struct mt352_config* config,
  454. struct i2c_adapter* i2c)
  455. {
  456. struct mt352_state* state = NULL;
  457. /* allocate memory for the internal state */
  458. state = kzalloc(sizeof(struct mt352_state), GFP_KERNEL);
  459. if (state == NULL) goto error;
  460. /* setup the state */
  461. state->i2c = i2c;
  462. memcpy(&state->config,config,sizeof(struct mt352_config));
  463. /* check if the demod is there */
  464. if (mt352_read_register(state, CHIP_ID) != ID_MT352) goto error;
  465. /* create dvb_frontend */
  466. memcpy(&state->frontend.ops, &mt352_ops, sizeof(struct dvb_frontend_ops));
  467. state->frontend.demodulator_priv = state;
  468. return &state->frontend;
  469. error:
  470. kfree(state);
  471. return NULL;
  472. }
  473. static const struct dvb_frontend_ops mt352_ops = {
  474. .delsys = { SYS_DVBT },
  475. .info = {
  476. .name = "Zarlink MT352 DVB-T",
  477. .frequency_min_hz = 174 * MHz,
  478. .frequency_max_hz = 862 * MHz,
  479. .frequency_stepsize_hz = 166667,
  480. .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
  481. FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
  482. FE_CAN_FEC_AUTO |
  483. FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
  484. FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
  485. FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER |
  486. FE_CAN_MUTE_TS
  487. },
  488. .release = mt352_release,
  489. .init = mt352_init,
  490. .sleep = mt352_sleep,
  491. .write = _mt352_write,
  492. .set_frontend = mt352_set_parameters,
  493. .get_frontend = mt352_get_parameters,
  494. .get_tune_settings = mt352_get_tune_settings,
  495. .read_status = mt352_read_status,
  496. .read_ber = mt352_read_ber,
  497. .read_signal_strength = mt352_read_signal_strength,
  498. .read_snr = mt352_read_snr,
  499. .read_ucblocks = mt352_read_ucblocks,
  500. };
  501. module_param(debug, int, 0644);
  502. MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
  503. MODULE_DESCRIPTION("Zarlink MT352 DVB-T Demodulator driver");
  504. MODULE_AUTHOR("Holger Waechtler, Daniel Mack, Antonio Mancuso");
  505. MODULE_LICENSE("GPL");
  506. EXPORT_SYMBOL(mt352_attach);