mb86a16.c 45 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. Fujitsu MB86A16 DVB-S/DSS DC Receiver driver
  4. Copyright (C) Manu Abraham (abraham.manu@gmail.com)
  5. */
  6. #include <linux/init.h>
  7. #include <linux/kernel.h>
  8. #include <linux/module.h>
  9. #include <linux/moduleparam.h>
  10. #include <linux/slab.h>
  11. #include <media/dvb_frontend.h>
  12. #include "mb86a16.h"
  13. #include "mb86a16_priv.h"
  14. static unsigned int verbose = 5;
  15. module_param(verbose, int, 0644);
  16. struct mb86a16_state {
  17. struct i2c_adapter *i2c_adap;
  18. const struct mb86a16_config *config;
  19. struct dvb_frontend frontend;
  20. /* tuning parameters */
  21. int frequency;
  22. int srate;
  23. /* Internal stuff */
  24. int master_clk;
  25. int deci;
  26. int csel;
  27. int rsel;
  28. };
  29. #define MB86A16_ERROR 0
  30. #define MB86A16_NOTICE 1
  31. #define MB86A16_INFO 2
  32. #define MB86A16_DEBUG 3
  33. #define dprintk(x, y, z, format, arg...) do { \
  34. if (z) { \
  35. if ((x > MB86A16_ERROR) && (x > y)) \
  36. printk(KERN_ERR "%s: " format "\n", __func__, ##arg); \
  37. else if ((x > MB86A16_NOTICE) && (x > y)) \
  38. printk(KERN_NOTICE "%s: " format "\n", __func__, ##arg); \
  39. else if ((x > MB86A16_INFO) && (x > y)) \
  40. printk(KERN_INFO "%s: " format "\n", __func__, ##arg); \
  41. else if ((x > MB86A16_DEBUG) && (x > y)) \
  42. printk(KERN_DEBUG "%s: " format "\n", __func__, ##arg); \
  43. } else { \
  44. if (x > y) \
  45. printk(format, ##arg); \
  46. } \
  47. } while (0)
  48. #define TRACE_IN dprintk(verbose, MB86A16_DEBUG, 1, "-->()")
  49. #define TRACE_OUT dprintk(verbose, MB86A16_DEBUG, 1, "()-->")
  50. static int mb86a16_write(struct mb86a16_state *state, u8 reg, u8 val)
  51. {
  52. int ret;
  53. u8 buf[] = { reg, val };
  54. struct i2c_msg msg = {
  55. .addr = state->config->demod_address,
  56. .flags = 0,
  57. .buf = buf,
  58. .len = 2
  59. };
  60. dprintk(verbose, MB86A16_DEBUG, 1,
  61. "writing to [0x%02x],Reg[0x%02x],Data[0x%02x]",
  62. state->config->demod_address, buf[0], buf[1]);
  63. ret = i2c_transfer(state->i2c_adap, &msg, 1);
  64. return (ret != 1) ? -EREMOTEIO : 0;
  65. }
  66. static int mb86a16_read(struct mb86a16_state *state, u8 reg, u8 *val)
  67. {
  68. int ret;
  69. u8 b0[] = { reg };
  70. u8 b1[] = { 0 };
  71. struct i2c_msg msg[] = {
  72. {
  73. .addr = state->config->demod_address,
  74. .flags = 0,
  75. .buf = b0,
  76. .len = 1
  77. }, {
  78. .addr = state->config->demod_address,
  79. .flags = I2C_M_RD,
  80. .buf = b1,
  81. .len = 1
  82. }
  83. };
  84. ret = i2c_transfer(state->i2c_adap, msg, 2);
  85. if (ret != 2) {
  86. dprintk(verbose, MB86A16_ERROR, 1, "read error(reg=0x%02x, ret=%i)",
  87. reg, ret);
  88. if (ret < 0)
  89. return ret;
  90. return -EREMOTEIO;
  91. }
  92. *val = b1[0];
  93. return ret;
  94. }
  95. static int CNTM_set(struct mb86a16_state *state,
  96. unsigned char timint1,
  97. unsigned char timint2,
  98. unsigned char cnext)
  99. {
  100. unsigned char val;
  101. val = (timint1 << 4) | (timint2 << 2) | cnext;
  102. if (mb86a16_write(state, MB86A16_CNTMR, val) < 0)
  103. goto err;
  104. return 0;
  105. err:
  106. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  107. return -EREMOTEIO;
  108. }
  109. static int smrt_set(struct mb86a16_state *state, int rate)
  110. {
  111. int tmp ;
  112. int m ;
  113. unsigned char STOFS0, STOFS1;
  114. m = 1 << state->deci;
  115. tmp = (8192 * state->master_clk - 2 * m * rate * 8192 + state->master_clk / 2) / state->master_clk;
  116. STOFS0 = tmp & 0x0ff;
  117. STOFS1 = (tmp & 0xf00) >> 8;
  118. if (mb86a16_write(state, MB86A16_SRATE1, (state->deci << 2) |
  119. (state->csel << 1) |
  120. state->rsel) < 0)
  121. goto err;
  122. if (mb86a16_write(state, MB86A16_SRATE2, STOFS0) < 0)
  123. goto err;
  124. if (mb86a16_write(state, MB86A16_SRATE3, STOFS1) < 0)
  125. goto err;
  126. return 0;
  127. err:
  128. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  129. return -1;
  130. }
  131. static int srst(struct mb86a16_state *state)
  132. {
  133. if (mb86a16_write(state, MB86A16_RESET, 0x04) < 0)
  134. goto err;
  135. return 0;
  136. err:
  137. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  138. return -EREMOTEIO;
  139. }
  140. static int afcex_data_set(struct mb86a16_state *state,
  141. unsigned char AFCEX_L,
  142. unsigned char AFCEX_H)
  143. {
  144. if (mb86a16_write(state, MB86A16_AFCEXL, AFCEX_L) < 0)
  145. goto err;
  146. if (mb86a16_write(state, MB86A16_AFCEXH, AFCEX_H) < 0)
  147. goto err;
  148. return 0;
  149. err:
  150. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  151. return -1;
  152. }
  153. static int afcofs_data_set(struct mb86a16_state *state,
  154. unsigned char AFCEX_L,
  155. unsigned char AFCEX_H)
  156. {
  157. if (mb86a16_write(state, 0x58, AFCEX_L) < 0)
  158. goto err;
  159. if (mb86a16_write(state, 0x59, AFCEX_H) < 0)
  160. goto err;
  161. return 0;
  162. err:
  163. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  164. return -EREMOTEIO;
  165. }
  166. static int stlp_set(struct mb86a16_state *state,
  167. unsigned char STRAS,
  168. unsigned char STRBS)
  169. {
  170. if (mb86a16_write(state, MB86A16_STRFILTCOEF1, (STRBS << 3) | (STRAS)) < 0)
  171. goto err;
  172. return 0;
  173. err:
  174. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  175. return -EREMOTEIO;
  176. }
  177. static int Vi_set(struct mb86a16_state *state, unsigned char ETH, unsigned char VIA)
  178. {
  179. if (mb86a16_write(state, MB86A16_VISET2, 0x04) < 0)
  180. goto err;
  181. if (mb86a16_write(state, MB86A16_VISET3, 0xf5) < 0)
  182. goto err;
  183. return 0;
  184. err:
  185. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  186. return -EREMOTEIO;
  187. }
  188. static int initial_set(struct mb86a16_state *state)
  189. {
  190. if (stlp_set(state, 5, 7))
  191. goto err;
  192. udelay(100);
  193. if (afcex_data_set(state, 0, 0))
  194. goto err;
  195. udelay(100);
  196. if (afcofs_data_set(state, 0, 0))
  197. goto err;
  198. udelay(100);
  199. if (mb86a16_write(state, MB86A16_CRLFILTCOEF1, 0x16) < 0)
  200. goto err;
  201. if (mb86a16_write(state, 0x2f, 0x21) < 0)
  202. goto err;
  203. if (mb86a16_write(state, MB86A16_VIMAG, 0x38) < 0)
  204. goto err;
  205. if (mb86a16_write(state, MB86A16_FAGCS1, 0x00) < 0)
  206. goto err;
  207. if (mb86a16_write(state, MB86A16_FAGCS2, 0x1c) < 0)
  208. goto err;
  209. if (mb86a16_write(state, MB86A16_FAGCS3, 0x20) < 0)
  210. goto err;
  211. if (mb86a16_write(state, MB86A16_FAGCS4, 0x1e) < 0)
  212. goto err;
  213. if (mb86a16_write(state, MB86A16_FAGCS5, 0x23) < 0)
  214. goto err;
  215. if (mb86a16_write(state, 0x54, 0xff) < 0)
  216. goto err;
  217. if (mb86a16_write(state, MB86A16_TSOUT, 0x00) < 0)
  218. goto err;
  219. return 0;
  220. err:
  221. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  222. return -EREMOTEIO;
  223. }
  224. static int S01T_set(struct mb86a16_state *state,
  225. unsigned char s1t,
  226. unsigned s0t)
  227. {
  228. if (mb86a16_write(state, 0x33, (s1t << 3) | s0t) < 0)
  229. goto err;
  230. return 0;
  231. err:
  232. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  233. return -EREMOTEIO;
  234. }
  235. static int EN_set(struct mb86a16_state *state,
  236. int cren,
  237. int afcen)
  238. {
  239. unsigned char val;
  240. val = 0x7a | (cren << 7) | (afcen << 2);
  241. if (mb86a16_write(state, 0x49, val) < 0)
  242. goto err;
  243. return 0;
  244. err:
  245. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  246. return -EREMOTEIO;
  247. }
  248. static int AFCEXEN_set(struct mb86a16_state *state,
  249. int afcexen,
  250. int smrt)
  251. {
  252. unsigned char AFCA ;
  253. if (smrt > 18875)
  254. AFCA = 4;
  255. else if (smrt > 9375)
  256. AFCA = 3;
  257. else if (smrt > 2250)
  258. AFCA = 2;
  259. else
  260. AFCA = 1;
  261. if (mb86a16_write(state, 0x2a, 0x02 | (afcexen << 5) | (AFCA << 2)) < 0)
  262. goto err;
  263. return 0;
  264. err:
  265. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  266. return -EREMOTEIO;
  267. }
  268. static int DAGC_data_set(struct mb86a16_state *state,
  269. unsigned char DAGCA,
  270. unsigned char DAGCW)
  271. {
  272. if (mb86a16_write(state, 0x2d, (DAGCA << 3) | DAGCW) < 0)
  273. goto err;
  274. return 0;
  275. err:
  276. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  277. return -EREMOTEIO;
  278. }
  279. static void smrt_info_get(struct mb86a16_state *state, int rate)
  280. {
  281. if (rate >= 37501) {
  282. state->deci = 0; state->csel = 0; state->rsel = 0;
  283. } else if (rate >= 30001) {
  284. state->deci = 0; state->csel = 0; state->rsel = 1;
  285. } else if (rate >= 26251) {
  286. state->deci = 0; state->csel = 1; state->rsel = 0;
  287. } else if (rate >= 22501) {
  288. state->deci = 0; state->csel = 1; state->rsel = 1;
  289. } else if (rate >= 18751) {
  290. state->deci = 1; state->csel = 0; state->rsel = 0;
  291. } else if (rate >= 15001) {
  292. state->deci = 1; state->csel = 0; state->rsel = 1;
  293. } else if (rate >= 13126) {
  294. state->deci = 1; state->csel = 1; state->rsel = 0;
  295. } else if (rate >= 11251) {
  296. state->deci = 1; state->csel = 1; state->rsel = 1;
  297. } else if (rate >= 9376) {
  298. state->deci = 2; state->csel = 0; state->rsel = 0;
  299. } else if (rate >= 7501) {
  300. state->deci = 2; state->csel = 0; state->rsel = 1;
  301. } else if (rate >= 6563) {
  302. state->deci = 2; state->csel = 1; state->rsel = 0;
  303. } else if (rate >= 5626) {
  304. state->deci = 2; state->csel = 1; state->rsel = 1;
  305. } else if (rate >= 4688) {
  306. state->deci = 3; state->csel = 0; state->rsel = 0;
  307. } else if (rate >= 3751) {
  308. state->deci = 3; state->csel = 0; state->rsel = 1;
  309. } else if (rate >= 3282) {
  310. state->deci = 3; state->csel = 1; state->rsel = 0;
  311. } else if (rate >= 2814) {
  312. state->deci = 3; state->csel = 1; state->rsel = 1;
  313. } else if (rate >= 2344) {
  314. state->deci = 4; state->csel = 0; state->rsel = 0;
  315. } else if (rate >= 1876) {
  316. state->deci = 4; state->csel = 0; state->rsel = 1;
  317. } else if (rate >= 1641) {
  318. state->deci = 4; state->csel = 1; state->rsel = 0;
  319. } else if (rate >= 1407) {
  320. state->deci = 4; state->csel = 1; state->rsel = 1;
  321. } else if (rate >= 1172) {
  322. state->deci = 5; state->csel = 0; state->rsel = 0;
  323. } else if (rate >= 939) {
  324. state->deci = 5; state->csel = 0; state->rsel = 1;
  325. } else if (rate >= 821) {
  326. state->deci = 5; state->csel = 1; state->rsel = 0;
  327. } else {
  328. state->deci = 5; state->csel = 1; state->rsel = 1;
  329. }
  330. if (state->csel == 0)
  331. state->master_clk = 92000;
  332. else
  333. state->master_clk = 61333;
  334. }
  335. static int signal_det(struct mb86a16_state *state,
  336. int smrt,
  337. unsigned char *SIG)
  338. {
  339. int ret;
  340. int smrtd;
  341. unsigned char S[3];
  342. int i;
  343. if (*SIG > 45) {
  344. if (CNTM_set(state, 2, 1, 2) < 0) {
  345. dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
  346. return -1;
  347. }
  348. } else {
  349. if (CNTM_set(state, 3, 1, 2) < 0) {
  350. dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
  351. return -1;
  352. }
  353. }
  354. for (i = 0; i < 3; i++) {
  355. if (i == 0)
  356. smrtd = smrt * 98 / 100;
  357. else if (i == 1)
  358. smrtd = smrt;
  359. else
  360. smrtd = smrt * 102 / 100;
  361. smrt_info_get(state, smrtd);
  362. smrt_set(state, smrtd);
  363. srst(state);
  364. msleep_interruptible(10);
  365. if (mb86a16_read(state, 0x37, &(S[i])) != 2) {
  366. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  367. return -EREMOTEIO;
  368. }
  369. }
  370. if ((S[1] > S[0] * 112 / 100) && (S[1] > S[2] * 112 / 100))
  371. ret = 1;
  372. else
  373. ret = 0;
  374. *SIG = S[1];
  375. if (CNTM_set(state, 0, 1, 2) < 0) {
  376. dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
  377. return -1;
  378. }
  379. return ret;
  380. }
  381. static int rf_val_set(struct mb86a16_state *state,
  382. int f,
  383. int smrt,
  384. unsigned char R)
  385. {
  386. unsigned char C, F, B;
  387. int M;
  388. unsigned char rf_val[5];
  389. int ack = -1;
  390. if (smrt > 37750)
  391. C = 1;
  392. else if (smrt > 18875)
  393. C = 2;
  394. else if (smrt > 5500)
  395. C = 3;
  396. else
  397. C = 4;
  398. if (smrt > 30500)
  399. F = 3;
  400. else if (smrt > 9375)
  401. F = 1;
  402. else if (smrt > 4625)
  403. F = 0;
  404. else
  405. F = 2;
  406. if (f < 1060)
  407. B = 0;
  408. else if (f < 1175)
  409. B = 1;
  410. else if (f < 1305)
  411. B = 2;
  412. else if (f < 1435)
  413. B = 3;
  414. else if (f < 1570)
  415. B = 4;
  416. else if (f < 1715)
  417. B = 5;
  418. else if (f < 1845)
  419. B = 6;
  420. else if (f < 1980)
  421. B = 7;
  422. else if (f < 2080)
  423. B = 8;
  424. else
  425. B = 9;
  426. M = f * (1 << R) / 2;
  427. rf_val[0] = 0x01 | (C << 3) | (F << 1);
  428. rf_val[1] = (R << 5) | ((M & 0x1f000) >> 12);
  429. rf_val[2] = (M & 0x00ff0) >> 4;
  430. rf_val[3] = ((M & 0x0000f) << 4) | B;
  431. /* Frequency Set */
  432. if (mb86a16_write(state, 0x21, rf_val[0]) < 0)
  433. ack = 0;
  434. if (mb86a16_write(state, 0x22, rf_val[1]) < 0)
  435. ack = 0;
  436. if (mb86a16_write(state, 0x23, rf_val[2]) < 0)
  437. ack = 0;
  438. if (mb86a16_write(state, 0x24, rf_val[3]) < 0)
  439. ack = 0;
  440. if (mb86a16_write(state, 0x25, 0x01) < 0)
  441. ack = 0;
  442. if (ack == 0) {
  443. dprintk(verbose, MB86A16_ERROR, 1, "RF Setup - I2C transfer error");
  444. return -EREMOTEIO;
  445. }
  446. return 0;
  447. }
  448. static int afcerr_chk(struct mb86a16_state *state)
  449. {
  450. unsigned char AFCM_L, AFCM_H ;
  451. int AFCM ;
  452. int afcm, afcerr ;
  453. if (mb86a16_read(state, 0x0e, &AFCM_L) != 2)
  454. goto err;
  455. if (mb86a16_read(state, 0x0f, &AFCM_H) != 2)
  456. goto err;
  457. AFCM = (AFCM_H << 8) + AFCM_L;
  458. if (AFCM > 2048)
  459. afcm = AFCM - 4096;
  460. else
  461. afcm = AFCM;
  462. afcerr = afcm * state->master_clk / 8192;
  463. return afcerr;
  464. err:
  465. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  466. return -EREMOTEIO;
  467. }
  468. static int dagcm_val_get(struct mb86a16_state *state)
  469. {
  470. int DAGCM;
  471. unsigned char DAGCM_H, DAGCM_L;
  472. if (mb86a16_read(state, 0x45, &DAGCM_L) != 2)
  473. goto err;
  474. if (mb86a16_read(state, 0x46, &DAGCM_H) != 2)
  475. goto err;
  476. DAGCM = (DAGCM_H << 8) + DAGCM_L;
  477. return DAGCM;
  478. err:
  479. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  480. return -EREMOTEIO;
  481. }
  482. static int mb86a16_read_status(struct dvb_frontend *fe, enum fe_status *status)
  483. {
  484. u8 stat, stat2;
  485. struct mb86a16_state *state = fe->demodulator_priv;
  486. *status = 0;
  487. if (mb86a16_read(state, MB86A16_SIG1, &stat) != 2)
  488. goto err;
  489. if (mb86a16_read(state, MB86A16_SIG2, &stat2) != 2)
  490. goto err;
  491. if ((stat > 25) && (stat2 > 25))
  492. *status |= FE_HAS_SIGNAL;
  493. if ((stat > 45) && (stat2 > 45))
  494. *status |= FE_HAS_CARRIER;
  495. if (mb86a16_read(state, MB86A16_STATUS, &stat) != 2)
  496. goto err;
  497. if (stat & 0x01)
  498. *status |= FE_HAS_SYNC;
  499. if (stat & 0x01)
  500. *status |= FE_HAS_VITERBI;
  501. if (mb86a16_read(state, MB86A16_FRAMESYNC, &stat) != 2)
  502. goto err;
  503. if ((stat & 0x0f) && (*status & FE_HAS_VITERBI))
  504. *status |= FE_HAS_LOCK;
  505. return 0;
  506. err:
  507. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  508. return -EREMOTEIO;
  509. }
  510. static int sync_chk(struct mb86a16_state *state,
  511. unsigned char *VIRM)
  512. {
  513. unsigned char val;
  514. int sync;
  515. if (mb86a16_read(state, 0x0d, &val) != 2)
  516. goto err;
  517. dprintk(verbose, MB86A16_INFO, 1, "Status = %02x,", val);
  518. sync = val & 0x01;
  519. *VIRM = (val & 0x1c) >> 2;
  520. return sync;
  521. err:
  522. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  523. *VIRM = 0;
  524. return -EREMOTEIO;
  525. }
  526. static int freqerr_chk(struct mb86a16_state *state,
  527. int fTP,
  528. int smrt,
  529. int unit)
  530. {
  531. unsigned char CRM, AFCML, AFCMH;
  532. unsigned char temp1, temp2, temp3;
  533. int crm, afcm, AFCM;
  534. int crrerr, afcerr; /* kHz */
  535. int frqerr; /* MHz */
  536. int afcen, afcexen = 0;
  537. int R, M, fOSC, fOSC_OFS;
  538. if (mb86a16_read(state, 0x43, &CRM) != 2)
  539. goto err;
  540. if (CRM > 127)
  541. crm = CRM - 256;
  542. else
  543. crm = CRM;
  544. crrerr = smrt * crm / 256;
  545. if (mb86a16_read(state, 0x49, &temp1) != 2)
  546. goto err;
  547. afcen = (temp1 & 0x04) >> 2;
  548. if (afcen == 0) {
  549. if (mb86a16_read(state, 0x2a, &temp1) != 2)
  550. goto err;
  551. afcexen = (temp1 & 0x20) >> 5;
  552. }
  553. if (afcen == 1) {
  554. if (mb86a16_read(state, 0x0e, &AFCML) != 2)
  555. goto err;
  556. if (mb86a16_read(state, 0x0f, &AFCMH) != 2)
  557. goto err;
  558. } else if (afcexen == 1) {
  559. if (mb86a16_read(state, 0x2b, &AFCML) != 2)
  560. goto err;
  561. if (mb86a16_read(state, 0x2c, &AFCMH) != 2)
  562. goto err;
  563. }
  564. if ((afcen == 1) || (afcexen == 1)) {
  565. smrt_info_get(state, smrt);
  566. AFCM = ((AFCMH & 0x01) << 8) + AFCML;
  567. if (AFCM > 255)
  568. afcm = AFCM - 512;
  569. else
  570. afcm = AFCM;
  571. afcerr = afcm * state->master_clk / 8192;
  572. } else
  573. afcerr = 0;
  574. if (mb86a16_read(state, 0x22, &temp1) != 2)
  575. goto err;
  576. if (mb86a16_read(state, 0x23, &temp2) != 2)
  577. goto err;
  578. if (mb86a16_read(state, 0x24, &temp3) != 2)
  579. goto err;
  580. R = (temp1 & 0xe0) >> 5;
  581. M = ((temp1 & 0x1f) << 12) + (temp2 << 4) + (temp3 >> 4);
  582. if (R == 0)
  583. fOSC = 2 * M;
  584. else
  585. fOSC = M;
  586. fOSC_OFS = fOSC - fTP;
  587. if (unit == 0) { /* MHz */
  588. if (crrerr + afcerr + fOSC_OFS * 1000 >= 0)
  589. frqerr = (crrerr + afcerr + fOSC_OFS * 1000 + 500) / 1000;
  590. else
  591. frqerr = (crrerr + afcerr + fOSC_OFS * 1000 - 500) / 1000;
  592. } else { /* kHz */
  593. frqerr = crrerr + afcerr + fOSC_OFS * 1000;
  594. }
  595. return frqerr;
  596. err:
  597. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  598. return -EREMOTEIO;
  599. }
  600. static unsigned char vco_dev_get(struct mb86a16_state *state, int smrt)
  601. {
  602. unsigned char R;
  603. if (smrt > 9375)
  604. R = 0;
  605. else
  606. R = 1;
  607. return R;
  608. }
  609. static void swp_info_get(struct mb86a16_state *state,
  610. int fOSC_start,
  611. int smrt,
  612. int v, int R,
  613. int swp_ofs,
  614. int *fOSC,
  615. int *afcex_freq,
  616. unsigned char *AFCEX_L,
  617. unsigned char *AFCEX_H)
  618. {
  619. int AFCEX ;
  620. int crnt_swp_freq ;
  621. crnt_swp_freq = fOSC_start * 1000 + v * swp_ofs;
  622. if (R == 0)
  623. *fOSC = (crnt_swp_freq + 1000) / 2000 * 2;
  624. else
  625. *fOSC = (crnt_swp_freq + 500) / 1000;
  626. if (*fOSC >= crnt_swp_freq)
  627. *afcex_freq = *fOSC * 1000 - crnt_swp_freq;
  628. else
  629. *afcex_freq = crnt_swp_freq - *fOSC * 1000;
  630. AFCEX = *afcex_freq * 8192 / state->master_clk;
  631. *AFCEX_L = AFCEX & 0x00ff;
  632. *AFCEX_H = (AFCEX & 0x0f00) >> 8;
  633. }
  634. static int swp_freq_calcuation(struct mb86a16_state *state, int i, int v, int *V, int vmax, int vmin,
  635. int SIGMIN, int fOSC, int afcex_freq, int swp_ofs, unsigned char *SIG1)
  636. {
  637. int swp_freq ;
  638. if ((i % 2 == 1) && (v <= vmax)) {
  639. /* positive v (case 1) */
  640. if ((v - 1 == vmin) &&
  641. (*(V + 30 + v) >= 0) &&
  642. (*(V + 30 + v - 1) >= 0) &&
  643. (*(V + 30 + v - 1) > *(V + 30 + v)) &&
  644. (*(V + 30 + v - 1) > SIGMIN)) {
  645. swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
  646. *SIG1 = *(V + 30 + v - 1);
  647. } else if ((v == vmax) &&
  648. (*(V + 30 + v) >= 0) &&
  649. (*(V + 30 + v - 1) >= 0) &&
  650. (*(V + 30 + v) > *(V + 30 + v - 1)) &&
  651. (*(V + 30 + v) > SIGMIN)) {
  652. /* (case 2) */
  653. swp_freq = fOSC * 1000 + afcex_freq;
  654. *SIG1 = *(V + 30 + v);
  655. } else if ((*(V + 30 + v) > 0) &&
  656. (*(V + 30 + v - 1) > 0) &&
  657. (*(V + 30 + v - 2) > 0) &&
  658. (*(V + 30 + v - 3) > 0) &&
  659. (*(V + 30 + v - 1) > *(V + 30 + v)) &&
  660. (*(V + 30 + v - 2) > *(V + 30 + v - 3)) &&
  661. ((*(V + 30 + v - 1) > SIGMIN) ||
  662. (*(V + 30 + v - 2) > SIGMIN))) {
  663. /* (case 3) */
  664. if (*(V + 30 + v - 1) >= *(V + 30 + v - 2)) {
  665. swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
  666. *SIG1 = *(V + 30 + v - 1);
  667. } else {
  668. swp_freq = fOSC * 1000 + afcex_freq - swp_ofs * 2;
  669. *SIG1 = *(V + 30 + v - 2);
  670. }
  671. } else if ((v == vmax) &&
  672. (*(V + 30 + v) >= 0) &&
  673. (*(V + 30 + v - 1) >= 0) &&
  674. (*(V + 30 + v - 2) >= 0) &&
  675. (*(V + 30 + v) > *(V + 30 + v - 2)) &&
  676. (*(V + 30 + v - 1) > *(V + 30 + v - 2)) &&
  677. ((*(V + 30 + v) > SIGMIN) ||
  678. (*(V + 30 + v - 1) > SIGMIN))) {
  679. /* (case 4) */
  680. if (*(V + 30 + v) >= *(V + 30 + v - 1)) {
  681. swp_freq = fOSC * 1000 + afcex_freq;
  682. *SIG1 = *(V + 30 + v);
  683. } else {
  684. swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
  685. *SIG1 = *(V + 30 + v - 1);
  686. }
  687. } else {
  688. swp_freq = -1 ;
  689. }
  690. } else if ((i % 2 == 0) && (v >= vmin)) {
  691. /* Negative v (case 1) */
  692. if ((*(V + 30 + v) > 0) &&
  693. (*(V + 30 + v + 1) > 0) &&
  694. (*(V + 30 + v + 2) > 0) &&
  695. (*(V + 30 + v + 1) > *(V + 30 + v)) &&
  696. (*(V + 30 + v + 1) > *(V + 30 + v + 2)) &&
  697. (*(V + 30 + v + 1) > SIGMIN)) {
  698. swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
  699. *SIG1 = *(V + 30 + v + 1);
  700. } else if ((v + 1 == vmax) &&
  701. (*(V + 30 + v) >= 0) &&
  702. (*(V + 30 + v + 1) >= 0) &&
  703. (*(V + 30 + v + 1) > *(V + 30 + v)) &&
  704. (*(V + 30 + v + 1) > SIGMIN)) {
  705. /* (case 2) */
  706. swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
  707. *SIG1 = *(V + 30 + v);
  708. } else if ((v == vmin) &&
  709. (*(V + 30 + v) > 0) &&
  710. (*(V + 30 + v + 1) > 0) &&
  711. (*(V + 30 + v + 2) > 0) &&
  712. (*(V + 30 + v) > *(V + 30 + v + 1)) &&
  713. (*(V + 30 + v) > *(V + 30 + v + 2)) &&
  714. (*(V + 30 + v) > SIGMIN)) {
  715. /* (case 3) */
  716. swp_freq = fOSC * 1000 + afcex_freq;
  717. *SIG1 = *(V + 30 + v);
  718. } else if ((*(V + 30 + v) >= 0) &&
  719. (*(V + 30 + v + 1) >= 0) &&
  720. (*(V + 30 + v + 2) >= 0) &&
  721. (*(V + 30 + v + 3) >= 0) &&
  722. (*(V + 30 + v + 1) > *(V + 30 + v)) &&
  723. (*(V + 30 + v + 2) > *(V + 30 + v + 3)) &&
  724. ((*(V + 30 + v + 1) > SIGMIN) ||
  725. (*(V + 30 + v + 2) > SIGMIN))) {
  726. /* (case 4) */
  727. if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) {
  728. swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
  729. *SIG1 = *(V + 30 + v + 1);
  730. } else {
  731. swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2;
  732. *SIG1 = *(V + 30 + v + 2);
  733. }
  734. } else if ((*(V + 30 + v) >= 0) &&
  735. (*(V + 30 + v + 1) >= 0) &&
  736. (*(V + 30 + v + 2) >= 0) &&
  737. (*(V + 30 + v + 3) >= 0) &&
  738. (*(V + 30 + v) > *(V + 30 + v + 2)) &&
  739. (*(V + 30 + v + 1) > *(V + 30 + v + 2)) &&
  740. (*(V + 30 + v) > *(V + 30 + v + 3)) &&
  741. (*(V + 30 + v + 1) > *(V + 30 + v + 3)) &&
  742. ((*(V + 30 + v) > SIGMIN) ||
  743. (*(V + 30 + v + 1) > SIGMIN))) {
  744. /* (case 5) */
  745. if (*(V + 30 + v) >= *(V + 30 + v + 1)) {
  746. swp_freq = fOSC * 1000 + afcex_freq;
  747. *SIG1 = *(V + 30 + v);
  748. } else {
  749. swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
  750. *SIG1 = *(V + 30 + v + 1);
  751. }
  752. } else if ((v + 2 == vmin) &&
  753. (*(V + 30 + v) >= 0) &&
  754. (*(V + 30 + v + 1) >= 0) &&
  755. (*(V + 30 + v + 2) >= 0) &&
  756. (*(V + 30 + v + 1) > *(V + 30 + v)) &&
  757. (*(V + 30 + v + 2) > *(V + 30 + v)) &&
  758. ((*(V + 30 + v + 1) > SIGMIN) ||
  759. (*(V + 30 + v + 2) > SIGMIN))) {
  760. /* (case 6) */
  761. if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) {
  762. swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
  763. *SIG1 = *(V + 30 + v + 1);
  764. } else {
  765. swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2;
  766. *SIG1 = *(V + 30 + v + 2);
  767. }
  768. } else if ((vmax == 0) && (vmin == 0) && (*(V + 30 + v) > SIGMIN)) {
  769. swp_freq = fOSC * 1000;
  770. *SIG1 = *(V + 30 + v);
  771. } else
  772. swp_freq = -1;
  773. } else
  774. swp_freq = -1;
  775. return swp_freq;
  776. }
  777. static void swp_info_get2(struct mb86a16_state *state,
  778. int smrt,
  779. int R,
  780. int swp_freq,
  781. int *afcex_freq,
  782. int *fOSC,
  783. unsigned char *AFCEX_L,
  784. unsigned char *AFCEX_H)
  785. {
  786. int AFCEX ;
  787. if (R == 0)
  788. *fOSC = (swp_freq + 1000) / 2000 * 2;
  789. else
  790. *fOSC = (swp_freq + 500) / 1000;
  791. if (*fOSC >= swp_freq)
  792. *afcex_freq = *fOSC * 1000 - swp_freq;
  793. else
  794. *afcex_freq = swp_freq - *fOSC * 1000;
  795. AFCEX = *afcex_freq * 8192 / state->master_clk;
  796. *AFCEX_L = AFCEX & 0x00ff;
  797. *AFCEX_H = (AFCEX & 0x0f00) >> 8;
  798. }
  799. static void afcex_info_get(struct mb86a16_state *state,
  800. int afcex_freq,
  801. unsigned char *AFCEX_L,
  802. unsigned char *AFCEX_H)
  803. {
  804. int AFCEX ;
  805. AFCEX = afcex_freq * 8192 / state->master_clk;
  806. *AFCEX_L = AFCEX & 0x00ff;
  807. *AFCEX_H = (AFCEX & 0x0f00) >> 8;
  808. }
  809. static int SEQ_set(struct mb86a16_state *state, unsigned char loop)
  810. {
  811. /* SLOCK0 = 0 */
  812. if (mb86a16_write(state, 0x32, 0x02 | (loop << 2)) < 0) {
  813. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  814. return -EREMOTEIO;
  815. }
  816. return 0;
  817. }
  818. static int iq_vt_set(struct mb86a16_state *state, unsigned char IQINV)
  819. {
  820. /* Viterbi Rate, IQ Settings */
  821. if (mb86a16_write(state, 0x06, 0xdf | (IQINV << 5)) < 0) {
  822. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  823. return -EREMOTEIO;
  824. }
  825. return 0;
  826. }
  827. static int FEC_srst(struct mb86a16_state *state)
  828. {
  829. if (mb86a16_write(state, MB86A16_RESET, 0x02) < 0) {
  830. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  831. return -EREMOTEIO;
  832. }
  833. return 0;
  834. }
  835. static int S2T_set(struct mb86a16_state *state, unsigned char S2T)
  836. {
  837. if (mb86a16_write(state, 0x34, 0x70 | S2T) < 0) {
  838. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  839. return -EREMOTEIO;
  840. }
  841. return 0;
  842. }
  843. static int S45T_set(struct mb86a16_state *state, unsigned char S4T, unsigned char S5T)
  844. {
  845. if (mb86a16_write(state, 0x35, 0x00 | (S5T << 4) | S4T) < 0) {
  846. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  847. return -EREMOTEIO;
  848. }
  849. return 0;
  850. }
  851. static int mb86a16_set_fe(struct mb86a16_state *state)
  852. {
  853. u8 agcval, cnmval;
  854. int i, j;
  855. int fOSC = 0;
  856. int fOSC_start = 0;
  857. int wait_t;
  858. int fcp;
  859. int swp_ofs;
  860. int V[60];
  861. u8 SIG1MIN;
  862. unsigned char CREN, AFCEN, AFCEXEN;
  863. unsigned char SIG1;
  864. unsigned char TIMINT1, TIMINT2, TIMEXT;
  865. unsigned char S0T, S1T;
  866. unsigned char S2T;
  867. /* unsigned char S2T, S3T; */
  868. unsigned char S4T, S5T;
  869. unsigned char AFCEX_L, AFCEX_H;
  870. unsigned char R;
  871. unsigned char VIRM;
  872. unsigned char ETH, VIA;
  873. unsigned char junk;
  874. int loop;
  875. int ftemp;
  876. int v, vmax, vmin;
  877. int vmax_his, vmin_his;
  878. int swp_freq, prev_swp_freq[20];
  879. int prev_freq_num;
  880. int signal_dupl;
  881. int afcex_freq;
  882. int signal;
  883. int afcerr;
  884. int temp_freq, delta_freq;
  885. int dagcm[4];
  886. int smrt_d;
  887. /* int freq_err; */
  888. int n;
  889. int ret = -1;
  890. int sync;
  891. dprintk(verbose, MB86A16_INFO, 1, "freq=%d Mhz, symbrt=%d Ksps", state->frequency, state->srate);
  892. fcp = 3000;
  893. swp_ofs = state->srate / 4;
  894. for (i = 0; i < 60; i++)
  895. V[i] = -1;
  896. for (i = 0; i < 20; i++)
  897. prev_swp_freq[i] = 0;
  898. SIG1MIN = 25;
  899. for (n = 0; ((n < 3) && (ret == -1)); n++) {
  900. SEQ_set(state, 0);
  901. iq_vt_set(state, 0);
  902. CREN = 0;
  903. AFCEN = 0;
  904. AFCEXEN = 1;
  905. TIMINT1 = 0;
  906. TIMINT2 = 1;
  907. TIMEXT = 2;
  908. S1T = 0;
  909. S0T = 0;
  910. if (initial_set(state) < 0) {
  911. dprintk(verbose, MB86A16_ERROR, 1, "initial set failed");
  912. return -1;
  913. }
  914. if (DAGC_data_set(state, 3, 2) < 0) {
  915. dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
  916. return -1;
  917. }
  918. if (EN_set(state, CREN, AFCEN) < 0) {
  919. dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
  920. return -1; /* (0, 0) */
  921. }
  922. if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
  923. dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
  924. return -1; /* (1, smrt) = (1, symbolrate) */
  925. }
  926. if (CNTM_set(state, TIMINT1, TIMINT2, TIMEXT) < 0) {
  927. dprintk(verbose, MB86A16_ERROR, 1, "CNTM set error");
  928. return -1; /* (0, 1, 2) */
  929. }
  930. if (S01T_set(state, S1T, S0T) < 0) {
  931. dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
  932. return -1; /* (0, 0) */
  933. }
  934. smrt_info_get(state, state->srate);
  935. if (smrt_set(state, state->srate) < 0) {
  936. dprintk(verbose, MB86A16_ERROR, 1, "smrt info get error");
  937. return -1;
  938. }
  939. R = vco_dev_get(state, state->srate);
  940. if (R == 1)
  941. fOSC_start = state->frequency;
  942. else if (R == 0) {
  943. if (state->frequency % 2 == 0) {
  944. fOSC_start = state->frequency;
  945. } else {
  946. fOSC_start = state->frequency + 1;
  947. if (fOSC_start > 2150)
  948. fOSC_start = state->frequency - 1;
  949. }
  950. }
  951. loop = 1;
  952. ftemp = fOSC_start * 1000;
  953. vmax = 0 ;
  954. while (loop == 1) {
  955. ftemp = ftemp + swp_ofs;
  956. vmax++;
  957. /* Upper bound */
  958. if (ftemp > 2150000) {
  959. loop = 0;
  960. vmax--;
  961. } else {
  962. if ((ftemp == 2150000) ||
  963. (ftemp - state->frequency * 1000 >= fcp + state->srate / 4))
  964. loop = 0;
  965. }
  966. }
  967. loop = 1;
  968. ftemp = fOSC_start * 1000;
  969. vmin = 0 ;
  970. while (loop == 1) {
  971. ftemp = ftemp - swp_ofs;
  972. vmin--;
  973. /* Lower bound */
  974. if (ftemp < 950000) {
  975. loop = 0;
  976. vmin++;
  977. } else {
  978. if ((ftemp == 950000) ||
  979. (state->frequency * 1000 - ftemp >= fcp + state->srate / 4))
  980. loop = 0;
  981. }
  982. }
  983. wait_t = (8000 + state->srate / 2) / state->srate;
  984. if (wait_t == 0)
  985. wait_t = 1;
  986. i = 0;
  987. j = 0;
  988. prev_freq_num = 0;
  989. loop = 1;
  990. signal = 0;
  991. vmax_his = 0;
  992. vmin_his = 0;
  993. v = 0;
  994. while (loop == 1) {
  995. swp_info_get(state, fOSC_start, state->srate,
  996. v, R, swp_ofs, &fOSC,
  997. &afcex_freq, &AFCEX_L, &AFCEX_H);
  998. udelay(100);
  999. if (rf_val_set(state, fOSC, state->srate, R) < 0) {
  1000. dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
  1001. return -1;
  1002. }
  1003. udelay(100);
  1004. if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
  1005. dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
  1006. return -1;
  1007. }
  1008. if (srst(state) < 0) {
  1009. dprintk(verbose, MB86A16_ERROR, 1, "srst error");
  1010. return -1;
  1011. }
  1012. msleep_interruptible(wait_t);
  1013. if (mb86a16_read(state, 0x37, &SIG1) != 2) {
  1014. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1015. return -1;
  1016. }
  1017. V[30 + v] = SIG1 ;
  1018. swp_freq = swp_freq_calcuation(state, i, v, V, vmax, vmin,
  1019. SIG1MIN, fOSC, afcex_freq,
  1020. swp_ofs, &SIG1); /* changed */
  1021. signal_dupl = 0;
  1022. for (j = 0; j < prev_freq_num; j++) {
  1023. if ((abs(prev_swp_freq[j] - swp_freq)) < (swp_ofs * 3 / 2)) {
  1024. signal_dupl = 1;
  1025. dprintk(verbose, MB86A16_INFO, 1, "Probably Duplicate Signal, j = %d", j);
  1026. }
  1027. }
  1028. if ((signal_dupl == 0) && (swp_freq > 0) && (abs(swp_freq - state->frequency * 1000) < fcp + state->srate / 6)) {
  1029. dprintk(verbose, MB86A16_DEBUG, 1, "------ Signal detect ------ [swp_freq=[%07d, srate=%05d]]", swp_freq, state->srate);
  1030. prev_swp_freq[prev_freq_num] = swp_freq;
  1031. prev_freq_num++;
  1032. swp_info_get2(state, state->srate, R, swp_freq,
  1033. &afcex_freq, &fOSC,
  1034. &AFCEX_L, &AFCEX_H);
  1035. if (rf_val_set(state, fOSC, state->srate, R) < 0) {
  1036. dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
  1037. return -1;
  1038. }
  1039. if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
  1040. dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
  1041. return -1;
  1042. }
  1043. signal = signal_det(state, state->srate, &SIG1);
  1044. if (signal == 1) {
  1045. dprintk(verbose, MB86A16_ERROR, 1, "***** Signal Found *****");
  1046. loop = 0;
  1047. } else {
  1048. dprintk(verbose, MB86A16_ERROR, 1, "!!!!! No signal !!!!!, try again...");
  1049. smrt_info_get(state, state->srate);
  1050. if (smrt_set(state, state->srate) < 0) {
  1051. dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
  1052. return -1;
  1053. }
  1054. }
  1055. }
  1056. if (v > vmax)
  1057. vmax_his = 1 ;
  1058. if (v < vmin)
  1059. vmin_his = 1 ;
  1060. i++;
  1061. if ((i % 2 == 1) && (vmax_his == 1))
  1062. i++;
  1063. if ((i % 2 == 0) && (vmin_his == 1))
  1064. i++;
  1065. if (i % 2 == 1)
  1066. v = (i + 1) / 2;
  1067. else
  1068. v = -i / 2;
  1069. if ((vmax_his == 1) && (vmin_his == 1))
  1070. loop = 0 ;
  1071. }
  1072. if (signal == 1) {
  1073. dprintk(verbose, MB86A16_INFO, 1, " Start Freq Error Check");
  1074. S1T = 7 ;
  1075. S0T = 1 ;
  1076. CREN = 0 ;
  1077. AFCEN = 1 ;
  1078. AFCEXEN = 0 ;
  1079. if (S01T_set(state, S1T, S0T) < 0) {
  1080. dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
  1081. return -1;
  1082. }
  1083. smrt_info_get(state, state->srate);
  1084. if (smrt_set(state, state->srate) < 0) {
  1085. dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
  1086. return -1;
  1087. }
  1088. if (EN_set(state, CREN, AFCEN) < 0) {
  1089. dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
  1090. return -1;
  1091. }
  1092. if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
  1093. dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
  1094. return -1;
  1095. }
  1096. afcex_info_get(state, afcex_freq, &AFCEX_L, &AFCEX_H);
  1097. if (afcofs_data_set(state, AFCEX_L, AFCEX_H) < 0) {
  1098. dprintk(verbose, MB86A16_ERROR, 1, "AFCOFS data set error");
  1099. return -1;
  1100. }
  1101. if (srst(state) < 0) {
  1102. dprintk(verbose, MB86A16_ERROR, 1, "srst error");
  1103. return -1;
  1104. }
  1105. /* delay 4~200 */
  1106. wait_t = 200000 / state->master_clk + 200000 / state->srate;
  1107. msleep(wait_t);
  1108. afcerr = afcerr_chk(state);
  1109. if (afcerr == -1)
  1110. return -1;
  1111. swp_freq = fOSC * 1000 + afcerr ;
  1112. AFCEXEN = 1 ;
  1113. if (state->srate >= 1500)
  1114. smrt_d = state->srate / 3;
  1115. else
  1116. smrt_d = state->srate / 2;
  1117. smrt_info_get(state, smrt_d);
  1118. if (smrt_set(state, smrt_d) < 0) {
  1119. dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
  1120. return -1;
  1121. }
  1122. if (AFCEXEN_set(state, AFCEXEN, smrt_d) < 0) {
  1123. dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
  1124. return -1;
  1125. }
  1126. R = vco_dev_get(state, smrt_d);
  1127. if (DAGC_data_set(state, 2, 0) < 0) {
  1128. dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
  1129. return -1;
  1130. }
  1131. for (i = 0; i < 3; i++) {
  1132. temp_freq = swp_freq + (i - 1) * state->srate / 8;
  1133. swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
  1134. if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
  1135. dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
  1136. return -1;
  1137. }
  1138. if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
  1139. dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
  1140. return -1;
  1141. }
  1142. wait_t = 200000 / state->master_clk + 40000 / smrt_d;
  1143. msleep(wait_t);
  1144. dagcm[i] = dagcm_val_get(state);
  1145. }
  1146. if ((dagcm[0] > dagcm[1]) &&
  1147. (dagcm[0] > dagcm[2]) &&
  1148. (dagcm[0] - dagcm[1] > 2 * (dagcm[2] - dagcm[1]))) {
  1149. temp_freq = swp_freq - 2 * state->srate / 8;
  1150. swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
  1151. if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
  1152. dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
  1153. return -1;
  1154. }
  1155. if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
  1156. dprintk(verbose, MB86A16_ERROR, 1, "afcex data set");
  1157. return -1;
  1158. }
  1159. wait_t = 200000 / state->master_clk + 40000 / smrt_d;
  1160. msleep(wait_t);
  1161. dagcm[3] = dagcm_val_get(state);
  1162. if (dagcm[3] > dagcm[1])
  1163. delta_freq = (dagcm[2] - dagcm[0] + dagcm[1] - dagcm[3]) * state->srate / 300;
  1164. else
  1165. delta_freq = 0;
  1166. } else if ((dagcm[2] > dagcm[1]) &&
  1167. (dagcm[2] > dagcm[0]) &&
  1168. (dagcm[2] - dagcm[1] > 2 * (dagcm[0] - dagcm[1]))) {
  1169. temp_freq = swp_freq + 2 * state->srate / 8;
  1170. swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
  1171. if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
  1172. dprintk(verbose, MB86A16_ERROR, 1, "rf val set");
  1173. return -1;
  1174. }
  1175. if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
  1176. dprintk(verbose, MB86A16_ERROR, 1, "afcex data set");
  1177. return -1;
  1178. }
  1179. wait_t = 200000 / state->master_clk + 40000 / smrt_d;
  1180. msleep(wait_t);
  1181. dagcm[3] = dagcm_val_get(state);
  1182. if (dagcm[3] > dagcm[1])
  1183. delta_freq = (dagcm[2] - dagcm[0] + dagcm[3] - dagcm[1]) * state->srate / 300;
  1184. else
  1185. delta_freq = 0 ;
  1186. } else {
  1187. delta_freq = 0 ;
  1188. }
  1189. dprintk(verbose, MB86A16_INFO, 1, "SWEEP Frequency = %d", swp_freq);
  1190. swp_freq += delta_freq;
  1191. dprintk(verbose, MB86A16_INFO, 1, "Adjusting .., DELTA Freq = %d, SWEEP Freq=%d", delta_freq, swp_freq);
  1192. if (abs(state->frequency * 1000 - swp_freq) > 3800) {
  1193. dprintk(verbose, MB86A16_INFO, 1, "NO -- SIGNAL !");
  1194. } else {
  1195. S1T = 0;
  1196. S0T = 3;
  1197. CREN = 1;
  1198. AFCEN = 0;
  1199. AFCEXEN = 1;
  1200. if (S01T_set(state, S1T, S0T) < 0) {
  1201. dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
  1202. return -1;
  1203. }
  1204. if (DAGC_data_set(state, 0, 0) < 0) {
  1205. dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
  1206. return -1;
  1207. }
  1208. R = vco_dev_get(state, state->srate);
  1209. smrt_info_get(state, state->srate);
  1210. if (smrt_set(state, state->srate) < 0) {
  1211. dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
  1212. return -1;
  1213. }
  1214. if (EN_set(state, CREN, AFCEN) < 0) {
  1215. dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
  1216. return -1;
  1217. }
  1218. if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
  1219. dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
  1220. return -1;
  1221. }
  1222. swp_info_get2(state, state->srate, R, swp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
  1223. if (rf_val_set(state, fOSC, state->srate, R) < 0) {
  1224. dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
  1225. return -1;
  1226. }
  1227. if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
  1228. dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
  1229. return -1;
  1230. }
  1231. if (srst(state) < 0) {
  1232. dprintk(verbose, MB86A16_ERROR, 1, "srst error");
  1233. return -1;
  1234. }
  1235. wait_t = 7 + (10000 + state->srate / 2) / state->srate;
  1236. if (wait_t == 0)
  1237. wait_t = 1;
  1238. msleep_interruptible(wait_t);
  1239. if (mb86a16_read(state, 0x37, &SIG1) != 2) {
  1240. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1241. return -EREMOTEIO;
  1242. }
  1243. if (SIG1 > 110) {
  1244. S2T = 4; S4T = 1; S5T = 6; ETH = 4; VIA = 6;
  1245. wait_t = 7 + (917504 + state->srate / 2) / state->srate;
  1246. } else if (SIG1 > 105) {
  1247. S2T = 4; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
  1248. wait_t = 7 + (1048576 + state->srate / 2) / state->srate;
  1249. } else if (SIG1 > 85) {
  1250. S2T = 5; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
  1251. wait_t = 7 + (1310720 + state->srate / 2) / state->srate;
  1252. } else if (SIG1 > 65) {
  1253. S2T = 6; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
  1254. wait_t = 7 + (1572864 + state->srate / 2) / state->srate;
  1255. } else {
  1256. S2T = 7; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
  1257. wait_t = 7 + (2097152 + state->srate / 2) / state->srate;
  1258. }
  1259. wait_t *= 2; /* FOS */
  1260. S2T_set(state, S2T);
  1261. S45T_set(state, S4T, S5T);
  1262. Vi_set(state, ETH, VIA);
  1263. srst(state);
  1264. msleep_interruptible(wait_t);
  1265. sync = sync_chk(state, &VIRM);
  1266. dprintk(verbose, MB86A16_INFO, 1, "-------- Viterbi=[%d] SYNC=[%d] ---------", VIRM, sync);
  1267. if (VIRM) {
  1268. if (VIRM == 4) {
  1269. /* 5/6 */
  1270. if (SIG1 > 110)
  1271. wait_t = (786432 + state->srate / 2) / state->srate;
  1272. else
  1273. wait_t = (1572864 + state->srate / 2) / state->srate;
  1274. if (state->srate < 5000)
  1275. /* FIXME ! , should be a long wait ! */
  1276. msleep_interruptible(wait_t);
  1277. else
  1278. msleep_interruptible(wait_t);
  1279. if (sync_chk(state, &junk) == 0) {
  1280. iq_vt_set(state, 1);
  1281. FEC_srst(state);
  1282. }
  1283. }
  1284. /* 1/2, 2/3, 3/4, 7/8 */
  1285. if (SIG1 > 110)
  1286. wait_t = (786432 + state->srate / 2) / state->srate;
  1287. else
  1288. wait_t = (1572864 + state->srate / 2) / state->srate;
  1289. msleep_interruptible(wait_t);
  1290. SEQ_set(state, 1);
  1291. } else {
  1292. dprintk(verbose, MB86A16_INFO, 1, "NO -- SYNC");
  1293. SEQ_set(state, 1);
  1294. ret = -1;
  1295. }
  1296. }
  1297. } else {
  1298. dprintk(verbose, MB86A16_INFO, 1, "NO -- SIGNAL");
  1299. ret = -1;
  1300. }
  1301. sync = sync_chk(state, &junk);
  1302. if (sync) {
  1303. dprintk(verbose, MB86A16_INFO, 1, "******* SYNC *******");
  1304. freqerr_chk(state, state->frequency, state->srate, 1);
  1305. ret = 0;
  1306. break;
  1307. }
  1308. }
  1309. mb86a16_read(state, 0x15, &agcval);
  1310. mb86a16_read(state, 0x26, &cnmval);
  1311. dprintk(verbose, MB86A16_INFO, 1, "AGC = %02x CNM = %02x", agcval, cnmval);
  1312. return ret;
  1313. }
  1314. static int mb86a16_send_diseqc_msg(struct dvb_frontend *fe,
  1315. struct dvb_diseqc_master_cmd *cmd)
  1316. {
  1317. struct mb86a16_state *state = fe->demodulator_priv;
  1318. int i;
  1319. u8 regs;
  1320. if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0)
  1321. goto err;
  1322. if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0)
  1323. goto err;
  1324. if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0)
  1325. goto err;
  1326. regs = 0x18;
  1327. if (cmd->msg_len > 5 || cmd->msg_len < 4)
  1328. return -EINVAL;
  1329. for (i = 0; i < cmd->msg_len; i++) {
  1330. if (mb86a16_write(state, regs, cmd->msg[i]) < 0)
  1331. goto err;
  1332. regs++;
  1333. }
  1334. i += 0x90;
  1335. msleep_interruptible(10);
  1336. if (mb86a16_write(state, MB86A16_DCC1, i) < 0)
  1337. goto err;
  1338. if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
  1339. goto err;
  1340. return 0;
  1341. err:
  1342. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1343. return -EREMOTEIO;
  1344. }
  1345. static int mb86a16_send_diseqc_burst(struct dvb_frontend *fe,
  1346. enum fe_sec_mini_cmd burst)
  1347. {
  1348. struct mb86a16_state *state = fe->demodulator_priv;
  1349. switch (burst) {
  1350. case SEC_MINI_A:
  1351. if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
  1352. MB86A16_DCC1_TBEN |
  1353. MB86A16_DCC1_TBO) < 0)
  1354. goto err;
  1355. if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
  1356. goto err;
  1357. break;
  1358. case SEC_MINI_B:
  1359. if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
  1360. MB86A16_DCC1_TBEN) < 0)
  1361. goto err;
  1362. if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
  1363. goto err;
  1364. break;
  1365. }
  1366. return 0;
  1367. err:
  1368. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1369. return -EREMOTEIO;
  1370. }
  1371. static int mb86a16_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
  1372. {
  1373. struct mb86a16_state *state = fe->demodulator_priv;
  1374. switch (tone) {
  1375. case SEC_TONE_ON:
  1376. if (mb86a16_write(state, MB86A16_TONEOUT2, 0x00) < 0)
  1377. goto err;
  1378. if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
  1379. MB86A16_DCC1_CTOE) < 0)
  1380. goto err;
  1381. if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
  1382. goto err;
  1383. break;
  1384. case SEC_TONE_OFF:
  1385. if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0)
  1386. goto err;
  1387. if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0)
  1388. goto err;
  1389. if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0)
  1390. goto err;
  1391. break;
  1392. default:
  1393. return -EINVAL;
  1394. }
  1395. return 0;
  1396. err:
  1397. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1398. return -EREMOTEIO;
  1399. }
  1400. static enum dvbfe_search mb86a16_search(struct dvb_frontend *fe)
  1401. {
  1402. struct dtv_frontend_properties *p = &fe->dtv_property_cache;
  1403. struct mb86a16_state *state = fe->demodulator_priv;
  1404. state->frequency = p->frequency / 1000;
  1405. state->srate = p->symbol_rate / 1000;
  1406. if (!mb86a16_set_fe(state)) {
  1407. dprintk(verbose, MB86A16_ERROR, 1, "Successfully acquired LOCK");
  1408. return DVBFE_ALGO_SEARCH_SUCCESS;
  1409. }
  1410. dprintk(verbose, MB86A16_ERROR, 1, "Lock acquisition failed!");
  1411. return DVBFE_ALGO_SEARCH_FAILED;
  1412. }
  1413. static void mb86a16_release(struct dvb_frontend *fe)
  1414. {
  1415. struct mb86a16_state *state = fe->demodulator_priv;
  1416. kfree(state);
  1417. }
  1418. static int mb86a16_init(struct dvb_frontend *fe)
  1419. {
  1420. return 0;
  1421. }
  1422. static int mb86a16_sleep(struct dvb_frontend *fe)
  1423. {
  1424. return 0;
  1425. }
  1426. static int mb86a16_read_ber(struct dvb_frontend *fe, u32 *ber)
  1427. {
  1428. u8 ber_mon, ber_tab, ber_lsb, ber_mid, ber_msb, ber_tim, ber_rst;
  1429. u32 timer;
  1430. struct mb86a16_state *state = fe->demodulator_priv;
  1431. *ber = 0;
  1432. if (mb86a16_read(state, MB86A16_BERMON, &ber_mon) != 2)
  1433. goto err;
  1434. if (mb86a16_read(state, MB86A16_BERTAB, &ber_tab) != 2)
  1435. goto err;
  1436. if (mb86a16_read(state, MB86A16_BERLSB, &ber_lsb) != 2)
  1437. goto err;
  1438. if (mb86a16_read(state, MB86A16_BERMID, &ber_mid) != 2)
  1439. goto err;
  1440. if (mb86a16_read(state, MB86A16_BERMSB, &ber_msb) != 2)
  1441. goto err;
  1442. /* BER monitor invalid when BER_EN = 0 */
  1443. if (ber_mon & 0x04) {
  1444. /* coarse, fast calculation */
  1445. *ber = ber_tab & 0x1f;
  1446. dprintk(verbose, MB86A16_DEBUG, 1, "BER coarse=[0x%02x]", *ber);
  1447. if (ber_mon & 0x01) {
  1448. /*
  1449. * BER_SEL = 1, The monitored BER is the estimated
  1450. * value with a Reed-Solomon decoder error amount at
  1451. * the deinterleaver output.
  1452. * monitored BER is expressed as a 20 bit output in total
  1453. */
  1454. ber_rst = (ber_mon >> 3) & 0x03;
  1455. *ber = (((ber_msb << 8) | ber_mid) << 8) | ber_lsb;
  1456. if (ber_rst == 0)
  1457. timer = 12500000;
  1458. else if (ber_rst == 1)
  1459. timer = 25000000;
  1460. else if (ber_rst == 2)
  1461. timer = 50000000;
  1462. else /* ber_rst == 3 */
  1463. timer = 100000000;
  1464. *ber /= timer;
  1465. dprintk(verbose, MB86A16_DEBUG, 1, "BER fine=[0x%02x]", *ber);
  1466. } else {
  1467. /*
  1468. * BER_SEL = 0, The monitored BER is the estimated
  1469. * value with a Viterbi decoder error amount at the
  1470. * QPSK demodulator output.
  1471. * monitored BER is expressed as a 24 bit output in total
  1472. */
  1473. ber_tim = (ber_mon >> 1) & 0x01;
  1474. *ber = (((ber_msb << 8) | ber_mid) << 8) | ber_lsb;
  1475. if (ber_tim == 0)
  1476. timer = 16;
  1477. else /* ber_tim == 1 */
  1478. timer = 24;
  1479. *ber /= 2 ^ timer;
  1480. dprintk(verbose, MB86A16_DEBUG, 1, "BER fine=[0x%02x]", *ber);
  1481. }
  1482. }
  1483. return 0;
  1484. err:
  1485. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1486. return -EREMOTEIO;
  1487. }
  1488. static int mb86a16_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
  1489. {
  1490. u8 agcm = 0;
  1491. struct mb86a16_state *state = fe->demodulator_priv;
  1492. *strength = 0;
  1493. if (mb86a16_read(state, MB86A16_AGCM, &agcm) != 2) {
  1494. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1495. return -EREMOTEIO;
  1496. }
  1497. *strength = ((0xff - agcm) * 100) / 256;
  1498. dprintk(verbose, MB86A16_DEBUG, 1, "Signal strength=[%d %%]", (u8) *strength);
  1499. *strength = (0xffff - 0xff) + agcm;
  1500. return 0;
  1501. }
  1502. struct cnr {
  1503. u8 cn_reg;
  1504. u8 cn_val;
  1505. };
  1506. static const struct cnr cnr_tab[] = {
  1507. { 35, 2 },
  1508. { 40, 3 },
  1509. { 50, 4 },
  1510. { 60, 5 },
  1511. { 70, 6 },
  1512. { 80, 7 },
  1513. { 92, 8 },
  1514. { 103, 9 },
  1515. { 115, 10 },
  1516. { 138, 12 },
  1517. { 162, 15 },
  1518. { 180, 18 },
  1519. { 185, 19 },
  1520. { 189, 20 },
  1521. { 195, 22 },
  1522. { 199, 24 },
  1523. { 201, 25 },
  1524. { 202, 26 },
  1525. { 203, 27 },
  1526. { 205, 28 },
  1527. { 208, 30 }
  1528. };
  1529. static int mb86a16_read_snr(struct dvb_frontend *fe, u16 *snr)
  1530. {
  1531. struct mb86a16_state *state = fe->demodulator_priv;
  1532. int i = 0;
  1533. int low_tide = 2, high_tide = 30, q_level;
  1534. u8 cn;
  1535. *snr = 0;
  1536. if (mb86a16_read(state, 0x26, &cn) != 2) {
  1537. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1538. return -EREMOTEIO;
  1539. }
  1540. for (i = 0; i < ARRAY_SIZE(cnr_tab); i++) {
  1541. if (cn < cnr_tab[i].cn_reg) {
  1542. *snr = cnr_tab[i].cn_val;
  1543. break;
  1544. }
  1545. }
  1546. q_level = (*snr * 100) / (high_tide - low_tide);
  1547. dprintk(verbose, MB86A16_ERROR, 1, "SNR (Quality) = [%d dB], Level=%d %%", *snr, q_level);
  1548. *snr = (0xffff - 0xff) + *snr;
  1549. return 0;
  1550. }
  1551. static int mb86a16_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
  1552. {
  1553. u8 dist;
  1554. struct mb86a16_state *state = fe->demodulator_priv;
  1555. if (mb86a16_read(state, MB86A16_DISTMON, &dist) != 2) {
  1556. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1557. return -EREMOTEIO;
  1558. }
  1559. *ucblocks = dist;
  1560. return 0;
  1561. }
  1562. static enum dvbfe_algo mb86a16_frontend_algo(struct dvb_frontend *fe)
  1563. {
  1564. return DVBFE_ALGO_CUSTOM;
  1565. }
  1566. static const struct dvb_frontend_ops mb86a16_ops = {
  1567. .delsys = { SYS_DVBS },
  1568. .info = {
  1569. .name = "Fujitsu MB86A16 DVB-S",
  1570. .frequency_min_hz = 950 * MHz,
  1571. .frequency_max_hz = 2150 * MHz,
  1572. .frequency_stepsize_hz = 3 * MHz,
  1573. .symbol_rate_min = 1000000,
  1574. .symbol_rate_max = 45000000,
  1575. .symbol_rate_tolerance = 500,
  1576. .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
  1577. FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 |
  1578. FE_CAN_FEC_7_8 | FE_CAN_QPSK |
  1579. FE_CAN_FEC_AUTO
  1580. },
  1581. .release = mb86a16_release,
  1582. .get_frontend_algo = mb86a16_frontend_algo,
  1583. .search = mb86a16_search,
  1584. .init = mb86a16_init,
  1585. .sleep = mb86a16_sleep,
  1586. .read_status = mb86a16_read_status,
  1587. .read_ber = mb86a16_read_ber,
  1588. .read_signal_strength = mb86a16_read_signal_strength,
  1589. .read_snr = mb86a16_read_snr,
  1590. .read_ucblocks = mb86a16_read_ucblocks,
  1591. .diseqc_send_master_cmd = mb86a16_send_diseqc_msg,
  1592. .diseqc_send_burst = mb86a16_send_diseqc_burst,
  1593. .set_tone = mb86a16_set_tone,
  1594. };
  1595. struct dvb_frontend *mb86a16_attach(const struct mb86a16_config *config,
  1596. struct i2c_adapter *i2c_adap)
  1597. {
  1598. u8 dev_id = 0;
  1599. struct mb86a16_state *state = NULL;
  1600. state = kmalloc(sizeof(struct mb86a16_state), GFP_KERNEL);
  1601. if (state == NULL)
  1602. goto error;
  1603. state->config = config;
  1604. state->i2c_adap = i2c_adap;
  1605. mb86a16_read(state, 0x7f, &dev_id);
  1606. if (dev_id != 0xfe)
  1607. goto error;
  1608. memcpy(&state->frontend.ops, &mb86a16_ops, sizeof(struct dvb_frontend_ops));
  1609. state->frontend.demodulator_priv = state;
  1610. state->frontend.ops.set_voltage = state->config->set_voltage;
  1611. return &state->frontend;
  1612. error:
  1613. kfree(state);
  1614. return NULL;
  1615. }
  1616. EXPORT_SYMBOL(mb86a16_attach);
  1617. MODULE_LICENSE("GPL");
  1618. MODULE_AUTHOR("Manu Abraham");