lgdt3305.c 31 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Support for LG Electronics LGDT3304 and LGDT3305 - VSB/QAM
  4. *
  5. * Copyright (C) 2008, 2009, 2010 Michael Krufky <mkrufky@linuxtv.org>
  6. *
  7. * LGDT3304 support by Jarod Wilson <jarod@redhat.com>
  8. */
  9. #include <asm/div64.h>
  10. #include <linux/dvb/frontend.h>
  11. #include <linux/slab.h>
  12. #include <media/dvb_math.h>
  13. #include "lgdt3305.h"
  14. static int debug;
  15. module_param(debug, int, 0644);
  16. MODULE_PARM_DESC(debug, "set debug level (info=1, reg=2 (or-able))");
  17. #define DBG_INFO 1
  18. #define DBG_REG 2
  19. #define lg_printk(kern, fmt, arg...) \
  20. printk(kern "%s: " fmt, __func__, ##arg)
  21. #define lg_info(fmt, arg...) printk(KERN_INFO "lgdt3305: " fmt, ##arg)
  22. #define lg_warn(fmt, arg...) lg_printk(KERN_WARNING, fmt, ##arg)
  23. #define lg_err(fmt, arg...) lg_printk(KERN_ERR, fmt, ##arg)
  24. #define lg_dbg(fmt, arg...) if (debug & DBG_INFO) \
  25. lg_printk(KERN_DEBUG, fmt, ##arg)
  26. #define lg_reg(fmt, arg...) if (debug & DBG_REG) \
  27. lg_printk(KERN_DEBUG, fmt, ##arg)
  28. #define lg_fail(ret) \
  29. ({ \
  30. int __ret; \
  31. __ret = (ret < 0); \
  32. if (__ret) \
  33. lg_err("error %d on line %d\n", ret, __LINE__); \
  34. __ret; \
  35. })
  36. struct lgdt3305_state {
  37. struct i2c_adapter *i2c_adap;
  38. const struct lgdt3305_config *cfg;
  39. struct dvb_frontend frontend;
  40. enum fe_modulation current_modulation;
  41. u32 current_frequency;
  42. u32 snr;
  43. };
  44. /* ------------------------------------------------------------------------ */
  45. /* FIXME: verify & document the LGDT3304 registers */
  46. #define LGDT3305_GEN_CTRL_1 0x0000
  47. #define LGDT3305_GEN_CTRL_2 0x0001
  48. #define LGDT3305_GEN_CTRL_3 0x0002
  49. #define LGDT3305_GEN_STATUS 0x0003
  50. #define LGDT3305_GEN_CONTROL 0x0007
  51. #define LGDT3305_GEN_CTRL_4 0x000a
  52. #define LGDT3305_DGTL_AGC_REF_1 0x0012
  53. #define LGDT3305_DGTL_AGC_REF_2 0x0013
  54. #define LGDT3305_CR_CTR_FREQ_1 0x0106
  55. #define LGDT3305_CR_CTR_FREQ_2 0x0107
  56. #define LGDT3305_CR_CTR_FREQ_3 0x0108
  57. #define LGDT3305_CR_CTR_FREQ_4 0x0109
  58. #define LGDT3305_CR_MSE_1 0x011b
  59. #define LGDT3305_CR_MSE_2 0x011c
  60. #define LGDT3305_CR_LOCK_STATUS 0x011d
  61. #define LGDT3305_CR_CTRL_7 0x0126
  62. #define LGDT3305_AGC_POWER_REF_1 0x0300
  63. #define LGDT3305_AGC_POWER_REF_2 0x0301
  64. #define LGDT3305_AGC_DELAY_PT_1 0x0302
  65. #define LGDT3305_AGC_DELAY_PT_2 0x0303
  66. #define LGDT3305_RFAGC_LOOP_FLTR_BW_1 0x0306
  67. #define LGDT3305_RFAGC_LOOP_FLTR_BW_2 0x0307
  68. #define LGDT3305_IFBW_1 0x0308
  69. #define LGDT3305_IFBW_2 0x0309
  70. #define LGDT3305_AGC_CTRL_1 0x030c
  71. #define LGDT3305_AGC_CTRL_4 0x0314
  72. #define LGDT3305_EQ_MSE_1 0x0413
  73. #define LGDT3305_EQ_MSE_2 0x0414
  74. #define LGDT3305_EQ_MSE_3 0x0415
  75. #define LGDT3305_PT_MSE_1 0x0417
  76. #define LGDT3305_PT_MSE_2 0x0418
  77. #define LGDT3305_PT_MSE_3 0x0419
  78. #define LGDT3305_FEC_BLOCK_CTRL 0x0504
  79. #define LGDT3305_FEC_LOCK_STATUS 0x050a
  80. #define LGDT3305_FEC_PKT_ERR_1 0x050c
  81. #define LGDT3305_FEC_PKT_ERR_2 0x050d
  82. #define LGDT3305_TP_CTRL_1 0x050e
  83. #define LGDT3305_BERT_PERIOD 0x0801
  84. #define LGDT3305_BERT_ERROR_COUNT_1 0x080a
  85. #define LGDT3305_BERT_ERROR_COUNT_2 0x080b
  86. #define LGDT3305_BERT_ERROR_COUNT_3 0x080c
  87. #define LGDT3305_BERT_ERROR_COUNT_4 0x080d
  88. static int lgdt3305_write_reg(struct lgdt3305_state *state, u16 reg, u8 val)
  89. {
  90. int ret;
  91. u8 buf[] = { reg >> 8, reg & 0xff, val };
  92. struct i2c_msg msg = {
  93. .addr = state->cfg->i2c_addr, .flags = 0,
  94. .buf = buf, .len = 3,
  95. };
  96. lg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val);
  97. ret = i2c_transfer(state->i2c_adap, &msg, 1);
  98. if (ret != 1) {
  99. lg_err("error (addr %02x %02x <- %02x, err = %i)\n",
  100. msg.buf[0], msg.buf[1], msg.buf[2], ret);
  101. if (ret < 0)
  102. return ret;
  103. else
  104. return -EREMOTEIO;
  105. }
  106. return 0;
  107. }
  108. static int lgdt3305_read_reg(struct lgdt3305_state *state, u16 reg, u8 *val)
  109. {
  110. int ret;
  111. u8 reg_buf[] = { reg >> 8, reg & 0xff };
  112. struct i2c_msg msg[] = {
  113. { .addr = state->cfg->i2c_addr,
  114. .flags = 0, .buf = reg_buf, .len = 2 },
  115. { .addr = state->cfg->i2c_addr,
  116. .flags = I2C_M_RD, .buf = val, .len = 1 },
  117. };
  118. lg_reg("reg: 0x%04x\n", reg);
  119. ret = i2c_transfer(state->i2c_adap, msg, 2);
  120. if (ret != 2) {
  121. lg_err("error (addr %02x reg %04x error (ret == %i)\n",
  122. state->cfg->i2c_addr, reg, ret);
  123. if (ret < 0)
  124. return ret;
  125. else
  126. return -EREMOTEIO;
  127. }
  128. return 0;
  129. }
  130. #define read_reg(state, reg) \
  131. ({ \
  132. u8 __val; \
  133. int ret = lgdt3305_read_reg(state, reg, &__val); \
  134. if (lg_fail(ret)) \
  135. __val = 0; \
  136. __val; \
  137. })
  138. static int lgdt3305_set_reg_bit(struct lgdt3305_state *state,
  139. u16 reg, int bit, int onoff)
  140. {
  141. u8 val;
  142. int ret;
  143. lg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff);
  144. ret = lgdt3305_read_reg(state, reg, &val);
  145. if (lg_fail(ret))
  146. goto fail;
  147. val &= ~(1 << bit);
  148. val |= (onoff & 1) << bit;
  149. ret = lgdt3305_write_reg(state, reg, val);
  150. fail:
  151. return ret;
  152. }
  153. struct lgdt3305_reg {
  154. u16 reg;
  155. u8 val;
  156. };
  157. static int lgdt3305_write_regs(struct lgdt3305_state *state,
  158. struct lgdt3305_reg *regs, int len)
  159. {
  160. int i, ret;
  161. lg_reg("writing %d registers...\n", len);
  162. for (i = 0; i < len - 1; i++) {
  163. ret = lgdt3305_write_reg(state, regs[i].reg, regs[i].val);
  164. if (lg_fail(ret))
  165. return ret;
  166. }
  167. return 0;
  168. }
  169. /* ------------------------------------------------------------------------ */
  170. static int lgdt3305_soft_reset(struct lgdt3305_state *state)
  171. {
  172. int ret;
  173. lg_dbg("\n");
  174. ret = lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_3, 0, 0);
  175. if (lg_fail(ret))
  176. goto fail;
  177. msleep(20);
  178. ret = lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_3, 0, 1);
  179. fail:
  180. return ret;
  181. }
  182. static inline int lgdt3305_mpeg_mode(struct lgdt3305_state *state,
  183. enum lgdt3305_mpeg_mode mode)
  184. {
  185. lg_dbg("(%d)\n", mode);
  186. return lgdt3305_set_reg_bit(state, LGDT3305_TP_CTRL_1, 5, mode);
  187. }
  188. static int lgdt3305_mpeg_mode_polarity(struct lgdt3305_state *state)
  189. {
  190. u8 val;
  191. int ret;
  192. enum lgdt3305_tp_clock_edge edge = state->cfg->tpclk_edge;
  193. enum lgdt3305_tp_clock_mode mode = state->cfg->tpclk_mode;
  194. enum lgdt3305_tp_valid_polarity valid = state->cfg->tpvalid_polarity;
  195. lg_dbg("edge = %d, valid = %d\n", edge, valid);
  196. ret = lgdt3305_read_reg(state, LGDT3305_TP_CTRL_1, &val);
  197. if (lg_fail(ret))
  198. goto fail;
  199. val &= ~0x09;
  200. if (edge)
  201. val |= 0x08;
  202. if (mode)
  203. val |= 0x40;
  204. if (valid)
  205. val |= 0x01;
  206. ret = lgdt3305_write_reg(state, LGDT3305_TP_CTRL_1, val);
  207. if (lg_fail(ret))
  208. goto fail;
  209. ret = lgdt3305_soft_reset(state);
  210. fail:
  211. return ret;
  212. }
  213. static int lgdt3305_set_modulation(struct lgdt3305_state *state,
  214. struct dtv_frontend_properties *p)
  215. {
  216. u8 opermode;
  217. int ret;
  218. lg_dbg("\n");
  219. ret = lgdt3305_read_reg(state, LGDT3305_GEN_CTRL_1, &opermode);
  220. if (lg_fail(ret))
  221. goto fail;
  222. opermode &= ~0x03;
  223. switch (p->modulation) {
  224. case VSB_8:
  225. opermode |= 0x03;
  226. break;
  227. case QAM_64:
  228. opermode |= 0x00;
  229. break;
  230. case QAM_256:
  231. opermode |= 0x01;
  232. break;
  233. default:
  234. return -EINVAL;
  235. }
  236. ret = lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_1, opermode);
  237. fail:
  238. return ret;
  239. }
  240. static int lgdt3305_set_filter_extension(struct lgdt3305_state *state,
  241. struct dtv_frontend_properties *p)
  242. {
  243. int val;
  244. switch (p->modulation) {
  245. case VSB_8:
  246. val = 0;
  247. break;
  248. case QAM_64:
  249. case QAM_256:
  250. val = 1;
  251. break;
  252. default:
  253. return -EINVAL;
  254. }
  255. lg_dbg("val = %d\n", val);
  256. return lgdt3305_set_reg_bit(state, 0x043f, 2, val);
  257. }
  258. /* ------------------------------------------------------------------------ */
  259. static int lgdt3305_passband_digital_agc(struct lgdt3305_state *state,
  260. struct dtv_frontend_properties *p)
  261. {
  262. u16 agc_ref;
  263. switch (p->modulation) {
  264. case VSB_8:
  265. agc_ref = 0x32c4;
  266. break;
  267. case QAM_64:
  268. agc_ref = 0x2a00;
  269. break;
  270. case QAM_256:
  271. agc_ref = 0x2a80;
  272. break;
  273. default:
  274. return -EINVAL;
  275. }
  276. lg_dbg("agc ref: 0x%04x\n", agc_ref);
  277. lgdt3305_write_reg(state, LGDT3305_DGTL_AGC_REF_1, agc_ref >> 8);
  278. lgdt3305_write_reg(state, LGDT3305_DGTL_AGC_REF_2, agc_ref & 0xff);
  279. return 0;
  280. }
  281. static int lgdt3305_rfagc_loop(struct lgdt3305_state *state,
  282. struct dtv_frontend_properties *p)
  283. {
  284. u16 ifbw, rfbw, agcdelay;
  285. switch (p->modulation) {
  286. case VSB_8:
  287. agcdelay = 0x04c0;
  288. rfbw = 0x8000;
  289. ifbw = 0x8000;
  290. break;
  291. case QAM_64:
  292. case QAM_256:
  293. agcdelay = 0x046b;
  294. rfbw = 0x8889;
  295. /* FIXME: investigate optimal ifbw & rfbw values for the
  296. * DT3304 and re-write this switch..case block */
  297. if (state->cfg->demod_chip == LGDT3304)
  298. ifbw = 0x6666;
  299. else /* (state->cfg->demod_chip == LGDT3305) */
  300. ifbw = 0x8888;
  301. break;
  302. default:
  303. return -EINVAL;
  304. }
  305. if (state->cfg->rf_agc_loop) {
  306. lg_dbg("agcdelay: 0x%04x, rfbw: 0x%04x\n", agcdelay, rfbw);
  307. /* rf agc loop filter bandwidth */
  308. lgdt3305_write_reg(state, LGDT3305_AGC_DELAY_PT_1,
  309. agcdelay >> 8);
  310. lgdt3305_write_reg(state, LGDT3305_AGC_DELAY_PT_2,
  311. agcdelay & 0xff);
  312. lgdt3305_write_reg(state, LGDT3305_RFAGC_LOOP_FLTR_BW_1,
  313. rfbw >> 8);
  314. lgdt3305_write_reg(state, LGDT3305_RFAGC_LOOP_FLTR_BW_2,
  315. rfbw & 0xff);
  316. } else {
  317. lg_dbg("ifbw: 0x%04x\n", ifbw);
  318. /* if agc loop filter bandwidth */
  319. lgdt3305_write_reg(state, LGDT3305_IFBW_1, ifbw >> 8);
  320. lgdt3305_write_reg(state, LGDT3305_IFBW_2, ifbw & 0xff);
  321. }
  322. return 0;
  323. }
  324. static int lgdt3305_agc_setup(struct lgdt3305_state *state,
  325. struct dtv_frontend_properties *p)
  326. {
  327. int lockdten, acqen;
  328. switch (p->modulation) {
  329. case VSB_8:
  330. lockdten = 0;
  331. acqen = 0;
  332. break;
  333. case QAM_64:
  334. case QAM_256:
  335. lockdten = 1;
  336. acqen = 1;
  337. break;
  338. default:
  339. return -EINVAL;
  340. }
  341. lg_dbg("lockdten = %d, acqen = %d\n", lockdten, acqen);
  342. /* control agc function */
  343. switch (state->cfg->demod_chip) {
  344. case LGDT3304:
  345. lgdt3305_write_reg(state, 0x0314, 0xe1 | lockdten << 1);
  346. lgdt3305_set_reg_bit(state, 0x030e, 2, acqen);
  347. break;
  348. case LGDT3305:
  349. lgdt3305_write_reg(state, LGDT3305_AGC_CTRL_4, 0xe1 | lockdten << 1);
  350. lgdt3305_set_reg_bit(state, LGDT3305_AGC_CTRL_1, 2, acqen);
  351. break;
  352. default:
  353. return -EINVAL;
  354. }
  355. return lgdt3305_rfagc_loop(state, p);
  356. }
  357. static int lgdt3305_set_agc_power_ref(struct lgdt3305_state *state,
  358. struct dtv_frontend_properties *p)
  359. {
  360. u16 usref = 0;
  361. switch (p->modulation) {
  362. case VSB_8:
  363. if (state->cfg->usref_8vsb)
  364. usref = state->cfg->usref_8vsb;
  365. break;
  366. case QAM_64:
  367. if (state->cfg->usref_qam64)
  368. usref = state->cfg->usref_qam64;
  369. break;
  370. case QAM_256:
  371. if (state->cfg->usref_qam256)
  372. usref = state->cfg->usref_qam256;
  373. break;
  374. default:
  375. return -EINVAL;
  376. }
  377. if (usref) {
  378. lg_dbg("set manual mode: 0x%04x\n", usref);
  379. lgdt3305_set_reg_bit(state, LGDT3305_AGC_CTRL_1, 3, 1);
  380. lgdt3305_write_reg(state, LGDT3305_AGC_POWER_REF_1,
  381. 0xff & (usref >> 8));
  382. lgdt3305_write_reg(state, LGDT3305_AGC_POWER_REF_2,
  383. 0xff & (usref >> 0));
  384. }
  385. return 0;
  386. }
  387. /* ------------------------------------------------------------------------ */
  388. static int lgdt3305_spectral_inversion(struct lgdt3305_state *state,
  389. struct dtv_frontend_properties *p,
  390. int inversion)
  391. {
  392. int ret;
  393. lg_dbg("(%d)\n", inversion);
  394. switch (p->modulation) {
  395. case VSB_8:
  396. ret = lgdt3305_write_reg(state, LGDT3305_CR_CTRL_7,
  397. inversion ? 0xf9 : 0x79);
  398. break;
  399. case QAM_64:
  400. case QAM_256:
  401. ret = lgdt3305_write_reg(state, LGDT3305_FEC_BLOCK_CTRL,
  402. inversion ? 0xfd : 0xff);
  403. break;
  404. default:
  405. ret = -EINVAL;
  406. }
  407. return ret;
  408. }
  409. static int lgdt3305_set_if(struct lgdt3305_state *state,
  410. struct dtv_frontend_properties *p)
  411. {
  412. u16 if_freq_khz;
  413. u8 nco1, nco2, nco3, nco4;
  414. u64 nco;
  415. switch (p->modulation) {
  416. case VSB_8:
  417. if_freq_khz = state->cfg->vsb_if_khz;
  418. break;
  419. case QAM_64:
  420. case QAM_256:
  421. if_freq_khz = state->cfg->qam_if_khz;
  422. break;
  423. default:
  424. return -EINVAL;
  425. }
  426. nco = if_freq_khz / 10;
  427. switch (p->modulation) {
  428. case VSB_8:
  429. nco <<= 24;
  430. do_div(nco, 625);
  431. break;
  432. case QAM_64:
  433. case QAM_256:
  434. nco <<= 28;
  435. do_div(nco, 625);
  436. break;
  437. default:
  438. return -EINVAL;
  439. }
  440. nco1 = (nco >> 24) & 0x3f;
  441. nco1 |= 0x40;
  442. nco2 = (nco >> 16) & 0xff;
  443. nco3 = (nco >> 8) & 0xff;
  444. nco4 = nco & 0xff;
  445. lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_1, nco1);
  446. lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_2, nco2);
  447. lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_3, nco3);
  448. lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_4, nco4);
  449. lg_dbg("%d KHz -> [%02x%02x%02x%02x]\n",
  450. if_freq_khz, nco1, nco2, nco3, nco4);
  451. return 0;
  452. }
  453. /* ------------------------------------------------------------------------ */
  454. static int lgdt3305_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
  455. {
  456. struct lgdt3305_state *state = fe->demodulator_priv;
  457. if (state->cfg->deny_i2c_rptr)
  458. return 0;
  459. lg_dbg("(%d)\n", enable);
  460. return lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_2, 5,
  461. enable ? 0 : 1);
  462. }
  463. static int lgdt3305_sleep(struct dvb_frontend *fe)
  464. {
  465. struct lgdt3305_state *state = fe->demodulator_priv;
  466. u8 gen_ctrl_3, gen_ctrl_4;
  467. lg_dbg("\n");
  468. gen_ctrl_3 = read_reg(state, LGDT3305_GEN_CTRL_3);
  469. gen_ctrl_4 = read_reg(state, LGDT3305_GEN_CTRL_4);
  470. /* hold in software reset while sleeping */
  471. gen_ctrl_3 &= ~0x01;
  472. /* tristate the IF-AGC pin */
  473. gen_ctrl_3 |= 0x02;
  474. /* tristate the RF-AGC pin */
  475. gen_ctrl_3 |= 0x04;
  476. /* disable vsb/qam module */
  477. gen_ctrl_4 &= ~0x01;
  478. /* disable adc module */
  479. gen_ctrl_4 &= ~0x02;
  480. lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_3, gen_ctrl_3);
  481. lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_4, gen_ctrl_4);
  482. return 0;
  483. }
  484. static int lgdt3305_init(struct dvb_frontend *fe)
  485. {
  486. struct lgdt3305_state *state = fe->demodulator_priv;
  487. int ret;
  488. static struct lgdt3305_reg lgdt3304_init_data[] = {
  489. { .reg = LGDT3305_GEN_CTRL_1, .val = 0x03, },
  490. { .reg = 0x000d, .val = 0x02, },
  491. { .reg = 0x000e, .val = 0x02, },
  492. { .reg = LGDT3305_DGTL_AGC_REF_1, .val = 0x32, },
  493. { .reg = LGDT3305_DGTL_AGC_REF_2, .val = 0xc4, },
  494. { .reg = LGDT3305_CR_CTR_FREQ_1, .val = 0x00, },
  495. { .reg = LGDT3305_CR_CTR_FREQ_2, .val = 0x00, },
  496. { .reg = LGDT3305_CR_CTR_FREQ_3, .val = 0x00, },
  497. { .reg = LGDT3305_CR_CTR_FREQ_4, .val = 0x00, },
  498. { .reg = LGDT3305_CR_CTRL_7, .val = 0xf9, },
  499. { .reg = 0x0112, .val = 0x17, },
  500. { .reg = 0x0113, .val = 0x15, },
  501. { .reg = 0x0114, .val = 0x18, },
  502. { .reg = 0x0115, .val = 0xff, },
  503. { .reg = 0x0116, .val = 0x3c, },
  504. { .reg = 0x0214, .val = 0x67, },
  505. { .reg = 0x0424, .val = 0x8d, },
  506. { .reg = 0x0427, .val = 0x12, },
  507. { .reg = 0x0428, .val = 0x4f, },
  508. { .reg = LGDT3305_IFBW_1, .val = 0x80, },
  509. { .reg = LGDT3305_IFBW_2, .val = 0x00, },
  510. { .reg = 0x030a, .val = 0x08, },
  511. { .reg = 0x030b, .val = 0x9b, },
  512. { .reg = 0x030d, .val = 0x00, },
  513. { .reg = 0x030e, .val = 0x1c, },
  514. { .reg = 0x0314, .val = 0xe1, },
  515. { .reg = 0x000d, .val = 0x82, },
  516. { .reg = LGDT3305_TP_CTRL_1, .val = 0x5b, },
  517. { .reg = LGDT3305_TP_CTRL_1, .val = 0x5b, },
  518. };
  519. static struct lgdt3305_reg lgdt3305_init_data[] = {
  520. { .reg = LGDT3305_GEN_CTRL_1, .val = 0x03, },
  521. { .reg = LGDT3305_GEN_CTRL_2, .val = 0xb0, },
  522. { .reg = LGDT3305_GEN_CTRL_3, .val = 0x01, },
  523. { .reg = LGDT3305_GEN_CONTROL, .val = 0x6f, },
  524. { .reg = LGDT3305_GEN_CTRL_4, .val = 0x03, },
  525. { .reg = LGDT3305_DGTL_AGC_REF_1, .val = 0x32, },
  526. { .reg = LGDT3305_DGTL_AGC_REF_2, .val = 0xc4, },
  527. { .reg = LGDT3305_CR_CTR_FREQ_1, .val = 0x00, },
  528. { .reg = LGDT3305_CR_CTR_FREQ_2, .val = 0x00, },
  529. { .reg = LGDT3305_CR_CTR_FREQ_3, .val = 0x00, },
  530. { .reg = LGDT3305_CR_CTR_FREQ_4, .val = 0x00, },
  531. { .reg = LGDT3305_CR_CTRL_7, .val = 0x79, },
  532. { .reg = LGDT3305_AGC_POWER_REF_1, .val = 0x32, },
  533. { .reg = LGDT3305_AGC_POWER_REF_2, .val = 0xc4, },
  534. { .reg = LGDT3305_AGC_DELAY_PT_1, .val = 0x0d, },
  535. { .reg = LGDT3305_AGC_DELAY_PT_2, .val = 0x30, },
  536. { .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_1, .val = 0x80, },
  537. { .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_2, .val = 0x00, },
  538. { .reg = LGDT3305_IFBW_1, .val = 0x80, },
  539. { .reg = LGDT3305_IFBW_2, .val = 0x00, },
  540. { .reg = LGDT3305_AGC_CTRL_1, .val = 0x30, },
  541. { .reg = LGDT3305_AGC_CTRL_4, .val = 0x61, },
  542. { .reg = LGDT3305_FEC_BLOCK_CTRL, .val = 0xff, },
  543. { .reg = LGDT3305_TP_CTRL_1, .val = 0x1b, },
  544. };
  545. lg_dbg("\n");
  546. switch (state->cfg->demod_chip) {
  547. case LGDT3304:
  548. ret = lgdt3305_write_regs(state, lgdt3304_init_data,
  549. ARRAY_SIZE(lgdt3304_init_data));
  550. break;
  551. case LGDT3305:
  552. ret = lgdt3305_write_regs(state, lgdt3305_init_data,
  553. ARRAY_SIZE(lgdt3305_init_data));
  554. break;
  555. default:
  556. ret = -EINVAL;
  557. }
  558. if (lg_fail(ret))
  559. goto fail;
  560. ret = lgdt3305_soft_reset(state);
  561. fail:
  562. return ret;
  563. }
  564. static int lgdt3304_set_parameters(struct dvb_frontend *fe)
  565. {
  566. struct dtv_frontend_properties *p = &fe->dtv_property_cache;
  567. struct lgdt3305_state *state = fe->demodulator_priv;
  568. int ret;
  569. lg_dbg("(%d, %d)\n", p->frequency, p->modulation);
  570. if (fe->ops.tuner_ops.set_params) {
  571. ret = fe->ops.tuner_ops.set_params(fe);
  572. if (fe->ops.i2c_gate_ctrl)
  573. fe->ops.i2c_gate_ctrl(fe, 0);
  574. if (lg_fail(ret))
  575. goto fail;
  576. state->current_frequency = p->frequency;
  577. }
  578. ret = lgdt3305_set_modulation(state, p);
  579. if (lg_fail(ret))
  580. goto fail;
  581. ret = lgdt3305_passband_digital_agc(state, p);
  582. if (lg_fail(ret))
  583. goto fail;
  584. ret = lgdt3305_agc_setup(state, p);
  585. if (lg_fail(ret))
  586. goto fail;
  587. /* reg 0x030d is 3304-only... seen in vsb and qam usbsnoops... */
  588. switch (p->modulation) {
  589. case VSB_8:
  590. lgdt3305_write_reg(state, 0x030d, 0x00);
  591. lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_1, 0x4f);
  592. lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_2, 0x0c);
  593. lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_3, 0xac);
  594. lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_4, 0xba);
  595. break;
  596. case QAM_64:
  597. case QAM_256:
  598. lgdt3305_write_reg(state, 0x030d, 0x14);
  599. ret = lgdt3305_set_if(state, p);
  600. if (lg_fail(ret))
  601. goto fail;
  602. break;
  603. default:
  604. return -EINVAL;
  605. }
  606. ret = lgdt3305_spectral_inversion(state, p,
  607. state->cfg->spectral_inversion
  608. ? 1 : 0);
  609. if (lg_fail(ret))
  610. goto fail;
  611. state->current_modulation = p->modulation;
  612. ret = lgdt3305_mpeg_mode(state, state->cfg->mpeg_mode);
  613. if (lg_fail(ret))
  614. goto fail;
  615. /* lgdt3305_mpeg_mode_polarity calls lgdt3305_soft_reset */
  616. ret = lgdt3305_mpeg_mode_polarity(state);
  617. fail:
  618. return ret;
  619. }
  620. static int lgdt3305_set_parameters(struct dvb_frontend *fe)
  621. {
  622. struct dtv_frontend_properties *p = &fe->dtv_property_cache;
  623. struct lgdt3305_state *state = fe->demodulator_priv;
  624. int ret;
  625. lg_dbg("(%d, %d)\n", p->frequency, p->modulation);
  626. if (fe->ops.tuner_ops.set_params) {
  627. ret = fe->ops.tuner_ops.set_params(fe);
  628. if (fe->ops.i2c_gate_ctrl)
  629. fe->ops.i2c_gate_ctrl(fe, 0);
  630. if (lg_fail(ret))
  631. goto fail;
  632. state->current_frequency = p->frequency;
  633. }
  634. ret = lgdt3305_set_modulation(state, p);
  635. if (lg_fail(ret))
  636. goto fail;
  637. ret = lgdt3305_passband_digital_agc(state, p);
  638. if (lg_fail(ret))
  639. goto fail;
  640. ret = lgdt3305_set_agc_power_ref(state, p);
  641. if (lg_fail(ret))
  642. goto fail;
  643. ret = lgdt3305_agc_setup(state, p);
  644. if (lg_fail(ret))
  645. goto fail;
  646. /* low if */
  647. ret = lgdt3305_write_reg(state, LGDT3305_GEN_CONTROL, 0x2f);
  648. if (lg_fail(ret))
  649. goto fail;
  650. ret = lgdt3305_set_reg_bit(state, LGDT3305_CR_CTR_FREQ_1, 6, 1);
  651. if (lg_fail(ret))
  652. goto fail;
  653. ret = lgdt3305_set_if(state, p);
  654. if (lg_fail(ret))
  655. goto fail;
  656. ret = lgdt3305_spectral_inversion(state, p,
  657. state->cfg->spectral_inversion
  658. ? 1 : 0);
  659. if (lg_fail(ret))
  660. goto fail;
  661. ret = lgdt3305_set_filter_extension(state, p);
  662. if (lg_fail(ret))
  663. goto fail;
  664. state->current_modulation = p->modulation;
  665. ret = lgdt3305_mpeg_mode(state, state->cfg->mpeg_mode);
  666. if (lg_fail(ret))
  667. goto fail;
  668. /* lgdt3305_mpeg_mode_polarity calls lgdt3305_soft_reset */
  669. ret = lgdt3305_mpeg_mode_polarity(state);
  670. fail:
  671. return ret;
  672. }
  673. static int lgdt3305_get_frontend(struct dvb_frontend *fe,
  674. struct dtv_frontend_properties *p)
  675. {
  676. struct lgdt3305_state *state = fe->demodulator_priv;
  677. lg_dbg("\n");
  678. p->modulation = state->current_modulation;
  679. p->frequency = state->current_frequency;
  680. return 0;
  681. }
  682. /* ------------------------------------------------------------------------ */
  683. static int lgdt3305_read_cr_lock_status(struct lgdt3305_state *state,
  684. int *locked)
  685. {
  686. u8 val;
  687. int ret;
  688. char *cr_lock_state = "";
  689. *locked = 0;
  690. ret = lgdt3305_read_reg(state, LGDT3305_CR_LOCK_STATUS, &val);
  691. if (lg_fail(ret))
  692. goto fail;
  693. switch (state->current_modulation) {
  694. case QAM_256:
  695. case QAM_64:
  696. if (val & (1 << 1))
  697. *locked = 1;
  698. switch (val & 0x07) {
  699. case 0:
  700. cr_lock_state = "QAM UNLOCK";
  701. break;
  702. case 4:
  703. cr_lock_state = "QAM 1stLock";
  704. break;
  705. case 6:
  706. cr_lock_state = "QAM 2ndLock";
  707. break;
  708. case 7:
  709. cr_lock_state = "QAM FinalLock";
  710. break;
  711. default:
  712. cr_lock_state = "CLOCKQAM-INVALID!";
  713. break;
  714. }
  715. break;
  716. case VSB_8:
  717. if (val & (1 << 7)) {
  718. *locked = 1;
  719. cr_lock_state = "CLOCKVSB";
  720. }
  721. break;
  722. default:
  723. ret = -EINVAL;
  724. }
  725. lg_dbg("(%d) %s\n", *locked, cr_lock_state);
  726. fail:
  727. return ret;
  728. }
  729. static int lgdt3305_read_fec_lock_status(struct lgdt3305_state *state,
  730. int *locked)
  731. {
  732. u8 val;
  733. int ret, mpeg_lock, fec_lock, viterbi_lock;
  734. *locked = 0;
  735. switch (state->current_modulation) {
  736. case QAM_256:
  737. case QAM_64:
  738. ret = lgdt3305_read_reg(state,
  739. LGDT3305_FEC_LOCK_STATUS, &val);
  740. if (lg_fail(ret))
  741. goto fail;
  742. mpeg_lock = (val & (1 << 0)) ? 1 : 0;
  743. fec_lock = (val & (1 << 2)) ? 1 : 0;
  744. viterbi_lock = (val & (1 << 3)) ? 1 : 0;
  745. *locked = mpeg_lock && fec_lock && viterbi_lock;
  746. lg_dbg("(%d) %s%s%s\n", *locked,
  747. mpeg_lock ? "mpeg lock " : "",
  748. fec_lock ? "fec lock " : "",
  749. viterbi_lock ? "viterbi lock" : "");
  750. break;
  751. case VSB_8:
  752. default:
  753. ret = -EINVAL;
  754. }
  755. fail:
  756. return ret;
  757. }
  758. static int lgdt3305_read_status(struct dvb_frontend *fe, enum fe_status *status)
  759. {
  760. struct lgdt3305_state *state = fe->demodulator_priv;
  761. u8 val;
  762. int ret, signal, inlock, nofecerr, snrgood,
  763. cr_lock, fec_lock, sync_lock;
  764. *status = 0;
  765. ret = lgdt3305_read_reg(state, LGDT3305_GEN_STATUS, &val);
  766. if (lg_fail(ret))
  767. goto fail;
  768. signal = (val & (1 << 4)) ? 1 : 0;
  769. inlock = (val & (1 << 3)) ? 0 : 1;
  770. sync_lock = (val & (1 << 2)) ? 1 : 0;
  771. nofecerr = (val & (1 << 1)) ? 1 : 0;
  772. snrgood = (val & (1 << 0)) ? 1 : 0;
  773. lg_dbg("%s%s%s%s%s\n",
  774. signal ? "SIGNALEXIST " : "",
  775. inlock ? "INLOCK " : "",
  776. sync_lock ? "SYNCLOCK " : "",
  777. nofecerr ? "NOFECERR " : "",
  778. snrgood ? "SNRGOOD " : "");
  779. ret = lgdt3305_read_cr_lock_status(state, &cr_lock);
  780. if (lg_fail(ret))
  781. goto fail;
  782. if (signal)
  783. *status |= FE_HAS_SIGNAL;
  784. if (cr_lock)
  785. *status |= FE_HAS_CARRIER;
  786. if (nofecerr)
  787. *status |= FE_HAS_VITERBI;
  788. if (sync_lock)
  789. *status |= FE_HAS_SYNC;
  790. switch (state->current_modulation) {
  791. case QAM_256:
  792. case QAM_64:
  793. /* signal bit is unreliable on the DT3304 in QAM mode */
  794. if (((LGDT3304 == state->cfg->demod_chip)) && (cr_lock))
  795. *status |= FE_HAS_SIGNAL;
  796. ret = lgdt3305_read_fec_lock_status(state, &fec_lock);
  797. if (lg_fail(ret))
  798. goto fail;
  799. if (fec_lock)
  800. *status |= FE_HAS_LOCK;
  801. break;
  802. case VSB_8:
  803. if (inlock)
  804. *status |= FE_HAS_LOCK;
  805. break;
  806. default:
  807. ret = -EINVAL;
  808. }
  809. fail:
  810. return ret;
  811. }
  812. /* ------------------------------------------------------------------------ */
  813. /* borrowed from lgdt330x.c */
  814. static u32 calculate_snr(u32 mse, u32 c)
  815. {
  816. if (mse == 0) /* no signal */
  817. return 0;
  818. mse = intlog10(mse);
  819. if (mse > c) {
  820. /* Negative SNR, which is possible, but realisticly the
  821. demod will lose lock before the signal gets this bad. The
  822. API only allows for unsigned values, so just return 0 */
  823. return 0;
  824. }
  825. return 10*(c - mse);
  826. }
  827. static int lgdt3305_read_snr(struct dvb_frontend *fe, u16 *snr)
  828. {
  829. struct lgdt3305_state *state = fe->demodulator_priv;
  830. u32 noise; /* noise value */
  831. u32 c; /* per-modulation SNR calculation constant */
  832. switch (state->current_modulation) {
  833. case VSB_8:
  834. #ifdef USE_PTMSE
  835. /* Use Phase Tracker Mean-Square Error Register */
  836. /* SNR for ranges from -13.11 to +44.08 */
  837. noise = ((read_reg(state, LGDT3305_PT_MSE_1) & 0x07) << 16) |
  838. (read_reg(state, LGDT3305_PT_MSE_2) << 8) |
  839. (read_reg(state, LGDT3305_PT_MSE_3) & 0xff);
  840. c = 73957994; /* log10(25*32^2)*2^24 */
  841. #else
  842. /* Use Equalizer Mean-Square Error Register */
  843. /* SNR for ranges from -16.12 to +44.08 */
  844. noise = ((read_reg(state, LGDT3305_EQ_MSE_1) & 0x0f) << 16) |
  845. (read_reg(state, LGDT3305_EQ_MSE_2) << 8) |
  846. (read_reg(state, LGDT3305_EQ_MSE_3) & 0xff);
  847. c = 73957994; /* log10(25*32^2)*2^24 */
  848. #endif
  849. break;
  850. case QAM_64:
  851. case QAM_256:
  852. noise = (read_reg(state, LGDT3305_CR_MSE_1) << 8) |
  853. (read_reg(state, LGDT3305_CR_MSE_2) & 0xff);
  854. c = (state->current_modulation == QAM_64) ?
  855. 97939837 : 98026066;
  856. /* log10(688128)*2^24 and log10(696320)*2^24 */
  857. break;
  858. default:
  859. return -EINVAL;
  860. }
  861. state->snr = calculate_snr(noise, c);
  862. /* report SNR in dB * 10 */
  863. *snr = (state->snr / ((1 << 24) / 10));
  864. lg_dbg("noise = 0x%08x, snr = %d.%02d dB\n", noise,
  865. state->snr >> 24, (((state->snr >> 8) & 0xffff) * 100) >> 16);
  866. return 0;
  867. }
  868. static int lgdt3305_read_signal_strength(struct dvb_frontend *fe,
  869. u16 *strength)
  870. {
  871. /* borrowed from lgdt330x.c
  872. *
  873. * Calculate strength from SNR up to 35dB
  874. * Even though the SNR can go higher than 35dB,
  875. * there is some comfort factor in having a range of
  876. * strong signals that can show at 100%
  877. */
  878. struct lgdt3305_state *state = fe->demodulator_priv;
  879. u16 snr;
  880. int ret;
  881. *strength = 0;
  882. ret = fe->ops.read_snr(fe, &snr);
  883. if (lg_fail(ret))
  884. goto fail;
  885. /* Rather than use the 8.8 value snr, use state->snr which is 8.24 */
  886. /* scale the range 0 - 35*2^24 into 0 - 65535 */
  887. if (state->snr >= 8960 * 0x10000)
  888. *strength = 0xffff;
  889. else
  890. *strength = state->snr / 8960;
  891. fail:
  892. return ret;
  893. }
  894. /* ------------------------------------------------------------------------ */
  895. static int lgdt3305_read_ber(struct dvb_frontend *fe, u32 *ber)
  896. {
  897. *ber = 0;
  898. return 0;
  899. }
  900. static int lgdt3305_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
  901. {
  902. struct lgdt3305_state *state = fe->demodulator_priv;
  903. *ucblocks =
  904. (read_reg(state, LGDT3305_FEC_PKT_ERR_1) << 8) |
  905. (read_reg(state, LGDT3305_FEC_PKT_ERR_2) & 0xff);
  906. return 0;
  907. }
  908. static int lgdt3305_get_tune_settings(struct dvb_frontend *fe,
  909. struct dvb_frontend_tune_settings
  910. *fe_tune_settings)
  911. {
  912. fe_tune_settings->min_delay_ms = 500;
  913. lg_dbg("\n");
  914. return 0;
  915. }
  916. static void lgdt3305_release(struct dvb_frontend *fe)
  917. {
  918. struct lgdt3305_state *state = fe->demodulator_priv;
  919. lg_dbg("\n");
  920. kfree(state);
  921. }
  922. static const struct dvb_frontend_ops lgdt3304_ops;
  923. static const struct dvb_frontend_ops lgdt3305_ops;
  924. struct dvb_frontend *lgdt3305_attach(const struct lgdt3305_config *config,
  925. struct i2c_adapter *i2c_adap)
  926. {
  927. struct lgdt3305_state *state = NULL;
  928. int ret;
  929. u8 val;
  930. lg_dbg("(%d-%04x)\n",
  931. i2c_adap ? i2c_adapter_id(i2c_adap) : 0,
  932. config ? config->i2c_addr : 0);
  933. state = kzalloc(sizeof(struct lgdt3305_state), GFP_KERNEL);
  934. if (state == NULL)
  935. goto fail;
  936. state->cfg = config;
  937. state->i2c_adap = i2c_adap;
  938. switch (config->demod_chip) {
  939. case LGDT3304:
  940. memcpy(&state->frontend.ops, &lgdt3304_ops,
  941. sizeof(struct dvb_frontend_ops));
  942. break;
  943. case LGDT3305:
  944. memcpy(&state->frontend.ops, &lgdt3305_ops,
  945. sizeof(struct dvb_frontend_ops));
  946. break;
  947. default:
  948. goto fail;
  949. }
  950. state->frontend.demodulator_priv = state;
  951. /* verify that we're talking to a lg dt3304/5 */
  952. ret = lgdt3305_read_reg(state, LGDT3305_GEN_CTRL_2, &val);
  953. if ((lg_fail(ret)) | (val == 0))
  954. goto fail;
  955. ret = lgdt3305_write_reg(state, 0x0808, 0x80);
  956. if (lg_fail(ret))
  957. goto fail;
  958. ret = lgdt3305_read_reg(state, 0x0808, &val);
  959. if ((lg_fail(ret)) | (val != 0x80))
  960. goto fail;
  961. ret = lgdt3305_write_reg(state, 0x0808, 0x00);
  962. if (lg_fail(ret))
  963. goto fail;
  964. state->current_frequency = -1;
  965. state->current_modulation = -1;
  966. return &state->frontend;
  967. fail:
  968. lg_warn("unable to detect %s hardware\n",
  969. config->demod_chip ? "LGDT3304" : "LGDT3305");
  970. kfree(state);
  971. return NULL;
  972. }
  973. EXPORT_SYMBOL(lgdt3305_attach);
  974. static const struct dvb_frontend_ops lgdt3304_ops = {
  975. .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
  976. .info = {
  977. .name = "LG Electronics LGDT3304 VSB/QAM Frontend",
  978. .frequency_min_hz = 54 * MHz,
  979. .frequency_max_hz = 858 * MHz,
  980. .frequency_stepsize_hz = 62500,
  981. .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
  982. },
  983. .i2c_gate_ctrl = lgdt3305_i2c_gate_ctrl,
  984. .init = lgdt3305_init,
  985. .sleep = lgdt3305_sleep,
  986. .set_frontend = lgdt3304_set_parameters,
  987. .get_frontend = lgdt3305_get_frontend,
  988. .get_tune_settings = lgdt3305_get_tune_settings,
  989. .read_status = lgdt3305_read_status,
  990. .read_ber = lgdt3305_read_ber,
  991. .read_signal_strength = lgdt3305_read_signal_strength,
  992. .read_snr = lgdt3305_read_snr,
  993. .read_ucblocks = lgdt3305_read_ucblocks,
  994. .release = lgdt3305_release,
  995. };
  996. static const struct dvb_frontend_ops lgdt3305_ops = {
  997. .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
  998. .info = {
  999. .name = "LG Electronics LGDT3305 VSB/QAM Frontend",
  1000. .frequency_min_hz = 54 * MHz,
  1001. .frequency_max_hz = 858 * MHz,
  1002. .frequency_stepsize_hz = 62500,
  1003. .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
  1004. },
  1005. .i2c_gate_ctrl = lgdt3305_i2c_gate_ctrl,
  1006. .init = lgdt3305_init,
  1007. .sleep = lgdt3305_sleep,
  1008. .set_frontend = lgdt3305_set_parameters,
  1009. .get_frontend = lgdt3305_get_frontend,
  1010. .get_tune_settings = lgdt3305_get_tune_settings,
  1011. .read_status = lgdt3305_read_status,
  1012. .read_ber = lgdt3305_read_ber,
  1013. .read_signal_strength = lgdt3305_read_signal_strength,
  1014. .read_snr = lgdt3305_read_snr,
  1015. .read_ucblocks = lgdt3305_read_ucblocks,
  1016. .release = lgdt3305_release,
  1017. };
  1018. MODULE_DESCRIPTION("LG Electronics LGDT3304/5 ATSC/QAM-B Demodulator Driver");
  1019. MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>");
  1020. MODULE_LICENSE("GPL");
  1021. MODULE_VERSION("0.2");