itd1000.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Driver for the Integrant ITD1000 "Zero-IF Tuner IC for Direct Broadcast Satellite"
  4. *
  5. * Copyright (c) 2007-8 Patrick Boettcher <pb@linuxtv.org>
  6. */
  7. #include <linux/module.h>
  8. #include <linux/moduleparam.h>
  9. #include <linux/delay.h>
  10. #include <linux/dvb/frontend.h>
  11. #include <linux/i2c.h>
  12. #include <linux/slab.h>
  13. #include <media/dvb_frontend.h>
  14. #include "itd1000.h"
  15. #include "itd1000_priv.h"
  16. /* Max transfer size done by I2C transfer functions */
  17. #define MAX_XFER_SIZE 64
  18. static int debug;
  19. module_param(debug, int, 0644);
  20. MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
  21. #define itd_dbg(args...) do { \
  22. if (debug) { \
  23. printk(KERN_DEBUG "ITD1000: " args);\
  24. } \
  25. } while (0)
  26. #define itd_warn(args...) do { \
  27. printk(KERN_WARNING "ITD1000: " args); \
  28. } while (0)
  29. #define itd_info(args...) do { \
  30. printk(KERN_INFO "ITD1000: " args); \
  31. } while (0)
  32. /* don't write more than one byte with flexcop behind */
  33. static int itd1000_write_regs(struct itd1000_state *state, u8 reg, u8 v[], u8 len)
  34. {
  35. u8 buf[MAX_XFER_SIZE];
  36. struct i2c_msg msg = {
  37. .addr = state->cfg->i2c_address, .flags = 0, .buf = buf, .len = len+1
  38. };
  39. if (1 + len > sizeof(buf)) {
  40. printk(KERN_WARNING
  41. "itd1000: i2c wr reg=%04x: len=%d is too big!\n",
  42. reg, len);
  43. return -EINVAL;
  44. }
  45. buf[0] = reg;
  46. memcpy(&buf[1], v, len);
  47. /* itd_dbg("wr %02x: %02x\n", reg, v[0]); */
  48. if (i2c_transfer(state->i2c, &msg, 1) != 1) {
  49. printk(KERN_WARNING "itd1000 I2C write failed\n");
  50. return -EREMOTEIO;
  51. }
  52. return 0;
  53. }
  54. static int itd1000_read_reg(struct itd1000_state *state, u8 reg)
  55. {
  56. u8 val;
  57. struct i2c_msg msg[2] = {
  58. { .addr = state->cfg->i2c_address, .flags = 0, .buf = &reg, .len = 1 },
  59. { .addr = state->cfg->i2c_address, .flags = I2C_M_RD, .buf = &val, .len = 1 },
  60. };
  61. /* ugly flexcop workaround */
  62. itd1000_write_regs(state, (reg - 1) & 0xff, &state->shadow[(reg - 1) & 0xff], 1);
  63. if (i2c_transfer(state->i2c, msg, 2) != 2) {
  64. itd_warn("itd1000 I2C read failed\n");
  65. return -EREMOTEIO;
  66. }
  67. return val;
  68. }
  69. static inline int itd1000_write_reg(struct itd1000_state *state, u8 r, u8 v)
  70. {
  71. u8 tmp = v; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
  72. int ret = itd1000_write_regs(state, r, &tmp, 1);
  73. state->shadow[r] = tmp;
  74. return ret;
  75. }
  76. static struct {
  77. u32 symbol_rate;
  78. u8 pgaext : 4; /* PLLFH */
  79. u8 bbgvmin : 4; /* BBGVMIN */
  80. } itd1000_lpf_pga[] = {
  81. { 0, 0x8, 0x3 },
  82. { 5200000, 0x8, 0x3 },
  83. { 12200000, 0x4, 0x3 },
  84. { 15400000, 0x2, 0x3 },
  85. { 19800000, 0x2, 0x3 },
  86. { 21500000, 0x2, 0x3 },
  87. { 24500000, 0x2, 0x3 },
  88. { 28400000, 0x2, 0x3 },
  89. { 33400000, 0x2, 0x3 },
  90. { 34400000, 0x1, 0x4 },
  91. { 34400000, 0x1, 0x4 },
  92. { 38400000, 0x1, 0x4 },
  93. { 38400000, 0x1, 0x4 },
  94. { 40400000, 0x1, 0x4 },
  95. { 45400000, 0x1, 0x4 },
  96. };
  97. static void itd1000_set_lpf_bw(struct itd1000_state *state, u32 symbol_rate)
  98. {
  99. u8 i;
  100. u8 con1 = itd1000_read_reg(state, CON1) & 0xfd;
  101. u8 pllfh = itd1000_read_reg(state, PLLFH) & 0x0f;
  102. u8 bbgvmin = itd1000_read_reg(state, BBGVMIN) & 0xf0;
  103. u8 bw = itd1000_read_reg(state, BW) & 0xf0;
  104. itd_dbg("symbol_rate = %d\n", symbol_rate);
  105. /* not sure what is that ? - starting to download the table */
  106. itd1000_write_reg(state, CON1, con1 | (1 << 1));
  107. for (i = 0; i < ARRAY_SIZE(itd1000_lpf_pga); i++)
  108. if (symbol_rate < itd1000_lpf_pga[i].symbol_rate) {
  109. itd_dbg("symrate: index: %d pgaext: %x, bbgvmin: %x\n", i, itd1000_lpf_pga[i].pgaext, itd1000_lpf_pga[i].bbgvmin);
  110. itd1000_write_reg(state, PLLFH, pllfh | (itd1000_lpf_pga[i].pgaext << 4));
  111. itd1000_write_reg(state, BBGVMIN, bbgvmin | (itd1000_lpf_pga[i].bbgvmin));
  112. itd1000_write_reg(state, BW, bw | (i & 0x0f));
  113. break;
  114. }
  115. itd1000_write_reg(state, CON1, con1 | (0 << 1));
  116. }
  117. static struct {
  118. u8 vcorg;
  119. u32 fmax_rg;
  120. } itd1000_vcorg[] = {
  121. { 1, 920000 },
  122. { 2, 971000 },
  123. { 3, 1031000 },
  124. { 4, 1091000 },
  125. { 5, 1171000 },
  126. { 6, 1281000 },
  127. { 7, 1381000 },
  128. { 8, 500000 }, /* this is intentional. */
  129. { 9, 1451000 },
  130. { 10, 1531000 },
  131. { 11, 1631000 },
  132. { 12, 1741000 },
  133. { 13, 1891000 },
  134. { 14, 2071000 },
  135. { 15, 2250000 },
  136. };
  137. static void itd1000_set_vco(struct itd1000_state *state, u32 freq_khz)
  138. {
  139. u8 i;
  140. u8 gvbb_i2c = itd1000_read_reg(state, GVBB_I2C) & 0xbf;
  141. u8 vco_chp1_i2c = itd1000_read_reg(state, VCO_CHP1_I2C) & 0x0f;
  142. u8 adcout;
  143. /* reserved bit again (reset ?) */
  144. itd1000_write_reg(state, GVBB_I2C, gvbb_i2c | (1 << 6));
  145. for (i = 0; i < ARRAY_SIZE(itd1000_vcorg); i++) {
  146. if (freq_khz < itd1000_vcorg[i].fmax_rg) {
  147. itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | (itd1000_vcorg[i].vcorg << 4));
  148. msleep(1);
  149. adcout = itd1000_read_reg(state, PLLLOCK) & 0x0f;
  150. itd_dbg("VCO: %dkHz: %d -> ADCOUT: %d %02x\n", freq_khz, itd1000_vcorg[i].vcorg, adcout, vco_chp1_i2c);
  151. if (adcout > 13) {
  152. if (!(itd1000_vcorg[i].vcorg == 7 || itd1000_vcorg[i].vcorg == 15))
  153. itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | ((itd1000_vcorg[i].vcorg + 1) << 4));
  154. } else if (adcout < 2) {
  155. if (!(itd1000_vcorg[i].vcorg == 1 || itd1000_vcorg[i].vcorg == 9))
  156. itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | ((itd1000_vcorg[i].vcorg - 1) << 4));
  157. }
  158. break;
  159. }
  160. }
  161. }
  162. static const struct {
  163. u32 freq;
  164. u8 values[10]; /* RFTR, RFST1 - RFST9 */
  165. } itd1000_fre_values[] = {
  166. { 1075000, { 0x59, 0x1d, 0x1c, 0x17, 0x16, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
  167. { 1250000, { 0x89, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
  168. { 1450000, { 0x89, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
  169. { 1650000, { 0x69, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
  170. { 1750000, { 0x69, 0x1e, 0x17, 0x15, 0x14, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
  171. { 1850000, { 0x69, 0x1d, 0x17, 0x16, 0x14, 0x0f, 0x0e, 0x0d, 0x0b, 0x0a } },
  172. { 1900000, { 0x69, 0x1d, 0x17, 0x15, 0x14, 0x0f, 0x0e, 0x0d, 0x0b, 0x0a } },
  173. { 1950000, { 0x69, 0x1d, 0x17, 0x16, 0x14, 0x13, 0x0e, 0x0d, 0x0b, 0x0a } },
  174. { 2050000, { 0x69, 0x1e, 0x1d, 0x17, 0x16, 0x14, 0x13, 0x0e, 0x0b, 0x0a } },
  175. { 2150000, { 0x69, 0x1d, 0x1c, 0x17, 0x15, 0x14, 0x13, 0x0f, 0x0e, 0x0b } }
  176. };
  177. #define FREF 16
  178. static void itd1000_set_lo(struct itd1000_state *state, u32 freq_khz)
  179. {
  180. int i, j;
  181. u32 plln, pllf;
  182. u64 tmp;
  183. plln = (freq_khz * 1000) / 2 / FREF;
  184. /* Compute the factional part times 1000 */
  185. tmp = plln % 1000000;
  186. plln /= 1000000;
  187. tmp *= 1048576;
  188. do_div(tmp, 1000000);
  189. pllf = (u32) tmp;
  190. state->frequency = ((plln * 1000) + (pllf * 1000)/1048576) * 2*FREF;
  191. itd_dbg("frequency: %dkHz (wanted) %dkHz (set), PLLF = %d, PLLN = %d\n", freq_khz, state->frequency, pllf, plln);
  192. itd1000_write_reg(state, PLLNH, 0x80); /* PLLNH */
  193. itd1000_write_reg(state, PLLNL, plln & 0xff);
  194. itd1000_write_reg(state, PLLFH, (itd1000_read_reg(state, PLLFH) & 0xf0) | ((pllf >> 16) & 0x0f));
  195. itd1000_write_reg(state, PLLFM, (pllf >> 8) & 0xff);
  196. itd1000_write_reg(state, PLLFL, (pllf >> 0) & 0xff);
  197. for (i = 0; i < ARRAY_SIZE(itd1000_fre_values); i++) {
  198. if (freq_khz <= itd1000_fre_values[i].freq) {
  199. itd_dbg("fre_values: %d\n", i);
  200. itd1000_write_reg(state, RFTR, itd1000_fre_values[i].values[0]);
  201. for (j = 0; j < 9; j++)
  202. itd1000_write_reg(state, RFST1+j, itd1000_fre_values[i].values[j+1]);
  203. break;
  204. }
  205. }
  206. itd1000_set_vco(state, freq_khz);
  207. }
  208. static int itd1000_set_parameters(struct dvb_frontend *fe)
  209. {
  210. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  211. struct itd1000_state *state = fe->tuner_priv;
  212. u8 pllcon1;
  213. itd1000_set_lo(state, c->frequency);
  214. itd1000_set_lpf_bw(state, c->symbol_rate);
  215. pllcon1 = itd1000_read_reg(state, PLLCON1) & 0x7f;
  216. itd1000_write_reg(state, PLLCON1, pllcon1 | (1 << 7));
  217. itd1000_write_reg(state, PLLCON1, pllcon1);
  218. return 0;
  219. }
  220. static int itd1000_get_frequency(struct dvb_frontend *fe, u32 *frequency)
  221. {
  222. struct itd1000_state *state = fe->tuner_priv;
  223. *frequency = state->frequency;
  224. return 0;
  225. }
  226. static int itd1000_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
  227. {
  228. return 0;
  229. }
  230. static u8 itd1000_init_tab[][2] = {
  231. { PLLCON1, 0x65 }, /* Register does not change */
  232. { PLLNH, 0x80 }, /* Bits [7:6] do not change */
  233. { RESERVED_0X6D, 0x3b },
  234. { VCO_CHP2_I2C, 0x12 },
  235. { 0x72, 0xf9 }, /* No such regsister defined */
  236. { RESERVED_0X73, 0xff },
  237. { RESERVED_0X74, 0xb2 },
  238. { RESERVED_0X75, 0xc7 },
  239. { EXTGVBBRF, 0xf0 },
  240. { DIVAGCCK, 0x80 },
  241. { BBTR, 0xa0 },
  242. { RESERVED_0X7E, 0x4f },
  243. { 0x82, 0x88 }, /* No such regsister defined */
  244. { 0x83, 0x80 }, /* No such regsister defined */
  245. { 0x84, 0x80 }, /* No such regsister defined */
  246. { RESERVED_0X85, 0x74 },
  247. { RESERVED_0X86, 0xff },
  248. { RESERVED_0X88, 0x02 },
  249. { RESERVED_0X89, 0x16 },
  250. { RFST0, 0x1f },
  251. { RESERVED_0X94, 0x66 },
  252. { RESERVED_0X95, 0x66 },
  253. { RESERVED_0X96, 0x77 },
  254. { RESERVED_0X97, 0x99 },
  255. { RESERVED_0X98, 0xff },
  256. { RESERVED_0X99, 0xfc },
  257. { RESERVED_0X9A, 0xba },
  258. { RESERVED_0X9B, 0xaa },
  259. };
  260. static u8 itd1000_reinit_tab[][2] = {
  261. { VCO_CHP1_I2C, 0x8a },
  262. { BW, 0x87 },
  263. { GVBB_I2C, 0x03 },
  264. { BBGVMIN, 0x03 },
  265. { CON1, 0x2e },
  266. };
  267. static int itd1000_init(struct dvb_frontend *fe)
  268. {
  269. struct itd1000_state *state = fe->tuner_priv;
  270. int i;
  271. for (i = 0; i < ARRAY_SIZE(itd1000_init_tab); i++)
  272. itd1000_write_reg(state, itd1000_init_tab[i][0], itd1000_init_tab[i][1]);
  273. for (i = 0; i < ARRAY_SIZE(itd1000_reinit_tab); i++)
  274. itd1000_write_reg(state, itd1000_reinit_tab[i][0], itd1000_reinit_tab[i][1]);
  275. return 0;
  276. }
  277. static int itd1000_sleep(struct dvb_frontend *fe)
  278. {
  279. return 0;
  280. }
  281. static void itd1000_release(struct dvb_frontend *fe)
  282. {
  283. kfree(fe->tuner_priv);
  284. fe->tuner_priv = NULL;
  285. }
  286. static const struct dvb_tuner_ops itd1000_tuner_ops = {
  287. .info = {
  288. .name = "Integrant ITD1000",
  289. .frequency_min_hz = 950 * MHz,
  290. .frequency_max_hz = 2150 * MHz,
  291. .frequency_step_hz = 125 * kHz,
  292. },
  293. .release = itd1000_release,
  294. .init = itd1000_init,
  295. .sleep = itd1000_sleep,
  296. .set_params = itd1000_set_parameters,
  297. .get_frequency = itd1000_get_frequency,
  298. .get_bandwidth = itd1000_get_bandwidth
  299. };
  300. struct dvb_frontend *itd1000_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct itd1000_config *cfg)
  301. {
  302. struct itd1000_state *state = NULL;
  303. u8 i = 0;
  304. state = kzalloc(sizeof(struct itd1000_state), GFP_KERNEL);
  305. if (state == NULL)
  306. return NULL;
  307. state->cfg = cfg;
  308. state->i2c = i2c;
  309. i = itd1000_read_reg(state, 0);
  310. if (i != 0) {
  311. kfree(state);
  312. return NULL;
  313. }
  314. itd_info("successfully identified (ID: %d)\n", i);
  315. memset(state->shadow, 0xff, sizeof(state->shadow));
  316. for (i = 0x65; i < 0x9c; i++)
  317. state->shadow[i] = itd1000_read_reg(state, i);
  318. memcpy(&fe->ops.tuner_ops, &itd1000_tuner_ops, sizeof(struct dvb_tuner_ops));
  319. fe->tuner_priv = state;
  320. return fe;
  321. }
  322. EXPORT_SYMBOL(itd1000_attach);
  323. MODULE_AUTHOR("Patrick Boettcher <pb@linuxtv.org>");
  324. MODULE_DESCRIPTION("Integrant ITD1000 driver");
  325. MODULE_LICENSE("GPL");