dib3000mb_priv.h 15 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * dib3000mb_priv.h
  4. *
  5. * Copyright (C) 2004 Patrick Boettcher (patrick.boettcher@posteo.de)
  6. *
  7. * for more information see dib3000mb.c .
  8. */
  9. #ifndef __DIB3000MB_PRIV_H_INCLUDED__
  10. #define __DIB3000MB_PRIV_H_INCLUDED__
  11. /* handy shortcuts */
  12. #define rd(reg) dib3000_read_reg(state,reg)
  13. #define wr(reg,val) if (dib3000_write_reg(state,reg,val)) \
  14. { pr_err("while sending 0x%04x to 0x%04x.", val, reg); return -EREMOTEIO; }
  15. #define wr_foreach(a,v) { int i; \
  16. if (sizeof(a) != sizeof(v)) \
  17. pr_err("sizeof: %zu %zu is different", sizeof(a), sizeof(v));\
  18. for (i=0; i < sizeof(a)/sizeof(u16); i++) \
  19. wr(a[i],v[i]); \
  20. }
  21. #define set_or(reg,val) wr(reg,rd(reg) | val)
  22. #define set_and(reg,val) wr(reg,rd(reg) & val)
  23. /* debug */
  24. #define dprintk(level, fmt, arg...) do { \
  25. if (debug & level) \
  26. printk(KERN_DEBUG pr_fmt("%s: " fmt), \
  27. __func__, ##arg); \
  28. } while (0)
  29. /* mask for enabling a specific pid for the pid_filter */
  30. #define DIB3000_ACTIVATE_PID_FILTERING (0x2000)
  31. /* common values for tuning */
  32. #define DIB3000_ALPHA_0 ( 0)
  33. #define DIB3000_ALPHA_1 ( 1)
  34. #define DIB3000_ALPHA_2 ( 2)
  35. #define DIB3000_ALPHA_4 ( 4)
  36. #define DIB3000_CONSTELLATION_QPSK ( 0)
  37. #define DIB3000_CONSTELLATION_16QAM ( 1)
  38. #define DIB3000_CONSTELLATION_64QAM ( 2)
  39. #define DIB3000_GUARD_TIME_1_32 ( 0)
  40. #define DIB3000_GUARD_TIME_1_16 ( 1)
  41. #define DIB3000_GUARD_TIME_1_8 ( 2)
  42. #define DIB3000_GUARD_TIME_1_4 ( 3)
  43. #define DIB3000_TRANSMISSION_MODE_2K ( 0)
  44. #define DIB3000_TRANSMISSION_MODE_8K ( 1)
  45. #define DIB3000_SELECT_LP ( 0)
  46. #define DIB3000_SELECT_HP ( 1)
  47. #define DIB3000_FEC_1_2 ( 1)
  48. #define DIB3000_FEC_2_3 ( 2)
  49. #define DIB3000_FEC_3_4 ( 3)
  50. #define DIB3000_FEC_5_6 ( 5)
  51. #define DIB3000_FEC_7_8 ( 7)
  52. #define DIB3000_HRCH_OFF ( 0)
  53. #define DIB3000_HRCH_ON ( 1)
  54. #define DIB3000_DDS_INVERSION_OFF ( 0)
  55. #define DIB3000_DDS_INVERSION_ON ( 1)
  56. #define DIB3000_TUNER_WRITE_ENABLE(a) (0xffff & (a << 8))
  57. #define DIB3000_TUNER_WRITE_DISABLE(a) (0xffff & ((a << 8) | (1 << 7)))
  58. #define DIB3000_REG_MANUFACTOR_ID ( 1025)
  59. #define DIB3000_I2C_ID_DIBCOM (0x01b3)
  60. #define DIB3000_REG_DEVICE_ID ( 1026)
  61. #define DIB3000MB_DEVICE_ID (0x3000)
  62. #define DIB3000MC_DEVICE_ID (0x3001)
  63. #define DIB3000P_DEVICE_ID (0x3002)
  64. /* frontend state */
  65. struct dib3000_state {
  66. struct i2c_adapter* i2c;
  67. /* configuration settings */
  68. struct dib3000_config config;
  69. struct dvb_frontend frontend;
  70. int timing_offset;
  71. int timing_offset_comp_done;
  72. u32 last_tuned_bw;
  73. u32 last_tuned_freq;
  74. };
  75. /* register addresses and some of their default values */
  76. /* restart subsystems */
  77. #define DIB3000MB_REG_RESTART ( 0)
  78. #define DIB3000MB_RESTART_OFF ( 0)
  79. #define DIB3000MB_RESTART_AUTO_SEARCH (1 << 1)
  80. #define DIB3000MB_RESTART_CTRL (1 << 2)
  81. #define DIB3000MB_RESTART_AGC (1 << 3)
  82. /* FFT size */
  83. #define DIB3000MB_REG_FFT ( 1)
  84. /* Guard time */
  85. #define DIB3000MB_REG_GUARD_TIME ( 2)
  86. /* QAM */
  87. #define DIB3000MB_REG_QAM ( 3)
  88. /* Alpha coefficient high priority Viterbi algorithm */
  89. #define DIB3000MB_REG_VIT_ALPHA ( 4)
  90. /* spectrum inversion */
  91. #define DIB3000MB_REG_DDS_INV ( 5)
  92. /* DDS frequency value (IF position) ad ? values don't match reg_3000mb.txt */
  93. #define DIB3000MB_REG_DDS_FREQ_MSB ( 6)
  94. #define DIB3000MB_REG_DDS_FREQ_LSB ( 7)
  95. #define DIB3000MB_DDS_FREQ_MSB ( 178)
  96. #define DIB3000MB_DDS_FREQ_LSB ( 8990)
  97. /* timing frequency (carrier spacing) */
  98. static u16 dib3000mb_reg_timing_freq[] = { 8,9 };
  99. static u16 dib3000mb_timing_freq[][2] = {
  100. { 126 , 48873 }, /* 6 MHz */
  101. { 147 , 57019 }, /* 7 MHz */
  102. { 168 , 65164 }, /* 8 MHz */
  103. };
  104. /* impulse noise parameter */
  105. /* 36 ??? */
  106. static u16 dib3000mb_reg_impulse_noise[] = { 10,11,12,15,36 };
  107. enum dib3000mb_impulse_noise_type {
  108. DIB3000MB_IMPNOISE_OFF,
  109. DIB3000MB_IMPNOISE_MOBILE,
  110. DIB3000MB_IMPNOISE_FIXED,
  111. DIB3000MB_IMPNOISE_DEFAULT
  112. };
  113. static u16 dib3000mb_impulse_noise_values[][5] = {
  114. { 0x0000, 0x0004, 0x0014, 0x01ff, 0x0399 }, /* off */
  115. { 0x0001, 0x0004, 0x0014, 0x01ff, 0x037b }, /* mobile */
  116. { 0x0001, 0x0004, 0x0020, 0x01bd, 0x0399 }, /* fixed */
  117. { 0x0000, 0x0002, 0x000a, 0x01ff, 0x0399 }, /* default */
  118. };
  119. /*
  120. * Dual Automatic-Gain-Control
  121. * - gains RF in tuner (AGC1)
  122. * - gains IF after filtering (AGC2)
  123. */
  124. /* also from 16 to 18 */
  125. static u16 dib3000mb_reg_agc_gain[] = {
  126. 19,20,21,22,23,24,25,26,27,28,29,30,31,32
  127. };
  128. static u16 dib3000mb_default_agc_gain[] =
  129. { 0x0001, 52429, 623, 128, 166, 195, 61, /* RF ??? */
  130. 0x0001, 53766, 38011, 0, 90, 33, 23 }; /* IF ??? */
  131. /* phase noise */
  132. /* 36 is set when setting the impulse noise */
  133. static u16 dib3000mb_reg_phase_noise[] = { 33,34,35,37,38 };
  134. static u16 dib3000mb_default_noise_phase[] = { 2, 544, 0, 5, 4 };
  135. /* lock duration */
  136. static u16 dib3000mb_reg_lock_duration[] = { 39,40 };
  137. static u16 dib3000mb_default_lock_duration[] = { 135, 135 };
  138. /* AGC loop bandwidth */
  139. static u16 dib3000mb_reg_agc_bandwidth[] = { 43,44,45,46,47,48,49,50 };
  140. static u16 dib3000mb_agc_bandwidth_low[] =
  141. { 2088, 10, 2088, 10, 3448, 5, 3448, 5 };
  142. static u16 dib3000mb_agc_bandwidth_high[] =
  143. { 2349, 5, 2349, 5, 2586, 2, 2586, 2 };
  144. /*
  145. * lock0 definition (coff_lock)
  146. */
  147. #define DIB3000MB_REG_LOCK0_MASK ( 51)
  148. #define DIB3000MB_LOCK0_DEFAULT ( 4)
  149. /*
  150. * lock1 definition (cpil_lock)
  151. * for auto search
  152. * which values hide behind the lock masks
  153. */
  154. #define DIB3000MB_REG_LOCK1_MASK ( 52)
  155. #define DIB3000MB_LOCK1_SEARCH_4 (0x0004)
  156. #define DIB3000MB_LOCK1_SEARCH_2048 (0x0800)
  157. #define DIB3000MB_LOCK1_DEFAULT (0x0001)
  158. /*
  159. * lock2 definition (fec_lock) */
  160. #define DIB3000MB_REG_LOCK2_MASK ( 53)
  161. #define DIB3000MB_LOCK2_DEFAULT (0x0080)
  162. /*
  163. * SEQ ? what was that again ... :)
  164. * changes when, inversion, guard time and fft is
  165. * either automatically detected or not
  166. */
  167. #define DIB3000MB_REG_SEQ ( 54)
  168. /* bandwidth */
  169. static u16 dib3000mb_reg_bandwidth[] = { 55,56,57,58,59,60,61,62,63,64,65,66,67 };
  170. static u16 dib3000mb_bandwidth_6mhz[] =
  171. { 0, 33, 53312, 112, 46635, 563, 36565, 0, 1000, 0, 1010, 1, 45264 };
  172. static u16 dib3000mb_bandwidth_7mhz[] =
  173. { 0, 28, 64421, 96, 39973, 483, 3255, 0, 1000, 0, 1010, 1, 45264 };
  174. static u16 dib3000mb_bandwidth_8mhz[] =
  175. { 0, 25, 23600, 84, 34976, 422, 43808, 0, 1000, 0, 1010, 1, 45264 };
  176. #define DIB3000MB_REG_UNK_68 ( 68)
  177. #define DIB3000MB_UNK_68 ( 0)
  178. #define DIB3000MB_REG_UNK_69 ( 69)
  179. #define DIB3000MB_UNK_69 ( 0)
  180. #define DIB3000MB_REG_UNK_71 ( 71)
  181. #define DIB3000MB_UNK_71 ( 0)
  182. #define DIB3000MB_REG_UNK_77 ( 77)
  183. #define DIB3000MB_UNK_77 ( 6)
  184. #define DIB3000MB_REG_UNK_78 ( 78)
  185. #define DIB3000MB_UNK_78 (0x0080)
  186. /* isi */
  187. #define DIB3000MB_REG_ISI ( 79)
  188. #define DIB3000MB_ISI_ACTIVATE ( 0)
  189. #define DIB3000MB_ISI_INHIBIT ( 1)
  190. /* sync impovement */
  191. #define DIB3000MB_REG_SYNC_IMPROVEMENT ( 84)
  192. #define DIB3000MB_SYNC_IMPROVE_2K_1_8 ( 3)
  193. #define DIB3000MB_SYNC_IMPROVE_DEFAULT ( 0)
  194. /* phase noise compensation inhibition */
  195. #define DIB3000MB_REG_PHASE_NOISE ( 87)
  196. #define DIB3000MB_PHASE_NOISE_DEFAULT ( 0)
  197. #define DIB3000MB_REG_UNK_92 ( 92)
  198. #define DIB3000MB_UNK_92 (0x0080)
  199. #define DIB3000MB_REG_UNK_96 ( 96)
  200. #define DIB3000MB_UNK_96 (0x0010)
  201. #define DIB3000MB_REG_UNK_97 ( 97)
  202. #define DIB3000MB_UNK_97 (0x0009)
  203. /* mobile mode ??? */
  204. #define DIB3000MB_REG_MOBILE_MODE ( 101)
  205. #define DIB3000MB_MOBILE_MODE_ON ( 1)
  206. #define DIB3000MB_MOBILE_MODE_OFF ( 0)
  207. #define DIB3000MB_REG_UNK_106 ( 106)
  208. #define DIB3000MB_UNK_106 (0x0080)
  209. #define DIB3000MB_REG_UNK_107 ( 107)
  210. #define DIB3000MB_UNK_107 (0x0080)
  211. #define DIB3000MB_REG_UNK_108 ( 108)
  212. #define DIB3000MB_UNK_108 (0x0080)
  213. /* fft */
  214. #define DIB3000MB_REG_UNK_121 ( 121)
  215. #define DIB3000MB_UNK_121_2K ( 7)
  216. #define DIB3000MB_UNK_121_DEFAULT ( 5)
  217. #define DIB3000MB_REG_UNK_122 ( 122)
  218. #define DIB3000MB_UNK_122 ( 2867)
  219. /* QAM for mobile mode */
  220. #define DIB3000MB_REG_MOBILE_MODE_QAM ( 126)
  221. #define DIB3000MB_MOBILE_MODE_QAM_64 ( 3)
  222. #define DIB3000MB_MOBILE_MODE_QAM_QPSK_16 ( 1)
  223. #define DIB3000MB_MOBILE_MODE_QAM_OFF ( 0)
  224. /*
  225. * data diversity when having more than one chip on-board
  226. * see also DIB3000MB_OUTPUT_MODE_DATA_DIVERSITY
  227. */
  228. #define DIB3000MB_REG_DATA_IN_DIVERSITY ( 127)
  229. #define DIB3000MB_DATA_DIVERSITY_IN_OFF ( 0)
  230. #define DIB3000MB_DATA_DIVERSITY_IN_ON ( 2)
  231. /* vit hrch */
  232. #define DIB3000MB_REG_VIT_HRCH ( 128)
  233. /* vit code rate */
  234. #define DIB3000MB_REG_VIT_CODE_RATE ( 129)
  235. /* vit select hp */
  236. #define DIB3000MB_REG_VIT_HP ( 130)
  237. /* time frame for Bit-Error-Rate calculation */
  238. #define DIB3000MB_REG_BERLEN ( 135)
  239. #define DIB3000MB_BERLEN_LONG ( 0)
  240. #define DIB3000MB_BERLEN_DEFAULT ( 1)
  241. #define DIB3000MB_BERLEN_MEDIUM ( 2)
  242. #define DIB3000MB_BERLEN_SHORT ( 3)
  243. /* 142 - 152 FIFO parameters
  244. * which is what ?
  245. */
  246. #define DIB3000MB_REG_FIFO_142 ( 142)
  247. #define DIB3000MB_FIFO_142 ( 0)
  248. /* MPEG2 TS output mode */
  249. #define DIB3000MB_REG_MPEG2_OUT_MODE ( 143)
  250. #define DIB3000MB_MPEG2_OUT_MODE_204 ( 0)
  251. #define DIB3000MB_MPEG2_OUT_MODE_188 ( 1)
  252. #define DIB3000MB_REG_PID_PARSE ( 144)
  253. #define DIB3000MB_PID_PARSE_INHIBIT ( 0)
  254. #define DIB3000MB_PID_PARSE_ACTIVATE ( 1)
  255. #define DIB3000MB_REG_FIFO ( 145)
  256. #define DIB3000MB_FIFO_INHIBIT ( 1)
  257. #define DIB3000MB_FIFO_ACTIVATE ( 0)
  258. #define DIB3000MB_REG_FIFO_146 ( 146)
  259. #define DIB3000MB_FIFO_146 ( 3)
  260. #define DIB3000MB_REG_FIFO_147 ( 147)
  261. #define DIB3000MB_FIFO_147 (0x0100)
  262. /*
  263. * pidfilter
  264. * it is not a hardware pidfilter but a filter which drops all pids
  265. * except the ones set. Necessary because of the limited USB1.1 bandwidth.
  266. * regs 153-168
  267. */
  268. #define DIB3000MB_REG_FIRST_PID ( 153)
  269. #define DIB3000MB_NUM_PIDS ( 16)
  270. /*
  271. * output mode
  272. * USB devices have to use 'slave'-mode
  273. * see also DIB3000MB_REG_ELECT_OUT_MODE
  274. */
  275. #define DIB3000MB_REG_OUTPUT_MODE ( 169)
  276. #define DIB3000MB_OUTPUT_MODE_GATED_CLK ( 0)
  277. #define DIB3000MB_OUTPUT_MODE_CONT_CLK ( 1)
  278. #define DIB3000MB_OUTPUT_MODE_SERIAL ( 2)
  279. #define DIB3000MB_OUTPUT_MODE_DATA_DIVERSITY ( 5)
  280. #define DIB3000MB_OUTPUT_MODE_SLAVE ( 6)
  281. /* irq event mask */
  282. #define DIB3000MB_REG_IRQ_EVENT_MASK ( 170)
  283. #define DIB3000MB_IRQ_EVENT_MASK ( 0)
  284. /* filter coefficients */
  285. static u16 dib3000mb_reg_filter_coeffs[] = {
  286. 171, 172, 173, 174, 175, 176, 177, 178,
  287. 179, 180, 181, 182, 183, 184, 185, 186,
  288. 188, 189, 190, 191, 192, 194
  289. };
  290. static u16 dib3000mb_filter_coeffs[] = {
  291. 226, 160, 29,
  292. 979, 998, 19,
  293. 22, 1019, 1006,
  294. 1022, 12, 6,
  295. 1017, 1017, 3,
  296. 6, 1019,
  297. 1021, 2, 3,
  298. 1, 0,
  299. };
  300. /*
  301. * mobile algorithm (when you are moving with your device)
  302. * but not faster than 90 km/h
  303. */
  304. #define DIB3000MB_REG_MOBILE_ALGO ( 195)
  305. #define DIB3000MB_MOBILE_ALGO_ON ( 0)
  306. #define DIB3000MB_MOBILE_ALGO_OFF ( 1)
  307. /* multiple demodulators algorithm */
  308. #define DIB3000MB_REG_MULTI_DEMOD_MSB ( 206)
  309. #define DIB3000MB_REG_MULTI_DEMOD_LSB ( 207)
  310. /* terminator, no more demods */
  311. #define DIB3000MB_MULTI_DEMOD_MSB ( 32767)
  312. #define DIB3000MB_MULTI_DEMOD_LSB ( 4095)
  313. /* bring the device into a known */
  314. #define DIB3000MB_REG_RESET_DEVICE ( 1024)
  315. #define DIB3000MB_RESET_DEVICE (0x812c)
  316. #define DIB3000MB_RESET_DEVICE_RST ( 0)
  317. /* hardware clock configuration */
  318. #define DIB3000MB_REG_CLOCK ( 1027)
  319. #define DIB3000MB_CLOCK_DEFAULT (0x9000)
  320. #define DIB3000MB_CLOCK_DIVERSITY (0x92b0)
  321. /* power down config */
  322. #define DIB3000MB_REG_POWER_CONTROL ( 1028)
  323. #define DIB3000MB_POWER_DOWN ( 1)
  324. #define DIB3000MB_POWER_UP ( 0)
  325. /* electrical output mode */
  326. #define DIB3000MB_REG_ELECT_OUT_MODE ( 1029)
  327. #define DIB3000MB_ELECT_OUT_MODE_OFF ( 0)
  328. #define DIB3000MB_ELECT_OUT_MODE_ON ( 1)
  329. /* set the tuner i2c address */
  330. #define DIB3000MB_REG_TUNER ( 1089)
  331. /* monitoring registers (read only) */
  332. /* agc loop locked (size: 1) */
  333. #define DIB3000MB_REG_AGC_LOCK ( 324)
  334. /* agc power (size: 16) */
  335. #define DIB3000MB_REG_AGC_POWER ( 325)
  336. /* agc1 value (16) */
  337. #define DIB3000MB_REG_AGC1_VALUE ( 326)
  338. /* agc2 value (16) */
  339. #define DIB3000MB_REG_AGC2_VALUE ( 327)
  340. /* total RF power (16), can be used for signal strength */
  341. #define DIB3000MB_REG_RF_POWER ( 328)
  342. /* dds_frequency with offset (24) */
  343. #define DIB3000MB_REG_DDS_VALUE_MSB ( 339)
  344. #define DIB3000MB_REG_DDS_VALUE_LSB ( 340)
  345. /* timing offset signed (24) */
  346. #define DIB3000MB_REG_TIMING_OFFSET_MSB ( 341)
  347. #define DIB3000MB_REG_TIMING_OFFSET_LSB ( 342)
  348. /* fft start position (13) */
  349. #define DIB3000MB_REG_FFT_WINDOW_POS ( 353)
  350. /* carriers locked (1) */
  351. #define DIB3000MB_REG_CARRIER_LOCK ( 355)
  352. /* noise power (24) */
  353. #define DIB3000MB_REG_NOISE_POWER_MSB ( 372)
  354. #define DIB3000MB_REG_NOISE_POWER_LSB ( 373)
  355. #define DIB3000MB_REG_MOBILE_NOISE_MSB ( 374)
  356. #define DIB3000MB_REG_MOBILE_NOISE_LSB ( 375)
  357. /*
  358. * signal power (16), this and the above can be
  359. * used to calculate the signal/noise - ratio
  360. */
  361. #define DIB3000MB_REG_SIGNAL_POWER ( 380)
  362. /* mer (24) */
  363. #define DIB3000MB_REG_MER_MSB ( 381)
  364. #define DIB3000MB_REG_MER_LSB ( 382)
  365. /*
  366. * Transmission Parameter Signalling (TPS)
  367. * the following registers can be used to get TPS-information.
  368. * The values are according to the DVB-T standard.
  369. */
  370. /* TPS locked (1) */
  371. #define DIB3000MB_REG_TPS_LOCK ( 394)
  372. /* QAM from TPS (2) (values according to DIB3000MB_REG_QAM) */
  373. #define DIB3000MB_REG_TPS_QAM ( 398)
  374. /* hierarchy from TPS (1) */
  375. #define DIB3000MB_REG_TPS_HRCH ( 399)
  376. /* alpha from TPS (3) (values according to DIB3000MB_REG_VIT_ALPHA) */
  377. #define DIB3000MB_REG_TPS_VIT_ALPHA ( 400)
  378. /* code rate high priority from TPS (3) (values according to DIB3000MB_FEC_*) */
  379. #define DIB3000MB_REG_TPS_CODE_RATE_HP ( 401)
  380. /* code rate low priority from TPS (3) if DIB3000MB_REG_TPS_VIT_ALPHA */
  381. #define DIB3000MB_REG_TPS_CODE_RATE_LP ( 402)
  382. /* guard time from TPS (2) (values according to DIB3000MB_REG_GUARD_TIME */
  383. #define DIB3000MB_REG_TPS_GUARD_TIME ( 403)
  384. /* fft size from TPS (2) (values according to DIB3000MB_REG_FFT) */
  385. #define DIB3000MB_REG_TPS_FFT ( 404)
  386. /* cell id from TPS (16) */
  387. #define DIB3000MB_REG_TPS_CELL_ID ( 406)
  388. /* TPS (68) */
  389. #define DIB3000MB_REG_TPS_1 ( 408)
  390. #define DIB3000MB_REG_TPS_2 ( 409)
  391. #define DIB3000MB_REG_TPS_3 ( 410)
  392. #define DIB3000MB_REG_TPS_4 ( 411)
  393. #define DIB3000MB_REG_TPS_5 ( 412)
  394. /* bit error rate (before RS correction) (21) */
  395. #define DIB3000MB_REG_BER_MSB ( 414)
  396. #define DIB3000MB_REG_BER_LSB ( 415)
  397. /* packet error rate (uncorrected TS packets) (16) */
  398. #define DIB3000MB_REG_PACKET_ERROR_RATE ( 417)
  399. /* uncorrected packet count (16) */
  400. #define DIB3000MB_REG_UNC ( 420)
  401. /* viterbi locked (1) */
  402. #define DIB3000MB_REG_VIT_LCK ( 421)
  403. /* viterbi inidcator (16) */
  404. #define DIB3000MB_REG_VIT_INDICATOR ( 422)
  405. /* transport stream sync lock (1) */
  406. #define DIB3000MB_REG_TS_SYNC_LOCK ( 423)
  407. /* transport stream RS lock (1) */
  408. #define DIB3000MB_REG_TS_RS_LOCK ( 424)
  409. /* lock mask 0 value (1) */
  410. #define DIB3000MB_REG_LOCK0_VALUE ( 425)
  411. /* lock mask 1 value (1) */
  412. #define DIB3000MB_REG_LOCK1_VALUE ( 426)
  413. /* lock mask 2 value (1) */
  414. #define DIB3000MB_REG_LOCK2_VALUE ( 427)
  415. /* interrupt pending for auto search */
  416. #define DIB3000MB_REG_AS_IRQ_PENDING ( 434)
  417. #endif