dev.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Tegra host1x driver
  4. *
  5. * Copyright (c) 2010-2013, NVIDIA Corporation.
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/dma-mapping.h>
  9. #include <linux/io.h>
  10. #include <linux/list.h>
  11. #include <linux/module.h>
  12. #include <linux/of_device.h>
  13. #include <linux/of.h>
  14. #include <linux/slab.h>
  15. #define CREATE_TRACE_POINTS
  16. #include <trace/events/host1x.h>
  17. #undef CREATE_TRACE_POINTS
  18. #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
  19. #include <asm/dma-iommu.h>
  20. #endif
  21. #include "bus.h"
  22. #include "channel.h"
  23. #include "debug.h"
  24. #include "dev.h"
  25. #include "intr.h"
  26. #include "hw/host1x01.h"
  27. #include "hw/host1x02.h"
  28. #include "hw/host1x04.h"
  29. #include "hw/host1x05.h"
  30. #include "hw/host1x06.h"
  31. #include "hw/host1x07.h"
  32. void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r)
  33. {
  34. writel(v, host1x->hv_regs + r);
  35. }
  36. u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r)
  37. {
  38. return readl(host1x->hv_regs + r);
  39. }
  40. void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r)
  41. {
  42. void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
  43. writel(v, sync_regs + r);
  44. }
  45. u32 host1x_sync_readl(struct host1x *host1x, u32 r)
  46. {
  47. void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
  48. return readl(sync_regs + r);
  49. }
  50. void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r)
  51. {
  52. writel(v, ch->regs + r);
  53. }
  54. u32 host1x_ch_readl(struct host1x_channel *ch, u32 r)
  55. {
  56. return readl(ch->regs + r);
  57. }
  58. static const struct host1x_info host1x01_info = {
  59. .nb_channels = 8,
  60. .nb_pts = 32,
  61. .nb_mlocks = 16,
  62. .nb_bases = 8,
  63. .init = host1x01_init,
  64. .sync_offset = 0x3000,
  65. .dma_mask = DMA_BIT_MASK(32),
  66. };
  67. static const struct host1x_info host1x02_info = {
  68. .nb_channels = 9,
  69. .nb_pts = 32,
  70. .nb_mlocks = 16,
  71. .nb_bases = 12,
  72. .init = host1x02_init,
  73. .sync_offset = 0x3000,
  74. .dma_mask = DMA_BIT_MASK(32),
  75. };
  76. static const struct host1x_info host1x04_info = {
  77. .nb_channels = 12,
  78. .nb_pts = 192,
  79. .nb_mlocks = 16,
  80. .nb_bases = 64,
  81. .init = host1x04_init,
  82. .sync_offset = 0x2100,
  83. .dma_mask = DMA_BIT_MASK(34),
  84. };
  85. static const struct host1x_info host1x05_info = {
  86. .nb_channels = 14,
  87. .nb_pts = 192,
  88. .nb_mlocks = 16,
  89. .nb_bases = 64,
  90. .init = host1x05_init,
  91. .sync_offset = 0x2100,
  92. .dma_mask = DMA_BIT_MASK(34),
  93. };
  94. static const struct host1x_sid_entry tegra186_sid_table[] = {
  95. {
  96. /* VIC */
  97. .base = 0x1af0,
  98. .offset = 0x30,
  99. .limit = 0x34
  100. },
  101. };
  102. static const struct host1x_info host1x06_info = {
  103. .nb_channels = 63,
  104. .nb_pts = 576,
  105. .nb_mlocks = 24,
  106. .nb_bases = 16,
  107. .init = host1x06_init,
  108. .sync_offset = 0x0,
  109. .dma_mask = DMA_BIT_MASK(40),
  110. .has_hypervisor = true,
  111. .num_sid_entries = ARRAY_SIZE(tegra186_sid_table),
  112. .sid_table = tegra186_sid_table,
  113. };
  114. static const struct host1x_sid_entry tegra194_sid_table[] = {
  115. {
  116. /* VIC */
  117. .base = 0x1af0,
  118. .offset = 0x30,
  119. .limit = 0x34
  120. },
  121. };
  122. static const struct host1x_info host1x07_info = {
  123. .nb_channels = 63,
  124. .nb_pts = 704,
  125. .nb_mlocks = 32,
  126. .nb_bases = 0,
  127. .init = host1x07_init,
  128. .sync_offset = 0x0,
  129. .dma_mask = DMA_BIT_MASK(40),
  130. .has_hypervisor = true,
  131. .num_sid_entries = ARRAY_SIZE(tegra194_sid_table),
  132. .sid_table = tegra194_sid_table,
  133. };
  134. static const struct of_device_id host1x_of_match[] = {
  135. { .compatible = "nvidia,tegra194-host1x", .data = &host1x07_info, },
  136. { .compatible = "nvidia,tegra186-host1x", .data = &host1x06_info, },
  137. { .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, },
  138. { .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, },
  139. { .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, },
  140. { .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, },
  141. { .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, },
  142. { },
  143. };
  144. MODULE_DEVICE_TABLE(of, host1x_of_match);
  145. static void host1x_setup_sid_table(struct host1x *host)
  146. {
  147. const struct host1x_info *info = host->info;
  148. unsigned int i;
  149. for (i = 0; i < info->num_sid_entries; i++) {
  150. const struct host1x_sid_entry *entry = &info->sid_table[i];
  151. host1x_hypervisor_writel(host, entry->offset, entry->base);
  152. host1x_hypervisor_writel(host, entry->limit, entry->base + 4);
  153. }
  154. }
  155. static int host1x_probe(struct platform_device *pdev)
  156. {
  157. struct host1x *host;
  158. struct resource *regs, *hv_regs = NULL;
  159. int syncpt_irq;
  160. int err;
  161. host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
  162. if (!host)
  163. return -ENOMEM;
  164. host->info = of_device_get_match_data(&pdev->dev);
  165. if (host->info->has_hypervisor) {
  166. regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vm");
  167. if (!regs) {
  168. dev_err(&pdev->dev, "failed to get vm registers\n");
  169. return -ENXIO;
  170. }
  171. hv_regs = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  172. "hypervisor");
  173. if (!hv_regs) {
  174. dev_err(&pdev->dev,
  175. "failed to get hypervisor registers\n");
  176. return -ENXIO;
  177. }
  178. } else {
  179. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  180. if (!regs) {
  181. dev_err(&pdev->dev, "failed to get registers\n");
  182. return -ENXIO;
  183. }
  184. }
  185. syncpt_irq = platform_get_irq(pdev, 0);
  186. if (syncpt_irq < 0) {
  187. dev_err(&pdev->dev, "failed to get IRQ: %d\n", syncpt_irq);
  188. return syncpt_irq;
  189. }
  190. mutex_init(&host->devices_lock);
  191. INIT_LIST_HEAD(&host->devices);
  192. INIT_LIST_HEAD(&host->list);
  193. host->dev = &pdev->dev;
  194. /* set common host1x device data */
  195. platform_set_drvdata(pdev, host);
  196. host->regs = devm_ioremap_resource(&pdev->dev, regs);
  197. if (IS_ERR(host->regs))
  198. return PTR_ERR(host->regs);
  199. if (host->info->has_hypervisor) {
  200. host->hv_regs = devm_ioremap_resource(&pdev->dev, hv_regs);
  201. if (IS_ERR(host->hv_regs))
  202. return PTR_ERR(host->hv_regs);
  203. }
  204. dma_set_mask_and_coherent(host->dev, host->info->dma_mask);
  205. if (host->info->init) {
  206. err = host->info->init(host);
  207. if (err)
  208. return err;
  209. }
  210. host->clk = devm_clk_get(&pdev->dev, NULL);
  211. if (IS_ERR(host->clk)) {
  212. err = PTR_ERR(host->clk);
  213. if (err != -EPROBE_DEFER)
  214. dev_err(&pdev->dev, "failed to get clock: %d\n", err);
  215. return err;
  216. }
  217. host->rst = devm_reset_control_get(&pdev->dev, "host1x");
  218. if (IS_ERR(host->rst)) {
  219. err = PTR_ERR(host->rst);
  220. dev_err(&pdev->dev, "failed to get reset: %d\n", err);
  221. return err;
  222. }
  223. #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
  224. if (host->dev->archdata.mapping) {
  225. struct dma_iommu_mapping *mapping =
  226. to_dma_iommu_mapping(host->dev);
  227. arm_iommu_detach_device(host->dev);
  228. arm_iommu_release_mapping(mapping);
  229. }
  230. #endif
  231. if (IS_ENABLED(CONFIG_TEGRA_HOST1X_FIREWALL))
  232. goto skip_iommu;
  233. host->group = iommu_group_get(&pdev->dev);
  234. if (host->group) {
  235. struct iommu_domain_geometry *geometry;
  236. u64 mask = dma_get_mask(host->dev);
  237. dma_addr_t start, end;
  238. unsigned long order;
  239. err = iova_cache_get();
  240. if (err < 0)
  241. goto put_group;
  242. host->domain = iommu_domain_alloc(&platform_bus_type);
  243. if (!host->domain) {
  244. err = -ENOMEM;
  245. goto put_cache;
  246. }
  247. err = iommu_attach_group(host->domain, host->group);
  248. if (err) {
  249. if (err == -ENODEV) {
  250. iommu_domain_free(host->domain);
  251. host->domain = NULL;
  252. iova_cache_put();
  253. iommu_group_put(host->group);
  254. host->group = NULL;
  255. goto skip_iommu;
  256. }
  257. goto fail_free_domain;
  258. }
  259. geometry = &host->domain->geometry;
  260. start = geometry->aperture_start & mask;
  261. end = geometry->aperture_end & mask;
  262. order = __ffs(host->domain->pgsize_bitmap);
  263. init_iova_domain(&host->iova, 1UL << order, start >> order);
  264. host->iova_end = end;
  265. }
  266. skip_iommu:
  267. err = host1x_channel_list_init(&host->channel_list,
  268. host->info->nb_channels);
  269. if (err) {
  270. dev_err(&pdev->dev, "failed to initialize channel list\n");
  271. goto fail_detach_device;
  272. }
  273. err = clk_prepare_enable(host->clk);
  274. if (err < 0) {
  275. dev_err(&pdev->dev, "failed to enable clock\n");
  276. goto fail_free_channels;
  277. }
  278. err = reset_control_deassert(host->rst);
  279. if (err < 0) {
  280. dev_err(&pdev->dev, "failed to deassert reset: %d\n", err);
  281. goto fail_unprepare_disable;
  282. }
  283. err = host1x_syncpt_init(host);
  284. if (err) {
  285. dev_err(&pdev->dev, "failed to initialize syncpts\n");
  286. goto fail_reset_assert;
  287. }
  288. err = host1x_intr_init(host, syncpt_irq);
  289. if (err) {
  290. dev_err(&pdev->dev, "failed to initialize interrupts\n");
  291. goto fail_deinit_syncpt;
  292. }
  293. host1x_debug_init(host);
  294. if (host->info->has_hypervisor)
  295. host1x_setup_sid_table(host);
  296. err = host1x_register(host);
  297. if (err < 0)
  298. goto fail_deinit_intr;
  299. return 0;
  300. fail_deinit_intr:
  301. host1x_intr_deinit(host);
  302. fail_deinit_syncpt:
  303. host1x_syncpt_deinit(host);
  304. fail_reset_assert:
  305. reset_control_assert(host->rst);
  306. fail_unprepare_disable:
  307. clk_disable_unprepare(host->clk);
  308. fail_free_channels:
  309. host1x_channel_list_free(&host->channel_list);
  310. fail_detach_device:
  311. if (host->group && host->domain) {
  312. put_iova_domain(&host->iova);
  313. iommu_detach_group(host->domain, host->group);
  314. }
  315. fail_free_domain:
  316. if (host->domain)
  317. iommu_domain_free(host->domain);
  318. put_cache:
  319. if (host->group)
  320. iova_cache_put();
  321. put_group:
  322. iommu_group_put(host->group);
  323. return err;
  324. }
  325. static int host1x_remove(struct platform_device *pdev)
  326. {
  327. struct host1x *host = platform_get_drvdata(pdev);
  328. host1x_unregister(host);
  329. host1x_intr_deinit(host);
  330. host1x_syncpt_deinit(host);
  331. reset_control_assert(host->rst);
  332. clk_disable_unprepare(host->clk);
  333. if (host->domain) {
  334. put_iova_domain(&host->iova);
  335. iommu_detach_group(host->domain, host->group);
  336. iommu_domain_free(host->domain);
  337. iova_cache_put();
  338. iommu_group_put(host->group);
  339. }
  340. return 0;
  341. }
  342. static struct platform_driver tegra_host1x_driver = {
  343. .driver = {
  344. .name = "tegra-host1x",
  345. .of_match_table = host1x_of_match,
  346. },
  347. .probe = host1x_probe,
  348. .remove = host1x_remove,
  349. };
  350. static struct platform_driver * const drivers[] = {
  351. &tegra_host1x_driver,
  352. &tegra_mipi_driver,
  353. };
  354. static int __init tegra_host1x_init(void)
  355. {
  356. int err;
  357. err = bus_register(&host1x_bus_type);
  358. if (err < 0)
  359. return err;
  360. err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
  361. if (err < 0)
  362. bus_unregister(&host1x_bus_type);
  363. return err;
  364. }
  365. module_init(tegra_host1x_init);
  366. static void __exit tegra_host1x_exit(void)
  367. {
  368. platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
  369. bus_unregister(&host1x_bus_type);
  370. }
  371. module_exit(tegra_host1x_exit);
  372. MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
  373. MODULE_AUTHOR("Terje Bergstrom <tbergstrom@nvidia.com>");
  374. MODULE_DESCRIPTION("Host1x driver for Tegra products");
  375. MODULE_LICENSE("GPL");