talitos.h 15 KB

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  1. /* SPDX-License-Identifier: BSD-3-Clause */
  2. /*
  3. * Freescale SEC (talitos) device register and descriptor header defines
  4. *
  5. * Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
  6. */
  7. #define TALITOS_TIMEOUT 100000
  8. #define TALITOS1_MAX_DATA_LEN 32768
  9. #define TALITOS2_MAX_DATA_LEN 65535
  10. #define DESC_TYPE(desc_hdr) ((be32_to_cpu(desc_hdr) >> 3) & 0x1f)
  11. #define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf)
  12. #define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf)
  13. /* descriptor pointer entry */
  14. struct talitos_ptr {
  15. union {
  16. struct { /* SEC2 format */
  17. __be16 len; /* length */
  18. u8 j_extent; /* jump to sg link table and/or extent*/
  19. u8 eptr; /* extended address */
  20. };
  21. struct { /* SEC1 format */
  22. __be16 res;
  23. __be16 len1; /* length */
  24. };
  25. };
  26. __be32 ptr; /* address */
  27. };
  28. /* descriptor */
  29. struct talitos_desc {
  30. __be32 hdr; /* header high bits */
  31. union {
  32. __be32 hdr_lo; /* header low bits */
  33. __be32 hdr1; /* header for SEC1 */
  34. };
  35. struct talitos_ptr ptr[7]; /* ptr/len pair array */
  36. __be32 next_desc; /* next descriptor (SEC1) */
  37. };
  38. #define TALITOS_DESC_SIZE (sizeof(struct talitos_desc) - sizeof(__be32))
  39. /*
  40. * talitos_edesc - s/w-extended descriptor
  41. * @src_nents: number of segments in input scatterlist
  42. * @dst_nents: number of segments in output scatterlist
  43. * @iv_dma: dma address of iv for checking continuity and link table
  44. * @dma_len: length of dma mapped link_tbl space
  45. * @dma_link_tbl: bus physical address of link_tbl/buf
  46. * @desc: h/w descriptor
  47. * @link_tbl: input and output h/w link tables (if {src,dst}_nents > 1) (SEC2)
  48. * @buf: input and output buffeur (if {src,dst}_nents > 1) (SEC1)
  49. *
  50. * if decrypting (with authcheck), or either one of src_nents or dst_nents
  51. * is greater than 1, an integrity check value is concatenated to the end
  52. * of link_tbl data
  53. */
  54. struct talitos_edesc {
  55. int src_nents;
  56. int dst_nents;
  57. dma_addr_t iv_dma;
  58. int dma_len;
  59. dma_addr_t dma_link_tbl;
  60. struct talitos_desc desc;
  61. union {
  62. struct talitos_ptr link_tbl[0];
  63. u8 buf[0];
  64. };
  65. };
  66. /**
  67. * talitos_request - descriptor submission request
  68. * @desc: descriptor pointer (kernel virtual)
  69. * @dma_desc: descriptor's physical bus address
  70. * @callback: whom to call when descriptor processing is done
  71. * @context: caller context (optional)
  72. */
  73. struct talitos_request {
  74. struct talitos_desc *desc;
  75. dma_addr_t dma_desc;
  76. void (*callback) (struct device *dev, struct talitos_desc *desc,
  77. void *context, int error);
  78. void *context;
  79. };
  80. /* per-channel fifo management */
  81. struct talitos_channel {
  82. void __iomem *reg;
  83. /* request fifo */
  84. struct talitos_request *fifo;
  85. /* number of requests pending in channel h/w fifo */
  86. atomic_t submit_count ____cacheline_aligned;
  87. /* request submission (head) lock */
  88. spinlock_t head_lock ____cacheline_aligned;
  89. /* index to next free descriptor request */
  90. int head;
  91. /* request release (tail) lock */
  92. spinlock_t tail_lock ____cacheline_aligned;
  93. /* index to next in-progress/done descriptor request */
  94. int tail;
  95. };
  96. struct talitos_private {
  97. struct device *dev;
  98. struct platform_device *ofdev;
  99. void __iomem *reg;
  100. void __iomem *reg_deu;
  101. void __iomem *reg_aesu;
  102. void __iomem *reg_mdeu;
  103. void __iomem *reg_afeu;
  104. void __iomem *reg_rngu;
  105. void __iomem *reg_pkeu;
  106. void __iomem *reg_keu;
  107. void __iomem *reg_crcu;
  108. int irq[2];
  109. /* SEC global registers lock */
  110. spinlock_t reg_lock ____cacheline_aligned;
  111. /* SEC version geometry (from device tree node) */
  112. unsigned int num_channels;
  113. unsigned int chfifo_len;
  114. unsigned int exec_units;
  115. unsigned int desc_types;
  116. /* SEC Compatibility info */
  117. unsigned long features;
  118. /*
  119. * length of the request fifo
  120. * fifo_len is chfifo_len rounded up to next power of 2
  121. * so we can use bitwise ops to wrap
  122. */
  123. unsigned int fifo_len;
  124. struct talitos_channel *chan;
  125. /* next channel to be assigned next incoming descriptor */
  126. atomic_t last_chan ____cacheline_aligned;
  127. /* request callback tasklet */
  128. struct tasklet_struct done_task[2];
  129. /* list of registered algorithms */
  130. struct list_head alg_list;
  131. /* hwrng device */
  132. struct hwrng rng;
  133. bool rng_registered;
  134. };
  135. /* .features flag */
  136. #define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001
  137. #define TALITOS_FTR_HW_AUTH_CHECK 0x00000002
  138. #define TALITOS_FTR_SHA224_HWINIT 0x00000004
  139. #define TALITOS_FTR_HMAC_OK 0x00000008
  140. #define TALITOS_FTR_SEC1 0x00000010
  141. /*
  142. * If both CONFIG_CRYPTO_DEV_TALITOS1 and CONFIG_CRYPTO_DEV_TALITOS2 are
  143. * defined, we check the features which are set according to the device tree.
  144. * Otherwise, we answer true or false directly
  145. */
  146. static inline bool has_ftr_sec1(struct talitos_private *priv)
  147. {
  148. if (IS_ENABLED(CONFIG_CRYPTO_DEV_TALITOS1) &&
  149. IS_ENABLED(CONFIG_CRYPTO_DEV_TALITOS2))
  150. return priv->features & TALITOS_FTR_SEC1;
  151. return IS_ENABLED(CONFIG_CRYPTO_DEV_TALITOS1);
  152. }
  153. /*
  154. * TALITOS_xxx_LO addresses point to the low data bits (32-63) of the register
  155. */
  156. #define ISR1_FORMAT(x) (((x) << 28) | ((x) << 16))
  157. #define ISR2_FORMAT(x) (((x) << 4) | (x))
  158. /* global register offset addresses */
  159. #define TALITOS_MCR 0x1030 /* master control register */
  160. #define TALITOS_MCR_RCA0 (1 << 15) /* remap channel 0 */
  161. #define TALITOS_MCR_RCA1 (1 << 14) /* remap channel 1 */
  162. #define TALITOS_MCR_RCA2 (1 << 13) /* remap channel 2 */
  163. #define TALITOS_MCR_RCA3 (1 << 12) /* remap channel 3 */
  164. #define TALITOS1_MCR_SWR 0x1000000 /* s/w reset */
  165. #define TALITOS2_MCR_SWR 0x1 /* s/w reset */
  166. #define TALITOS_MCR_LO 0x1034
  167. #define TALITOS_IMR 0x1008 /* interrupt mask register */
  168. /* enable channel IRQs */
  169. #define TALITOS1_IMR_INIT ISR1_FORMAT(0xf)
  170. #define TALITOS1_IMR_DONE ISR1_FORMAT(0x5) /* done IRQs */
  171. /* enable channel IRQs */
  172. #define TALITOS2_IMR_INIT (ISR2_FORMAT(0xf) | 0x10000)
  173. #define TALITOS2_IMR_DONE ISR1_FORMAT(0x5) /* done IRQs */
  174. #define TALITOS_IMR_LO 0x100C
  175. #define TALITOS1_IMR_LO_INIT 0x2000000 /* allow RNGU error IRQs */
  176. #define TALITOS2_IMR_LO_INIT 0x20000 /* allow RNGU error IRQs */
  177. #define TALITOS_ISR 0x1010 /* interrupt status register */
  178. #define TALITOS1_ISR_4CHERR ISR1_FORMAT(0xa) /* 4 ch errors mask */
  179. #define TALITOS1_ISR_4CHDONE ISR1_FORMAT(0x5) /* 4 ch done mask */
  180. #define TALITOS1_ISR_CH_0_ERR (2 << 28) /* ch 0 errors mask */
  181. #define TALITOS1_ISR_CH_0_DONE (1 << 28) /* ch 0 done mask */
  182. #define TALITOS1_ISR_TEA_ERR 0x00000040
  183. #define TALITOS2_ISR_4CHERR ISR2_FORMAT(0xa) /* 4 ch errors mask */
  184. #define TALITOS2_ISR_4CHDONE ISR2_FORMAT(0x5) /* 4 ch done mask */
  185. #define TALITOS2_ISR_CH_0_ERR 2 /* ch 0 errors mask */
  186. #define TALITOS2_ISR_CH_0_DONE 1 /* ch 0 done mask */
  187. #define TALITOS2_ISR_CH_0_2_ERR ISR2_FORMAT(0x2) /* ch 0, 2 err mask */
  188. #define TALITOS2_ISR_CH_0_2_DONE ISR2_FORMAT(0x1) /* ch 0, 2 done mask */
  189. #define TALITOS2_ISR_CH_1_3_ERR ISR2_FORMAT(0x8) /* ch 1, 3 err mask */
  190. #define TALITOS2_ISR_CH_1_3_DONE ISR2_FORMAT(0x4) /* ch 1, 3 done mask */
  191. #define TALITOS_ISR_LO 0x1014
  192. #define TALITOS_ICR 0x1018 /* interrupt clear register */
  193. #define TALITOS_ICR_LO 0x101C
  194. /* channel register address stride */
  195. #define TALITOS_CH_BASE_OFFSET 0x1000 /* default channel map base */
  196. #define TALITOS1_CH_STRIDE 0x1000
  197. #define TALITOS2_CH_STRIDE 0x100
  198. /* channel configuration register */
  199. #define TALITOS_CCCR 0x8
  200. #define TALITOS2_CCCR_CONT 0x2 /* channel continue on SEC2 */
  201. #define TALITOS2_CCCR_RESET 0x1 /* channel reset on SEC2 */
  202. #define TALITOS_CCCR_LO 0xc
  203. #define TALITOS_CCCR_LO_IWSE 0x80 /* chan. ICCR writeback enab. */
  204. #define TALITOS_CCCR_LO_EAE 0x20 /* extended address enable */
  205. #define TALITOS_CCCR_LO_CDWE 0x10 /* chan. done writeback enab. */
  206. #define TALITOS_CCCR_LO_NE 0x8 /* fetch next descriptor enab. */
  207. #define TALITOS_CCCR_LO_NT 0x4 /* notification type */
  208. #define TALITOS_CCCR_LO_CDIE 0x2 /* channel done IRQ enable */
  209. #define TALITOS1_CCCR_LO_RESET 0x1 /* channel reset on SEC1 */
  210. /* CCPSR: channel pointer status register */
  211. #define TALITOS_CCPSR 0x10
  212. #define TALITOS_CCPSR_LO 0x14
  213. #define TALITOS_CCPSR_LO_DOF 0x8000 /* double FF write oflow error */
  214. #define TALITOS_CCPSR_LO_SOF 0x4000 /* single FF write oflow error */
  215. #define TALITOS_CCPSR_LO_MDTE 0x2000 /* master data transfer error */
  216. #define TALITOS_CCPSR_LO_SGDLZ 0x1000 /* s/g data len zero error */
  217. #define TALITOS_CCPSR_LO_FPZ 0x0800 /* fetch ptr zero error */
  218. #define TALITOS_CCPSR_LO_IDH 0x0400 /* illegal desc hdr error */
  219. #define TALITOS_CCPSR_LO_IEU 0x0200 /* invalid EU error */
  220. #define TALITOS_CCPSR_LO_EU 0x0100 /* EU error detected */
  221. #define TALITOS_CCPSR_LO_GB 0x0080 /* gather boundary error */
  222. #define TALITOS_CCPSR_LO_GRL 0x0040 /* gather return/length error */
  223. #define TALITOS_CCPSR_LO_SB 0x0020 /* scatter boundary error */
  224. #define TALITOS_CCPSR_LO_SRL 0x0010 /* scatter return/length error */
  225. /* channel fetch fifo register */
  226. #define TALITOS_FF 0x48
  227. #define TALITOS_FF_LO 0x4c
  228. /* current descriptor pointer register */
  229. #define TALITOS_CDPR 0x40
  230. #define TALITOS_CDPR_LO 0x44
  231. /* descriptor buffer register */
  232. #define TALITOS_DESCBUF 0x80
  233. #define TALITOS_DESCBUF_LO 0x84
  234. /* gather link table */
  235. #define TALITOS_GATHER 0xc0
  236. #define TALITOS_GATHER_LO 0xc4
  237. /* scatter link table */
  238. #define TALITOS_SCATTER 0xe0
  239. #define TALITOS_SCATTER_LO 0xe4
  240. /* execution unit registers base */
  241. #define TALITOS2_DEU 0x2000
  242. #define TALITOS2_AESU 0x4000
  243. #define TALITOS2_MDEU 0x6000
  244. #define TALITOS2_AFEU 0x8000
  245. #define TALITOS2_RNGU 0xa000
  246. #define TALITOS2_PKEU 0xc000
  247. #define TALITOS2_KEU 0xe000
  248. #define TALITOS2_CRCU 0xf000
  249. #define TALITOS12_AESU 0x4000
  250. #define TALITOS12_DEU 0x5000
  251. #define TALITOS12_MDEU 0x6000
  252. #define TALITOS10_AFEU 0x8000
  253. #define TALITOS10_DEU 0xa000
  254. #define TALITOS10_MDEU 0xc000
  255. #define TALITOS10_RNGU 0xe000
  256. #define TALITOS10_PKEU 0x10000
  257. #define TALITOS10_AESU 0x12000
  258. /* execution unit interrupt status registers */
  259. #define TALITOS_EUDSR 0x10 /* data size */
  260. #define TALITOS_EUDSR_LO 0x14
  261. #define TALITOS_EURCR 0x18 /* reset control*/
  262. #define TALITOS_EURCR_LO 0x1c
  263. #define TALITOS_EUSR 0x28 /* rng status */
  264. #define TALITOS_EUSR_LO 0x2c
  265. #define TALITOS_EUISR 0x30
  266. #define TALITOS_EUISR_LO 0x34
  267. #define TALITOS_EUICR 0x38 /* int. control */
  268. #define TALITOS_EUICR_LO 0x3c
  269. #define TALITOS_EU_FIFO 0x800 /* output FIFO */
  270. #define TALITOS_EU_FIFO_LO 0x804 /* output FIFO */
  271. /* DES unit */
  272. #define TALITOS1_DEUICR_KPE 0x00200000 /* Key Parity Error */
  273. /* message digest unit */
  274. #define TALITOS_MDEUICR_LO_ICE 0x4000 /* integrity check IRQ enable */
  275. /* random number unit */
  276. #define TALITOS_RNGUSR_LO_RD 0x1 /* reset done */
  277. #define TALITOS_RNGUSR_LO_OFL 0xff0000/* output FIFO length */
  278. #define TALITOS_RNGURCR_LO_SR 0x1 /* software reset */
  279. #define TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256 0x28
  280. #define TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512 0x48
  281. /*
  282. * talitos descriptor header (hdr) bits
  283. */
  284. /* written back when done */
  285. #define DESC_HDR_DONE cpu_to_be32(0xff000000)
  286. #define DESC_HDR_LO_ICCR1_MASK cpu_to_be32(0x00180000)
  287. #define DESC_HDR_LO_ICCR1_PASS cpu_to_be32(0x00080000)
  288. #define DESC_HDR_LO_ICCR1_FAIL cpu_to_be32(0x00100000)
  289. /* primary execution unit select */
  290. #define DESC_HDR_SEL0_MASK cpu_to_be32(0xf0000000)
  291. #define DESC_HDR_SEL0_AFEU cpu_to_be32(0x10000000)
  292. #define DESC_HDR_SEL0_DEU cpu_to_be32(0x20000000)
  293. #define DESC_HDR_SEL0_MDEUA cpu_to_be32(0x30000000)
  294. #define DESC_HDR_SEL0_MDEUB cpu_to_be32(0xb0000000)
  295. #define DESC_HDR_SEL0_RNG cpu_to_be32(0x40000000)
  296. #define DESC_HDR_SEL0_PKEU cpu_to_be32(0x50000000)
  297. #define DESC_HDR_SEL0_AESU cpu_to_be32(0x60000000)
  298. #define DESC_HDR_SEL0_KEU cpu_to_be32(0x70000000)
  299. #define DESC_HDR_SEL0_CRCU cpu_to_be32(0x80000000)
  300. /* primary execution unit mode (MODE0) and derivatives */
  301. #define DESC_HDR_MODE0_ENCRYPT cpu_to_be32(0x00100000)
  302. #define DESC_HDR_MODE0_AESU_MASK cpu_to_be32(0x00600000)
  303. #define DESC_HDR_MODE0_AESU_CBC cpu_to_be32(0x00200000)
  304. #define DESC_HDR_MODE0_AESU_CTR cpu_to_be32(0x00600000)
  305. #define DESC_HDR_MODE0_DEU_CBC cpu_to_be32(0x00400000)
  306. #define DESC_HDR_MODE0_DEU_3DES cpu_to_be32(0x00200000)
  307. #define DESC_HDR_MODE0_MDEU_CONT cpu_to_be32(0x08000000)
  308. #define DESC_HDR_MODE0_MDEU_INIT cpu_to_be32(0x01000000)
  309. #define DESC_HDR_MODE0_MDEU_HMAC cpu_to_be32(0x00800000)
  310. #define DESC_HDR_MODE0_MDEU_PAD cpu_to_be32(0x00400000)
  311. #define DESC_HDR_MODE0_MDEU_SHA224 cpu_to_be32(0x00300000)
  312. #define DESC_HDR_MODE0_MDEU_MD5 cpu_to_be32(0x00200000)
  313. #define DESC_HDR_MODE0_MDEU_SHA256 cpu_to_be32(0x00100000)
  314. #define DESC_HDR_MODE0_MDEU_SHA1 cpu_to_be32(0x00000000)
  315. #define DESC_HDR_MODE0_MDEUB_SHA384 cpu_to_be32(0x00000000)
  316. #define DESC_HDR_MODE0_MDEUB_SHA512 cpu_to_be32(0x00200000)
  317. #define DESC_HDR_MODE0_MDEU_MD5_HMAC (DESC_HDR_MODE0_MDEU_MD5 | \
  318. DESC_HDR_MODE0_MDEU_HMAC)
  319. #define DESC_HDR_MODE0_MDEU_SHA256_HMAC (DESC_HDR_MODE0_MDEU_SHA256 | \
  320. DESC_HDR_MODE0_MDEU_HMAC)
  321. #define DESC_HDR_MODE0_MDEU_SHA1_HMAC (DESC_HDR_MODE0_MDEU_SHA1 | \
  322. DESC_HDR_MODE0_MDEU_HMAC)
  323. /* secondary execution unit select (SEL1) */
  324. #define DESC_HDR_SEL1_MASK cpu_to_be32(0x000f0000)
  325. #define DESC_HDR_SEL1_MDEUA cpu_to_be32(0x00030000)
  326. #define DESC_HDR_SEL1_MDEUB cpu_to_be32(0x000b0000)
  327. #define DESC_HDR_SEL1_CRCU cpu_to_be32(0x00080000)
  328. /* secondary execution unit mode (MODE1) and derivatives */
  329. #define DESC_HDR_MODE1_MDEU_CICV cpu_to_be32(0x00004000)
  330. #define DESC_HDR_MODE1_MDEU_INIT cpu_to_be32(0x00001000)
  331. #define DESC_HDR_MODE1_MDEU_HMAC cpu_to_be32(0x00000800)
  332. #define DESC_HDR_MODE1_MDEU_PAD cpu_to_be32(0x00000400)
  333. #define DESC_HDR_MODE1_MDEU_SHA224 cpu_to_be32(0x00000300)
  334. #define DESC_HDR_MODE1_MDEU_MD5 cpu_to_be32(0x00000200)
  335. #define DESC_HDR_MODE1_MDEU_SHA256 cpu_to_be32(0x00000100)
  336. #define DESC_HDR_MODE1_MDEU_SHA1 cpu_to_be32(0x00000000)
  337. #define DESC_HDR_MODE1_MDEUB_SHA384 cpu_to_be32(0x00000000)
  338. #define DESC_HDR_MODE1_MDEUB_SHA512 cpu_to_be32(0x00000200)
  339. #define DESC_HDR_MODE1_MDEU_MD5_HMAC (DESC_HDR_MODE1_MDEU_MD5 | \
  340. DESC_HDR_MODE1_MDEU_HMAC)
  341. #define DESC_HDR_MODE1_MDEU_SHA256_HMAC (DESC_HDR_MODE1_MDEU_SHA256 | \
  342. DESC_HDR_MODE1_MDEU_HMAC)
  343. #define DESC_HDR_MODE1_MDEU_SHA1_HMAC (DESC_HDR_MODE1_MDEU_SHA1 | \
  344. DESC_HDR_MODE1_MDEU_HMAC)
  345. #define DESC_HDR_MODE1_MDEU_SHA224_HMAC (DESC_HDR_MODE1_MDEU_SHA224 | \
  346. DESC_HDR_MODE1_MDEU_HMAC)
  347. #define DESC_HDR_MODE1_MDEUB_SHA384_HMAC (DESC_HDR_MODE1_MDEUB_SHA384 | \
  348. DESC_HDR_MODE1_MDEU_HMAC)
  349. #define DESC_HDR_MODE1_MDEUB_SHA512_HMAC (DESC_HDR_MODE1_MDEUB_SHA512 | \
  350. DESC_HDR_MODE1_MDEU_HMAC)
  351. /* direction of overall data flow (DIR) */
  352. #define DESC_HDR_DIR_INBOUND cpu_to_be32(0x00000002)
  353. /* request done notification (DN) */
  354. #define DESC_HDR_DONE_NOTIFY cpu_to_be32(0x00000001)
  355. /* descriptor types */
  356. #define DESC_HDR_TYPE_AESU_CTR_NONSNOOP cpu_to_be32(0 << 3)
  357. #define DESC_HDR_TYPE_IPSEC_ESP cpu_to_be32(1 << 3)
  358. #define DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU cpu_to_be32(2 << 3)
  359. #define DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU cpu_to_be32(4 << 3)
  360. /* link table extent field bits */
  361. #define DESC_PTR_LNKTBL_JUMP 0x80
  362. #define DESC_PTR_LNKTBL_RET 0x02
  363. #define DESC_PTR_LNKTBL_NEXT 0x01