qi.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * CAAM/SEC 4.x QI transport/backend driver
  4. * Queue Interface backend functionality
  5. *
  6. * Copyright 2013-2016 Freescale Semiconductor, Inc.
  7. * Copyright 2016-2017, 2019 NXP
  8. */
  9. #include <linux/cpumask.h>
  10. #include <linux/kthread.h>
  11. #include <soc/fsl/qman.h>
  12. #include "regs.h"
  13. #include "qi.h"
  14. #include "desc.h"
  15. #include "intern.h"
  16. #include "desc_constr.h"
  17. #define PREHDR_RSLS_SHIFT 31
  18. #define PREHDR_ABS BIT(25)
  19. /*
  20. * Use a reasonable backlog of frames (per CPU) as congestion threshold,
  21. * so that resources used by the in-flight buffers do not become a memory hog.
  22. */
  23. #define MAX_RSP_FQ_BACKLOG_PER_CPU 256
  24. #define CAAM_QI_ENQUEUE_RETRIES 10000
  25. #define CAAM_NAPI_WEIGHT 63
  26. /*
  27. * caam_napi - struct holding CAAM NAPI-related params
  28. * @irqtask: IRQ task for QI backend
  29. * @p: QMan portal
  30. */
  31. struct caam_napi {
  32. struct napi_struct irqtask;
  33. struct qman_portal *p;
  34. };
  35. /*
  36. * caam_qi_pcpu_priv - percpu private data structure to main list of pending
  37. * responses expected on each cpu.
  38. * @caam_napi: CAAM NAPI params
  39. * @net_dev: netdev used by NAPI
  40. * @rsp_fq: response FQ from CAAM
  41. */
  42. struct caam_qi_pcpu_priv {
  43. struct caam_napi caam_napi;
  44. struct net_device net_dev;
  45. struct qman_fq *rsp_fq;
  46. } ____cacheline_aligned;
  47. static DEFINE_PER_CPU(struct caam_qi_pcpu_priv, pcpu_qipriv);
  48. static DEFINE_PER_CPU(int, last_cpu);
  49. /*
  50. * caam_qi_priv - CAAM QI backend private params
  51. * @cgr: QMan congestion group
  52. */
  53. struct caam_qi_priv {
  54. struct qman_cgr cgr;
  55. };
  56. static struct caam_qi_priv qipriv ____cacheline_aligned;
  57. /*
  58. * This is written by only one core - the one that initialized the CGR - and
  59. * read by multiple cores (all the others).
  60. */
  61. bool caam_congested __read_mostly;
  62. EXPORT_SYMBOL(caam_congested);
  63. #ifdef CONFIG_DEBUG_FS
  64. /*
  65. * This is a counter for the number of times the congestion group (where all
  66. * the request and response queueus are) reached congestion. Incremented
  67. * each time the congestion callback is called with congested == true.
  68. */
  69. static u64 times_congested;
  70. #endif
  71. /*
  72. * This is a a cache of buffers, from which the users of CAAM QI driver
  73. * can allocate short (CAAM_QI_MEMCACHE_SIZE) buffers. It's faster than
  74. * doing malloc on the hotpath.
  75. * NOTE: A more elegant solution would be to have some headroom in the frames
  76. * being processed. This could be added by the dpaa-ethernet driver.
  77. * This would pose a problem for userspace application processing which
  78. * cannot know of this limitation. So for now, this will work.
  79. * NOTE: The memcache is SMP-safe. No need to handle spinlocks in-here
  80. */
  81. static struct kmem_cache *qi_cache;
  82. static void *caam_iova_to_virt(struct iommu_domain *domain,
  83. dma_addr_t iova_addr)
  84. {
  85. phys_addr_t phys_addr;
  86. phys_addr = domain ? iommu_iova_to_phys(domain, iova_addr) : iova_addr;
  87. return phys_to_virt(phys_addr);
  88. }
  89. int caam_qi_enqueue(struct device *qidev, struct caam_drv_req *req)
  90. {
  91. struct qm_fd fd;
  92. dma_addr_t addr;
  93. int ret;
  94. int num_retries = 0;
  95. qm_fd_clear_fd(&fd);
  96. qm_fd_set_compound(&fd, qm_sg_entry_get_len(&req->fd_sgt[1]));
  97. addr = dma_map_single(qidev, req->fd_sgt, sizeof(req->fd_sgt),
  98. DMA_BIDIRECTIONAL);
  99. if (dma_mapping_error(qidev, addr)) {
  100. dev_err(qidev, "DMA mapping error for QI enqueue request\n");
  101. return -EIO;
  102. }
  103. qm_fd_addr_set64(&fd, addr);
  104. do {
  105. ret = qman_enqueue(req->drv_ctx->req_fq, &fd);
  106. if (likely(!ret))
  107. return 0;
  108. if (ret != -EBUSY)
  109. break;
  110. num_retries++;
  111. } while (num_retries < CAAM_QI_ENQUEUE_RETRIES);
  112. dev_err(qidev, "qman_enqueue failed: %d\n", ret);
  113. return ret;
  114. }
  115. EXPORT_SYMBOL(caam_qi_enqueue);
  116. static void caam_fq_ern_cb(struct qman_portal *qm, struct qman_fq *fq,
  117. const union qm_mr_entry *msg)
  118. {
  119. const struct qm_fd *fd;
  120. struct caam_drv_req *drv_req;
  121. struct device *qidev = &(raw_cpu_ptr(&pcpu_qipriv)->net_dev.dev);
  122. struct caam_drv_private *priv = dev_get_drvdata(qidev);
  123. fd = &msg->ern.fd;
  124. if (qm_fd_get_format(fd) != qm_fd_compound) {
  125. dev_err(qidev, "Non-compound FD from CAAM\n");
  126. return;
  127. }
  128. drv_req = caam_iova_to_virt(priv->domain, qm_fd_addr_get64(fd));
  129. if (!drv_req) {
  130. dev_err(qidev,
  131. "Can't find original request for CAAM response\n");
  132. return;
  133. }
  134. dma_unmap_single(drv_req->drv_ctx->qidev, qm_fd_addr(fd),
  135. sizeof(drv_req->fd_sgt), DMA_BIDIRECTIONAL);
  136. if (fd->status)
  137. drv_req->cbk(drv_req, be32_to_cpu(fd->status));
  138. else
  139. drv_req->cbk(drv_req, JRSTA_SSRC_QI);
  140. }
  141. static struct qman_fq *create_caam_req_fq(struct device *qidev,
  142. struct qman_fq *rsp_fq,
  143. dma_addr_t hwdesc,
  144. int fq_sched_flag)
  145. {
  146. int ret;
  147. struct qman_fq *req_fq;
  148. struct qm_mcc_initfq opts;
  149. req_fq = kzalloc(sizeof(*req_fq), GFP_ATOMIC);
  150. if (!req_fq)
  151. return ERR_PTR(-ENOMEM);
  152. req_fq->cb.ern = caam_fq_ern_cb;
  153. req_fq->cb.fqs = NULL;
  154. ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
  155. QMAN_FQ_FLAG_TO_DCPORTAL, req_fq);
  156. if (ret) {
  157. dev_err(qidev, "Failed to create session req FQ\n");
  158. goto create_req_fq_fail;
  159. }
  160. memset(&opts, 0, sizeof(opts));
  161. opts.we_mask = cpu_to_be16(QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_DESTWQ |
  162. QM_INITFQ_WE_CONTEXTB |
  163. QM_INITFQ_WE_CONTEXTA | QM_INITFQ_WE_CGID);
  164. opts.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_CPCSTASH | QM_FQCTRL_CGE);
  165. qm_fqd_set_destwq(&opts.fqd, qm_channel_caam, 2);
  166. opts.fqd.context_b = cpu_to_be32(qman_fq_fqid(rsp_fq));
  167. qm_fqd_context_a_set64(&opts.fqd, hwdesc);
  168. opts.fqd.cgid = qipriv.cgr.cgrid;
  169. ret = qman_init_fq(req_fq, fq_sched_flag, &opts);
  170. if (ret) {
  171. dev_err(qidev, "Failed to init session req FQ\n");
  172. goto init_req_fq_fail;
  173. }
  174. dev_dbg(qidev, "Allocated request FQ %u for CPU %u\n", req_fq->fqid,
  175. smp_processor_id());
  176. return req_fq;
  177. init_req_fq_fail:
  178. qman_destroy_fq(req_fq);
  179. create_req_fq_fail:
  180. kfree(req_fq);
  181. return ERR_PTR(ret);
  182. }
  183. static int empty_retired_fq(struct device *qidev, struct qman_fq *fq)
  184. {
  185. int ret;
  186. ret = qman_volatile_dequeue(fq, QMAN_VOLATILE_FLAG_WAIT_INT |
  187. QMAN_VOLATILE_FLAG_FINISH,
  188. QM_VDQCR_PRECEDENCE_VDQCR |
  189. QM_VDQCR_NUMFRAMES_TILLEMPTY);
  190. if (ret) {
  191. dev_err(qidev, "Volatile dequeue fail for FQ: %u\n", fq->fqid);
  192. return ret;
  193. }
  194. do {
  195. struct qman_portal *p;
  196. p = qman_get_affine_portal(smp_processor_id());
  197. qman_p_poll_dqrr(p, 16);
  198. } while (fq->flags & QMAN_FQ_STATE_NE);
  199. return 0;
  200. }
  201. static int kill_fq(struct device *qidev, struct qman_fq *fq)
  202. {
  203. u32 flags;
  204. int ret;
  205. ret = qman_retire_fq(fq, &flags);
  206. if (ret < 0) {
  207. dev_err(qidev, "qman_retire_fq failed: %d\n", ret);
  208. return ret;
  209. }
  210. if (!ret)
  211. goto empty_fq;
  212. /* Async FQ retirement condition */
  213. if (ret == 1) {
  214. /* Retry till FQ gets in retired state */
  215. do {
  216. msleep(20);
  217. } while (fq->state != qman_fq_state_retired);
  218. WARN_ON(fq->flags & QMAN_FQ_STATE_BLOCKOOS);
  219. WARN_ON(fq->flags & QMAN_FQ_STATE_ORL);
  220. }
  221. empty_fq:
  222. if (fq->flags & QMAN_FQ_STATE_NE) {
  223. ret = empty_retired_fq(qidev, fq);
  224. if (ret) {
  225. dev_err(qidev, "empty_retired_fq fail for FQ: %u\n",
  226. fq->fqid);
  227. return ret;
  228. }
  229. }
  230. ret = qman_oos_fq(fq);
  231. if (ret)
  232. dev_err(qidev, "OOS of FQID: %u failed\n", fq->fqid);
  233. qman_destroy_fq(fq);
  234. kfree(fq);
  235. return ret;
  236. }
  237. static int empty_caam_fq(struct qman_fq *fq)
  238. {
  239. int ret;
  240. struct qm_mcr_queryfq_np np;
  241. /* Wait till the older CAAM FQ get empty */
  242. do {
  243. ret = qman_query_fq_np(fq, &np);
  244. if (ret)
  245. return ret;
  246. if (!qm_mcr_np_get(&np, frm_cnt))
  247. break;
  248. msleep(20);
  249. } while (1);
  250. /*
  251. * Give extra time for pending jobs from this FQ in holding tanks
  252. * to get processed
  253. */
  254. msleep(20);
  255. return 0;
  256. }
  257. int caam_drv_ctx_update(struct caam_drv_ctx *drv_ctx, u32 *sh_desc)
  258. {
  259. int ret;
  260. u32 num_words;
  261. struct qman_fq *new_fq, *old_fq;
  262. struct device *qidev = drv_ctx->qidev;
  263. num_words = desc_len(sh_desc);
  264. if (num_words > MAX_SDLEN) {
  265. dev_err(qidev, "Invalid descriptor len: %d words\n", num_words);
  266. return -EINVAL;
  267. }
  268. /* Note down older req FQ */
  269. old_fq = drv_ctx->req_fq;
  270. /* Create a new req FQ in parked state */
  271. new_fq = create_caam_req_fq(drv_ctx->qidev, drv_ctx->rsp_fq,
  272. drv_ctx->context_a, 0);
  273. if (IS_ERR(new_fq)) {
  274. dev_err(qidev, "FQ allocation for shdesc update failed\n");
  275. return PTR_ERR(new_fq);
  276. }
  277. /* Hook up new FQ to context so that new requests keep queuing */
  278. drv_ctx->req_fq = new_fq;
  279. /* Empty and remove the older FQ */
  280. ret = empty_caam_fq(old_fq);
  281. if (ret) {
  282. dev_err(qidev, "Old CAAM FQ empty failed: %d\n", ret);
  283. /* We can revert to older FQ */
  284. drv_ctx->req_fq = old_fq;
  285. if (kill_fq(qidev, new_fq))
  286. dev_warn(qidev, "New CAAM FQ kill failed\n");
  287. return ret;
  288. }
  289. /*
  290. * Re-initialise pre-header. Set RSLS and SDLEN.
  291. * Update the shared descriptor for driver context.
  292. */
  293. drv_ctx->prehdr[0] = cpu_to_caam32((1 << PREHDR_RSLS_SHIFT) |
  294. num_words);
  295. drv_ctx->prehdr[1] = cpu_to_caam32(PREHDR_ABS);
  296. memcpy(drv_ctx->sh_desc, sh_desc, desc_bytes(sh_desc));
  297. dma_sync_single_for_device(qidev, drv_ctx->context_a,
  298. sizeof(drv_ctx->sh_desc) +
  299. sizeof(drv_ctx->prehdr),
  300. DMA_BIDIRECTIONAL);
  301. /* Put the new FQ in scheduled state */
  302. ret = qman_schedule_fq(new_fq);
  303. if (ret) {
  304. dev_err(qidev, "Fail to sched new CAAM FQ, ecode = %d\n", ret);
  305. /*
  306. * We can kill new FQ and revert to old FQ.
  307. * Since the desc is already modified, it is success case
  308. */
  309. drv_ctx->req_fq = old_fq;
  310. if (kill_fq(qidev, new_fq))
  311. dev_warn(qidev, "New CAAM FQ kill failed\n");
  312. } else if (kill_fq(qidev, old_fq)) {
  313. dev_warn(qidev, "Old CAAM FQ kill failed\n");
  314. }
  315. return 0;
  316. }
  317. EXPORT_SYMBOL(caam_drv_ctx_update);
  318. struct caam_drv_ctx *caam_drv_ctx_init(struct device *qidev,
  319. int *cpu,
  320. u32 *sh_desc)
  321. {
  322. size_t size;
  323. u32 num_words;
  324. dma_addr_t hwdesc;
  325. struct caam_drv_ctx *drv_ctx;
  326. const cpumask_t *cpus = qman_affine_cpus();
  327. num_words = desc_len(sh_desc);
  328. if (num_words > MAX_SDLEN) {
  329. dev_err(qidev, "Invalid descriptor len: %d words\n",
  330. num_words);
  331. return ERR_PTR(-EINVAL);
  332. }
  333. drv_ctx = kzalloc(sizeof(*drv_ctx), GFP_ATOMIC);
  334. if (!drv_ctx)
  335. return ERR_PTR(-ENOMEM);
  336. /*
  337. * Initialise pre-header - set RSLS and SDLEN - and shared descriptor
  338. * and dma-map them.
  339. */
  340. drv_ctx->prehdr[0] = cpu_to_caam32((1 << PREHDR_RSLS_SHIFT) |
  341. num_words);
  342. drv_ctx->prehdr[1] = cpu_to_caam32(PREHDR_ABS);
  343. memcpy(drv_ctx->sh_desc, sh_desc, desc_bytes(sh_desc));
  344. size = sizeof(drv_ctx->prehdr) + sizeof(drv_ctx->sh_desc);
  345. hwdesc = dma_map_single(qidev, drv_ctx->prehdr, size,
  346. DMA_BIDIRECTIONAL);
  347. if (dma_mapping_error(qidev, hwdesc)) {
  348. dev_err(qidev, "DMA map error for preheader + shdesc\n");
  349. kfree(drv_ctx);
  350. return ERR_PTR(-ENOMEM);
  351. }
  352. drv_ctx->context_a = hwdesc;
  353. /* If given CPU does not own the portal, choose another one that does */
  354. if (!cpumask_test_cpu(*cpu, cpus)) {
  355. int *pcpu = &get_cpu_var(last_cpu);
  356. *pcpu = cpumask_next(*pcpu, cpus);
  357. if (*pcpu >= nr_cpu_ids)
  358. *pcpu = cpumask_first(cpus);
  359. *cpu = *pcpu;
  360. put_cpu_var(last_cpu);
  361. }
  362. drv_ctx->cpu = *cpu;
  363. /* Find response FQ hooked with this CPU */
  364. drv_ctx->rsp_fq = per_cpu(pcpu_qipriv.rsp_fq, drv_ctx->cpu);
  365. /* Attach request FQ */
  366. drv_ctx->req_fq = create_caam_req_fq(qidev, drv_ctx->rsp_fq, hwdesc,
  367. QMAN_INITFQ_FLAG_SCHED);
  368. if (IS_ERR(drv_ctx->req_fq)) {
  369. dev_err(qidev, "create_caam_req_fq failed\n");
  370. dma_unmap_single(qidev, hwdesc, size, DMA_BIDIRECTIONAL);
  371. kfree(drv_ctx);
  372. return ERR_PTR(-ENOMEM);
  373. }
  374. drv_ctx->qidev = qidev;
  375. return drv_ctx;
  376. }
  377. EXPORT_SYMBOL(caam_drv_ctx_init);
  378. void *qi_cache_alloc(gfp_t flags)
  379. {
  380. return kmem_cache_alloc(qi_cache, flags);
  381. }
  382. EXPORT_SYMBOL(qi_cache_alloc);
  383. void qi_cache_free(void *obj)
  384. {
  385. kmem_cache_free(qi_cache, obj);
  386. }
  387. EXPORT_SYMBOL(qi_cache_free);
  388. static int caam_qi_poll(struct napi_struct *napi, int budget)
  389. {
  390. struct caam_napi *np = container_of(napi, struct caam_napi, irqtask);
  391. int cleaned = qman_p_poll_dqrr(np->p, budget);
  392. if (cleaned < budget) {
  393. napi_complete(napi);
  394. qman_p_irqsource_add(np->p, QM_PIRQ_DQRI);
  395. }
  396. return cleaned;
  397. }
  398. void caam_drv_ctx_rel(struct caam_drv_ctx *drv_ctx)
  399. {
  400. if (IS_ERR_OR_NULL(drv_ctx))
  401. return;
  402. /* Remove request FQ */
  403. if (kill_fq(drv_ctx->qidev, drv_ctx->req_fq))
  404. dev_err(drv_ctx->qidev, "Crypto session req FQ kill failed\n");
  405. dma_unmap_single(drv_ctx->qidev, drv_ctx->context_a,
  406. sizeof(drv_ctx->sh_desc) + sizeof(drv_ctx->prehdr),
  407. DMA_BIDIRECTIONAL);
  408. kfree(drv_ctx);
  409. }
  410. EXPORT_SYMBOL(caam_drv_ctx_rel);
  411. void caam_qi_shutdown(struct device *qidev)
  412. {
  413. int i;
  414. struct caam_qi_priv *priv = &qipriv;
  415. const cpumask_t *cpus = qman_affine_cpus();
  416. for_each_cpu(i, cpus) {
  417. struct napi_struct *irqtask;
  418. irqtask = &per_cpu_ptr(&pcpu_qipriv.caam_napi, i)->irqtask;
  419. napi_disable(irqtask);
  420. netif_napi_del(irqtask);
  421. if (kill_fq(qidev, per_cpu(pcpu_qipriv.rsp_fq, i)))
  422. dev_err(qidev, "Rsp FQ kill failed, cpu: %d\n", i);
  423. }
  424. qman_delete_cgr_safe(&priv->cgr);
  425. qman_release_cgrid(priv->cgr.cgrid);
  426. kmem_cache_destroy(qi_cache);
  427. }
  428. static void cgr_cb(struct qman_portal *qm, struct qman_cgr *cgr, int congested)
  429. {
  430. caam_congested = congested;
  431. if (congested) {
  432. #ifdef CONFIG_DEBUG_FS
  433. times_congested++;
  434. #endif
  435. pr_debug_ratelimited("CAAM entered congestion\n");
  436. } else {
  437. pr_debug_ratelimited("CAAM exited congestion\n");
  438. }
  439. }
  440. static int caam_qi_napi_schedule(struct qman_portal *p, struct caam_napi *np)
  441. {
  442. /*
  443. * In case of threaded ISR, for RT kernels in_irq() does not return
  444. * appropriate value, so use in_serving_softirq to distinguish between
  445. * softirq and irq contexts.
  446. */
  447. if (unlikely(in_irq() || !in_serving_softirq())) {
  448. /* Disable QMan IRQ source and invoke NAPI */
  449. qman_p_irqsource_remove(p, QM_PIRQ_DQRI);
  450. np->p = p;
  451. napi_schedule(&np->irqtask);
  452. return 1;
  453. }
  454. return 0;
  455. }
  456. static enum qman_cb_dqrr_result caam_rsp_fq_dqrr_cb(struct qman_portal *p,
  457. struct qman_fq *rsp_fq,
  458. const struct qm_dqrr_entry *dqrr)
  459. {
  460. struct caam_napi *caam_napi = raw_cpu_ptr(&pcpu_qipriv.caam_napi);
  461. struct caam_drv_req *drv_req;
  462. const struct qm_fd *fd;
  463. struct device *qidev = &(raw_cpu_ptr(&pcpu_qipriv)->net_dev.dev);
  464. struct caam_drv_private *priv = dev_get_drvdata(qidev);
  465. u32 status;
  466. if (caam_qi_napi_schedule(p, caam_napi))
  467. return qman_cb_dqrr_stop;
  468. fd = &dqrr->fd;
  469. status = be32_to_cpu(fd->status);
  470. if (unlikely(status)) {
  471. u32 ssrc = status & JRSTA_SSRC_MASK;
  472. u8 err_id = status & JRSTA_CCBERR_ERRID_MASK;
  473. if (ssrc != JRSTA_SSRC_CCB_ERROR ||
  474. err_id != JRSTA_CCBERR_ERRID_ICVCHK)
  475. dev_err_ratelimited(qidev,
  476. "Error: %#x in CAAM response FD\n",
  477. status);
  478. }
  479. if (unlikely(qm_fd_get_format(fd) != qm_fd_compound)) {
  480. dev_err(qidev, "Non-compound FD from CAAM\n");
  481. return qman_cb_dqrr_consume;
  482. }
  483. drv_req = caam_iova_to_virt(priv->domain, qm_fd_addr_get64(fd));
  484. if (unlikely(!drv_req)) {
  485. dev_err(qidev,
  486. "Can't find original request for caam response\n");
  487. return qman_cb_dqrr_consume;
  488. }
  489. dma_unmap_single(drv_req->drv_ctx->qidev, qm_fd_addr(fd),
  490. sizeof(drv_req->fd_sgt), DMA_BIDIRECTIONAL);
  491. drv_req->cbk(drv_req, status);
  492. return qman_cb_dqrr_consume;
  493. }
  494. static int alloc_rsp_fq_cpu(struct device *qidev, unsigned int cpu)
  495. {
  496. struct qm_mcc_initfq opts;
  497. struct qman_fq *fq;
  498. int ret;
  499. fq = kzalloc(sizeof(*fq), GFP_KERNEL | GFP_DMA);
  500. if (!fq)
  501. return -ENOMEM;
  502. fq->cb.dqrr = caam_rsp_fq_dqrr_cb;
  503. ret = qman_create_fq(0, QMAN_FQ_FLAG_NO_ENQUEUE |
  504. QMAN_FQ_FLAG_DYNAMIC_FQID, fq);
  505. if (ret) {
  506. dev_err(qidev, "Rsp FQ create failed\n");
  507. kfree(fq);
  508. return -ENODEV;
  509. }
  510. memset(&opts, 0, sizeof(opts));
  511. opts.we_mask = cpu_to_be16(QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_DESTWQ |
  512. QM_INITFQ_WE_CONTEXTB |
  513. QM_INITFQ_WE_CONTEXTA | QM_INITFQ_WE_CGID);
  514. opts.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_CTXASTASHING |
  515. QM_FQCTRL_CPCSTASH | QM_FQCTRL_CGE);
  516. qm_fqd_set_destwq(&opts.fqd, qman_affine_channel(cpu), 3);
  517. opts.fqd.cgid = qipriv.cgr.cgrid;
  518. opts.fqd.context_a.stashing.exclusive = QM_STASHING_EXCL_CTX |
  519. QM_STASHING_EXCL_DATA;
  520. qm_fqd_set_stashing(&opts.fqd, 0, 1, 1);
  521. ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
  522. if (ret) {
  523. dev_err(qidev, "Rsp FQ init failed\n");
  524. kfree(fq);
  525. return -ENODEV;
  526. }
  527. per_cpu(pcpu_qipriv.rsp_fq, cpu) = fq;
  528. dev_dbg(qidev, "Allocated response FQ %u for CPU %u", fq->fqid, cpu);
  529. return 0;
  530. }
  531. static int init_cgr(struct device *qidev)
  532. {
  533. int ret;
  534. struct qm_mcc_initcgr opts;
  535. const u64 val = (u64)cpumask_weight(qman_affine_cpus()) *
  536. MAX_RSP_FQ_BACKLOG_PER_CPU;
  537. ret = qman_alloc_cgrid(&qipriv.cgr.cgrid);
  538. if (ret) {
  539. dev_err(qidev, "CGR alloc failed for rsp FQs: %d\n", ret);
  540. return ret;
  541. }
  542. qipriv.cgr.cb = cgr_cb;
  543. memset(&opts, 0, sizeof(opts));
  544. opts.we_mask = cpu_to_be16(QM_CGR_WE_CSCN_EN | QM_CGR_WE_CS_THRES |
  545. QM_CGR_WE_MODE);
  546. opts.cgr.cscn_en = QM_CGR_EN;
  547. opts.cgr.mode = QMAN_CGR_MODE_FRAME;
  548. qm_cgr_cs_thres_set64(&opts.cgr.cs_thres, val, 1);
  549. ret = qman_create_cgr(&qipriv.cgr, QMAN_CGR_FLAG_USE_INIT, &opts);
  550. if (ret) {
  551. dev_err(qidev, "Error %d creating CAAM CGRID: %u\n", ret,
  552. qipriv.cgr.cgrid);
  553. return ret;
  554. }
  555. dev_dbg(qidev, "Congestion threshold set to %llu\n", val);
  556. return 0;
  557. }
  558. static int alloc_rsp_fqs(struct device *qidev)
  559. {
  560. int ret, i;
  561. const cpumask_t *cpus = qman_affine_cpus();
  562. /*Now create response FQs*/
  563. for_each_cpu(i, cpus) {
  564. ret = alloc_rsp_fq_cpu(qidev, i);
  565. if (ret) {
  566. dev_err(qidev, "CAAM rsp FQ alloc failed, cpu: %u", i);
  567. return ret;
  568. }
  569. }
  570. return 0;
  571. }
  572. static void free_rsp_fqs(void)
  573. {
  574. int i;
  575. const cpumask_t *cpus = qman_affine_cpus();
  576. for_each_cpu(i, cpus)
  577. kfree(per_cpu(pcpu_qipriv.rsp_fq, i));
  578. }
  579. int caam_qi_init(struct platform_device *caam_pdev)
  580. {
  581. int err, i;
  582. struct device *ctrldev = &caam_pdev->dev, *qidev;
  583. struct caam_drv_private *ctrlpriv;
  584. const cpumask_t *cpus = qman_affine_cpus();
  585. ctrlpriv = dev_get_drvdata(ctrldev);
  586. qidev = ctrldev;
  587. /* Initialize the congestion detection */
  588. err = init_cgr(qidev);
  589. if (err) {
  590. dev_err(qidev, "CGR initialization failed: %d\n", err);
  591. return err;
  592. }
  593. /* Initialise response FQs */
  594. err = alloc_rsp_fqs(qidev);
  595. if (err) {
  596. dev_err(qidev, "Can't allocate CAAM response FQs: %d\n", err);
  597. free_rsp_fqs();
  598. return err;
  599. }
  600. /*
  601. * Enable the NAPI contexts on each of the core which has an affine
  602. * portal.
  603. */
  604. for_each_cpu(i, cpus) {
  605. struct caam_qi_pcpu_priv *priv = per_cpu_ptr(&pcpu_qipriv, i);
  606. struct caam_napi *caam_napi = &priv->caam_napi;
  607. struct napi_struct *irqtask = &caam_napi->irqtask;
  608. struct net_device *net_dev = &priv->net_dev;
  609. net_dev->dev = *qidev;
  610. INIT_LIST_HEAD(&net_dev->napi_list);
  611. netif_napi_add(net_dev, irqtask, caam_qi_poll,
  612. CAAM_NAPI_WEIGHT);
  613. napi_enable(irqtask);
  614. }
  615. qi_cache = kmem_cache_create("caamqicache", CAAM_QI_MEMCACHE_SIZE, 0,
  616. SLAB_CACHE_DMA, NULL);
  617. if (!qi_cache) {
  618. dev_err(qidev, "Can't allocate CAAM cache\n");
  619. free_rsp_fqs();
  620. return -ENOMEM;
  621. }
  622. #ifdef CONFIG_DEBUG_FS
  623. debugfs_create_file("qi_congested", 0444, ctrlpriv->ctl,
  624. &times_congested, &caam_fops_u64_ro);
  625. #endif
  626. ctrlpriv->qi_init = 1;
  627. dev_info(qidev, "Linux CAAM Queue I/F driver initialised\n");
  628. return 0;
  629. }