mvebu-mbus.c 36 KB

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  1. /*
  2. * Address map functions for Marvell EBU SoCs (Kirkwood, Armada
  3. * 370/XP, Dove, Orion5x and MV78xx0)
  4. *
  5. * This file is licensed under the terms of the GNU General Public
  6. * License version 2. This program is licensed "as is" without any
  7. * warranty of any kind, whether express or implied.
  8. *
  9. * The Marvell EBU SoCs have a configurable physical address space:
  10. * the physical address at which certain devices (PCIe, NOR, NAND,
  11. * etc.) sit can be configured. The configuration takes place through
  12. * two sets of registers:
  13. *
  14. * - One to configure the access of the CPU to the devices. Depending
  15. * on the families, there are between 8 and 20 configurable windows,
  16. * each can be use to create a physical memory window that maps to a
  17. * specific device. Devices are identified by a tuple (target,
  18. * attribute).
  19. *
  20. * - One to configure the access to the CPU to the SDRAM. There are
  21. * either 2 (for Dove) or 4 (for other families) windows to map the
  22. * SDRAM into the physical address space.
  23. *
  24. * This driver:
  25. *
  26. * - Reads out the SDRAM address decoding windows at initialization
  27. * time, and fills the mvebu_mbus_dram_info structure with these
  28. * informations. The exported function mv_mbus_dram_info() allow
  29. * device drivers to get those informations related to the SDRAM
  30. * address decoding windows. This is because devices also have their
  31. * own windows (configured through registers that are part of each
  32. * device register space), and therefore the drivers for Marvell
  33. * devices have to configure those device -> SDRAM windows to ensure
  34. * that DMA works properly.
  35. *
  36. * - Provides an API for platform code or device drivers to
  37. * dynamically add or remove address decoding windows for the CPU ->
  38. * device accesses. This API is mvebu_mbus_add_window_by_id(),
  39. * mvebu_mbus_add_window_remap_by_id() and
  40. * mvebu_mbus_del_window().
  41. *
  42. * - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to
  43. * see the list of CPU -> SDRAM windows and their configuration
  44. * (file 'sdram') and the list of CPU -> devices windows and their
  45. * configuration (file 'devices').
  46. */
  47. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  48. #include <linux/kernel.h>
  49. #include <linux/module.h>
  50. #include <linux/init.h>
  51. #include <linux/mbus.h>
  52. #include <linux/io.h>
  53. #include <linux/ioport.h>
  54. #include <linux/of.h>
  55. #include <linux/of_address.h>
  56. #include <linux/debugfs.h>
  57. #include <linux/log2.h>
  58. #include <linux/memblock.h>
  59. #include <linux/syscore_ops.h>
  60. /*
  61. * DDR target is the same on all platforms.
  62. */
  63. #define TARGET_DDR 0
  64. /*
  65. * CPU Address Decode Windows registers
  66. */
  67. #define WIN_CTRL_OFF 0x0000
  68. #define WIN_CTRL_ENABLE BIT(0)
  69. /* Only on HW I/O coherency capable platforms */
  70. #define WIN_CTRL_SYNCBARRIER BIT(1)
  71. #define WIN_CTRL_TGT_MASK 0xf0
  72. #define WIN_CTRL_TGT_SHIFT 4
  73. #define WIN_CTRL_ATTR_MASK 0xff00
  74. #define WIN_CTRL_ATTR_SHIFT 8
  75. #define WIN_CTRL_SIZE_MASK 0xffff0000
  76. #define WIN_CTRL_SIZE_SHIFT 16
  77. #define WIN_BASE_OFF 0x0004
  78. #define WIN_BASE_LOW 0xffff0000
  79. #define WIN_BASE_HIGH 0xf
  80. #define WIN_REMAP_LO_OFF 0x0008
  81. #define WIN_REMAP_LOW 0xffff0000
  82. #define WIN_REMAP_HI_OFF 0x000c
  83. #define UNIT_SYNC_BARRIER_OFF 0x84
  84. #define UNIT_SYNC_BARRIER_ALL 0xFFFF
  85. #define ATTR_HW_COHERENCY (0x1 << 4)
  86. #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
  87. #define DDR_BASE_CS_HIGH_MASK 0xf
  88. #define DDR_BASE_CS_LOW_MASK 0xff000000
  89. #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
  90. #define DDR_SIZE_ENABLED BIT(0)
  91. #define DDR_SIZE_CS_MASK 0x1c
  92. #define DDR_SIZE_CS_SHIFT 2
  93. #define DDR_SIZE_MASK 0xff000000
  94. #define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
  95. /* Relative to mbusbridge_base */
  96. #define MBUS_BRIDGE_CTRL_OFF 0x0
  97. #define MBUS_BRIDGE_BASE_OFF 0x4
  98. /* Maximum number of windows, for all known platforms */
  99. #define MBUS_WINS_MAX 20
  100. struct mvebu_mbus_state;
  101. struct mvebu_mbus_soc_data {
  102. unsigned int num_wins;
  103. bool has_mbus_bridge;
  104. unsigned int (*win_cfg_offset)(const int win);
  105. unsigned int (*win_remap_offset)(const int win);
  106. void (*setup_cpu_target)(struct mvebu_mbus_state *s);
  107. int (*save_cpu_target)(struct mvebu_mbus_state *s,
  108. u32 __iomem *store_addr);
  109. int (*show_cpu_target)(struct mvebu_mbus_state *s,
  110. struct seq_file *seq, void *v);
  111. };
  112. /*
  113. * Used to store the state of one MBus window accross suspend/resume.
  114. */
  115. struct mvebu_mbus_win_data {
  116. u32 ctrl;
  117. u32 base;
  118. u32 remap_lo;
  119. u32 remap_hi;
  120. };
  121. struct mvebu_mbus_state {
  122. void __iomem *mbuswins_base;
  123. void __iomem *sdramwins_base;
  124. void __iomem *mbusbridge_base;
  125. phys_addr_t sdramwins_phys_base;
  126. struct dentry *debugfs_root;
  127. struct dentry *debugfs_sdram;
  128. struct dentry *debugfs_devs;
  129. struct resource pcie_mem_aperture;
  130. struct resource pcie_io_aperture;
  131. const struct mvebu_mbus_soc_data *soc;
  132. int hw_io_coherency;
  133. /* Used during suspend/resume */
  134. u32 mbus_bridge_ctrl;
  135. u32 mbus_bridge_base;
  136. struct mvebu_mbus_win_data wins[MBUS_WINS_MAX];
  137. };
  138. static struct mvebu_mbus_state mbus_state;
  139. /*
  140. * We provide two variants of the mv_mbus_dram_info() function:
  141. *
  142. * - The normal one, where the described DRAM ranges may overlap with
  143. * the I/O windows, but for which the DRAM ranges are guaranteed to
  144. * have a power of two size. Such ranges are suitable for the DMA
  145. * masters that only DMA between the RAM and the device, which is
  146. * actually all devices except the crypto engines.
  147. *
  148. * - The 'nooverlap' one, where the described DRAM ranges are
  149. * guaranteed to not overlap with the I/O windows, but for which the
  150. * DRAM ranges will not have power of two sizes. They will only be
  151. * aligned on a 64 KB boundary, and have a size multiple of 64
  152. * KB. Such ranges are suitable for the DMA masters that DMA between
  153. * the crypto SRAM (which is mapped through an I/O window) and a
  154. * device. This is the case for the crypto engines.
  155. */
  156. static struct mbus_dram_target_info mvebu_mbus_dram_info;
  157. static struct mbus_dram_target_info mvebu_mbus_dram_info_nooverlap;
  158. const struct mbus_dram_target_info *mv_mbus_dram_info(void)
  159. {
  160. return &mvebu_mbus_dram_info;
  161. }
  162. EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
  163. const struct mbus_dram_target_info *mv_mbus_dram_info_nooverlap(void)
  164. {
  165. return &mvebu_mbus_dram_info_nooverlap;
  166. }
  167. EXPORT_SYMBOL_GPL(mv_mbus_dram_info_nooverlap);
  168. /* Checks whether the given window has remap capability */
  169. static bool mvebu_mbus_window_is_remappable(struct mvebu_mbus_state *mbus,
  170. const int win)
  171. {
  172. return mbus->soc->win_remap_offset(win) != MVEBU_MBUS_NO_REMAP;
  173. }
  174. /*
  175. * Functions to manipulate the address decoding windows
  176. */
  177. static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus,
  178. int win, int *enabled, u64 *base,
  179. u32 *size, u8 *target, u8 *attr,
  180. u64 *remap)
  181. {
  182. void __iomem *addr = mbus->mbuswins_base +
  183. mbus->soc->win_cfg_offset(win);
  184. u32 basereg = readl(addr + WIN_BASE_OFF);
  185. u32 ctrlreg = readl(addr + WIN_CTRL_OFF);
  186. if (!(ctrlreg & WIN_CTRL_ENABLE)) {
  187. *enabled = 0;
  188. return;
  189. }
  190. *enabled = 1;
  191. *base = ((u64)basereg & WIN_BASE_HIGH) << 32;
  192. *base |= (basereg & WIN_BASE_LOW);
  193. *size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1;
  194. if (target)
  195. *target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT;
  196. if (attr)
  197. *attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT;
  198. if (remap) {
  199. if (mvebu_mbus_window_is_remappable(mbus, win)) {
  200. u32 remap_low, remap_hi;
  201. void __iomem *addr_rmp = mbus->mbuswins_base +
  202. mbus->soc->win_remap_offset(win);
  203. remap_low = readl(addr_rmp + WIN_REMAP_LO_OFF);
  204. remap_hi = readl(addr_rmp + WIN_REMAP_HI_OFF);
  205. *remap = ((u64)remap_hi << 32) | remap_low;
  206. } else
  207. *remap = 0;
  208. }
  209. }
  210. static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus,
  211. int win)
  212. {
  213. void __iomem *addr;
  214. addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win);
  215. writel(0, addr + WIN_BASE_OFF);
  216. writel(0, addr + WIN_CTRL_OFF);
  217. if (mvebu_mbus_window_is_remappable(mbus, win)) {
  218. addr = mbus->mbuswins_base + mbus->soc->win_remap_offset(win);
  219. writel(0, addr + WIN_REMAP_LO_OFF);
  220. writel(0, addr + WIN_REMAP_HI_OFF);
  221. }
  222. }
  223. /* Checks whether the given window number is available */
  224. static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus,
  225. const int win)
  226. {
  227. void __iomem *addr = mbus->mbuswins_base +
  228. mbus->soc->win_cfg_offset(win);
  229. u32 ctrl = readl(addr + WIN_CTRL_OFF);
  230. return !(ctrl & WIN_CTRL_ENABLE);
  231. }
  232. /*
  233. * Checks whether the given (base, base+size) area doesn't overlap an
  234. * existing region
  235. */
  236. static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus,
  237. phys_addr_t base, size_t size,
  238. u8 target, u8 attr)
  239. {
  240. u64 end = (u64)base + size;
  241. int win;
  242. for (win = 0; win < mbus->soc->num_wins; win++) {
  243. u64 wbase, wend;
  244. u32 wsize;
  245. u8 wtarget, wattr;
  246. int enabled;
  247. mvebu_mbus_read_window(mbus, win,
  248. &enabled, &wbase, &wsize,
  249. &wtarget, &wattr, NULL);
  250. if (!enabled)
  251. continue;
  252. wend = wbase + wsize;
  253. /*
  254. * Check if the current window overlaps with the
  255. * proposed physical range
  256. */
  257. if ((u64)base < wend && end > wbase)
  258. return 0;
  259. }
  260. return 1;
  261. }
  262. static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus,
  263. phys_addr_t base, size_t size)
  264. {
  265. int win;
  266. for (win = 0; win < mbus->soc->num_wins; win++) {
  267. u64 wbase;
  268. u32 wsize;
  269. int enabled;
  270. mvebu_mbus_read_window(mbus, win,
  271. &enabled, &wbase, &wsize,
  272. NULL, NULL, NULL);
  273. if (!enabled)
  274. continue;
  275. if (base == wbase && size == wsize)
  276. return win;
  277. }
  278. return -ENODEV;
  279. }
  280. static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
  281. int win, phys_addr_t base, size_t size,
  282. phys_addr_t remap, u8 target,
  283. u8 attr)
  284. {
  285. void __iomem *addr = mbus->mbuswins_base +
  286. mbus->soc->win_cfg_offset(win);
  287. u32 ctrl, remap_addr;
  288. if (!is_power_of_2(size)) {
  289. WARN(true, "Invalid MBus window size: 0x%zx\n", size);
  290. return -EINVAL;
  291. }
  292. if ((base & (phys_addr_t)(size - 1)) != 0) {
  293. WARN(true, "Invalid MBus base/size: %pa len 0x%zx\n", &base,
  294. size);
  295. return -EINVAL;
  296. }
  297. ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
  298. (attr << WIN_CTRL_ATTR_SHIFT) |
  299. (target << WIN_CTRL_TGT_SHIFT) |
  300. WIN_CTRL_ENABLE;
  301. if (mbus->hw_io_coherency)
  302. ctrl |= WIN_CTRL_SYNCBARRIER;
  303. writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
  304. writel(ctrl, addr + WIN_CTRL_OFF);
  305. if (mvebu_mbus_window_is_remappable(mbus, win)) {
  306. void __iomem *addr_rmp = mbus->mbuswins_base +
  307. mbus->soc->win_remap_offset(win);
  308. if (remap == MVEBU_MBUS_NO_REMAP)
  309. remap_addr = base;
  310. else
  311. remap_addr = remap;
  312. writel(remap_addr & WIN_REMAP_LOW, addr_rmp + WIN_REMAP_LO_OFF);
  313. writel(0, addr_rmp + WIN_REMAP_HI_OFF);
  314. }
  315. return 0;
  316. }
  317. static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus,
  318. phys_addr_t base, size_t size,
  319. phys_addr_t remap, u8 target,
  320. u8 attr)
  321. {
  322. int win;
  323. if (remap == MVEBU_MBUS_NO_REMAP) {
  324. for (win = 0; win < mbus->soc->num_wins; win++) {
  325. if (mvebu_mbus_window_is_remappable(mbus, win))
  326. continue;
  327. if (mvebu_mbus_window_is_free(mbus, win))
  328. return mvebu_mbus_setup_window(mbus, win, base,
  329. size, remap,
  330. target, attr);
  331. }
  332. }
  333. for (win = 0; win < mbus->soc->num_wins; win++) {
  334. /* Skip window if need remap but is not supported */
  335. if ((remap != MVEBU_MBUS_NO_REMAP) &&
  336. !mvebu_mbus_window_is_remappable(mbus, win))
  337. continue;
  338. if (mvebu_mbus_window_is_free(mbus, win))
  339. return mvebu_mbus_setup_window(mbus, win, base, size,
  340. remap, target, attr);
  341. }
  342. return -ENOMEM;
  343. }
  344. /*
  345. * Debugfs debugging
  346. */
  347. /* Common function used for Dove, Kirkwood, Armada 370/XP and Orion 5x */
  348. static int mvebu_sdram_debug_show_orion(struct mvebu_mbus_state *mbus,
  349. struct seq_file *seq, void *v)
  350. {
  351. int i;
  352. for (i = 0; i < 4; i++) {
  353. u32 basereg = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
  354. u32 sizereg = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
  355. u64 base;
  356. u32 size;
  357. if (!(sizereg & DDR_SIZE_ENABLED)) {
  358. seq_printf(seq, "[%d] disabled\n", i);
  359. continue;
  360. }
  361. base = ((u64)basereg & DDR_BASE_CS_HIGH_MASK) << 32;
  362. base |= basereg & DDR_BASE_CS_LOW_MASK;
  363. size = (sizereg | ~DDR_SIZE_MASK);
  364. seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
  365. i, (unsigned long long)base,
  366. (unsigned long long)base + size + 1,
  367. (sizereg & DDR_SIZE_CS_MASK) >> DDR_SIZE_CS_SHIFT);
  368. }
  369. return 0;
  370. }
  371. /* Special function for Dove */
  372. static int mvebu_sdram_debug_show_dove(struct mvebu_mbus_state *mbus,
  373. struct seq_file *seq, void *v)
  374. {
  375. int i;
  376. for (i = 0; i < 2; i++) {
  377. u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
  378. u64 base;
  379. u32 size;
  380. if (!(map & 1)) {
  381. seq_printf(seq, "[%d] disabled\n", i);
  382. continue;
  383. }
  384. base = map & 0xff800000;
  385. size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
  386. seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
  387. i, (unsigned long long)base,
  388. (unsigned long long)base + size, i);
  389. }
  390. return 0;
  391. }
  392. static int mvebu_sdram_debug_show(struct seq_file *seq, void *v)
  393. {
  394. struct mvebu_mbus_state *mbus = &mbus_state;
  395. return mbus->soc->show_cpu_target(mbus, seq, v);
  396. }
  397. static int mvebu_sdram_debug_open(struct inode *inode, struct file *file)
  398. {
  399. return single_open(file, mvebu_sdram_debug_show, inode->i_private);
  400. }
  401. static const struct file_operations mvebu_sdram_debug_fops = {
  402. .open = mvebu_sdram_debug_open,
  403. .read = seq_read,
  404. .llseek = seq_lseek,
  405. .release = single_release,
  406. };
  407. static int mvebu_devs_debug_show(struct seq_file *seq, void *v)
  408. {
  409. struct mvebu_mbus_state *mbus = &mbus_state;
  410. int win;
  411. for (win = 0; win < mbus->soc->num_wins; win++) {
  412. u64 wbase, wremap;
  413. u32 wsize;
  414. u8 wtarget, wattr;
  415. int enabled;
  416. mvebu_mbus_read_window(mbus, win,
  417. &enabled, &wbase, &wsize,
  418. &wtarget, &wattr, &wremap);
  419. if (!enabled) {
  420. seq_printf(seq, "[%02d] disabled\n", win);
  421. continue;
  422. }
  423. seq_printf(seq, "[%02d] %016llx - %016llx : %04x:%04x",
  424. win, (unsigned long long)wbase,
  425. (unsigned long long)(wbase + wsize), wtarget, wattr);
  426. if (!is_power_of_2(wsize) ||
  427. ((wbase & (u64)(wsize - 1)) != 0))
  428. seq_puts(seq, " (Invalid base/size!!)");
  429. if (mvebu_mbus_window_is_remappable(mbus, win)) {
  430. seq_printf(seq, " (remap %016llx)\n",
  431. (unsigned long long)wremap);
  432. } else
  433. seq_printf(seq, "\n");
  434. }
  435. return 0;
  436. }
  437. static int mvebu_devs_debug_open(struct inode *inode, struct file *file)
  438. {
  439. return single_open(file, mvebu_devs_debug_show, inode->i_private);
  440. }
  441. static const struct file_operations mvebu_devs_debug_fops = {
  442. .open = mvebu_devs_debug_open,
  443. .read = seq_read,
  444. .llseek = seq_lseek,
  445. .release = single_release,
  446. };
  447. /*
  448. * SoC-specific functions and definitions
  449. */
  450. static unsigned int generic_mbus_win_cfg_offset(int win)
  451. {
  452. return win << 4;
  453. }
  454. static unsigned int armada_370_xp_mbus_win_cfg_offset(int win)
  455. {
  456. /* The register layout is a bit annoying and the below code
  457. * tries to cope with it.
  458. * - At offset 0x0, there are the registers for the first 8
  459. * windows, with 4 registers of 32 bits per window (ctrl,
  460. * base, remap low, remap high)
  461. * - Then at offset 0x80, there is a hole of 0x10 bytes for
  462. * the internal registers base address and internal units
  463. * sync barrier register.
  464. * - Then at offset 0x90, there the registers for 12
  465. * windows, with only 2 registers of 32 bits per window
  466. * (ctrl, base).
  467. */
  468. if (win < 8)
  469. return win << 4;
  470. else
  471. return 0x90 + ((win - 8) << 3);
  472. }
  473. static unsigned int mv78xx0_mbus_win_cfg_offset(int win)
  474. {
  475. if (win < 8)
  476. return win << 4;
  477. else
  478. return 0x900 + ((win - 8) << 4);
  479. }
  480. static unsigned int generic_mbus_win_remap_2_offset(int win)
  481. {
  482. if (win < 2)
  483. return generic_mbus_win_cfg_offset(win);
  484. else
  485. return MVEBU_MBUS_NO_REMAP;
  486. }
  487. static unsigned int generic_mbus_win_remap_4_offset(int win)
  488. {
  489. if (win < 4)
  490. return generic_mbus_win_cfg_offset(win);
  491. else
  492. return MVEBU_MBUS_NO_REMAP;
  493. }
  494. static unsigned int generic_mbus_win_remap_8_offset(int win)
  495. {
  496. if (win < 8)
  497. return generic_mbus_win_cfg_offset(win);
  498. else
  499. return MVEBU_MBUS_NO_REMAP;
  500. }
  501. static unsigned int armada_xp_mbus_win_remap_offset(int win)
  502. {
  503. if (win < 8)
  504. return generic_mbus_win_cfg_offset(win);
  505. else if (win == 13)
  506. return 0xF0 - WIN_REMAP_LO_OFF;
  507. else
  508. return MVEBU_MBUS_NO_REMAP;
  509. }
  510. /*
  511. * Use the memblock information to find the MBus bridge hole in the
  512. * physical address space.
  513. */
  514. static void __init
  515. mvebu_mbus_find_bridge_hole(uint64_t *start, uint64_t *end)
  516. {
  517. struct memblock_region *r;
  518. uint64_t s = 0;
  519. for_each_memblock(memory, r) {
  520. /*
  521. * This part of the memory is above 4 GB, so we don't
  522. * care for the MBus bridge hole.
  523. */
  524. if (r->base >= 0x100000000ULL)
  525. continue;
  526. /*
  527. * The MBus bridge hole is at the end of the RAM under
  528. * the 4 GB limit.
  529. */
  530. if (r->base + r->size > s)
  531. s = r->base + r->size;
  532. }
  533. *start = s;
  534. *end = 0x100000000ULL;
  535. }
  536. /*
  537. * This function fills in the mvebu_mbus_dram_info_nooverlap data
  538. * structure, by looking at the mvebu_mbus_dram_info data, and
  539. * removing the parts of it that overlap with I/O windows.
  540. */
  541. static void __init
  542. mvebu_mbus_setup_cpu_target_nooverlap(struct mvebu_mbus_state *mbus)
  543. {
  544. uint64_t mbus_bridge_base, mbus_bridge_end;
  545. int cs_nooverlap = 0;
  546. int i;
  547. mvebu_mbus_find_bridge_hole(&mbus_bridge_base, &mbus_bridge_end);
  548. for (i = 0; i < mvebu_mbus_dram_info.num_cs; i++) {
  549. struct mbus_dram_window *w;
  550. u64 base, size, end;
  551. w = &mvebu_mbus_dram_info.cs[i];
  552. base = w->base;
  553. size = w->size;
  554. end = base + size;
  555. /*
  556. * The CS is fully enclosed inside the MBus bridge
  557. * area, so ignore it.
  558. */
  559. if (base >= mbus_bridge_base && end <= mbus_bridge_end)
  560. continue;
  561. /*
  562. * Beginning of CS overlaps with end of MBus, raise CS
  563. * base address, and shrink its size.
  564. */
  565. if (base >= mbus_bridge_base && end > mbus_bridge_end) {
  566. size -= mbus_bridge_end - base;
  567. base = mbus_bridge_end;
  568. }
  569. /*
  570. * End of CS overlaps with beginning of MBus, shrink
  571. * CS size.
  572. */
  573. if (base < mbus_bridge_base && end > mbus_bridge_base)
  574. size -= end - mbus_bridge_base;
  575. w = &mvebu_mbus_dram_info_nooverlap.cs[cs_nooverlap++];
  576. w->cs_index = i;
  577. w->mbus_attr = 0xf & ~(1 << i);
  578. if (mbus->hw_io_coherency)
  579. w->mbus_attr |= ATTR_HW_COHERENCY;
  580. w->base = base;
  581. w->size = size;
  582. }
  583. mvebu_mbus_dram_info_nooverlap.mbus_dram_target_id = TARGET_DDR;
  584. mvebu_mbus_dram_info_nooverlap.num_cs = cs_nooverlap;
  585. }
  586. static void __init
  587. mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
  588. {
  589. int i;
  590. int cs;
  591. mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
  592. for (i = 0, cs = 0; i < 4; i++) {
  593. u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
  594. u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
  595. /*
  596. * We only take care of entries for which the chip
  597. * select is enabled, and that don't have high base
  598. * address bits set (devices can only access the first
  599. * 32 bits of the memory).
  600. */
  601. if ((size & DDR_SIZE_ENABLED) &&
  602. !(base & DDR_BASE_CS_HIGH_MASK)) {
  603. struct mbus_dram_window *w;
  604. w = &mvebu_mbus_dram_info.cs[cs++];
  605. w->cs_index = i;
  606. w->mbus_attr = 0xf & ~(1 << i);
  607. if (mbus->hw_io_coherency)
  608. w->mbus_attr |= ATTR_HW_COHERENCY;
  609. w->base = base & DDR_BASE_CS_LOW_MASK;
  610. w->size = (u64)(size | ~DDR_SIZE_MASK) + 1;
  611. }
  612. }
  613. mvebu_mbus_dram_info.num_cs = cs;
  614. }
  615. static int
  616. mvebu_mbus_default_save_cpu_target(struct mvebu_mbus_state *mbus,
  617. u32 __iomem *store_addr)
  618. {
  619. int i;
  620. for (i = 0; i < 4; i++) {
  621. u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
  622. u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
  623. writel(mbus->sdramwins_phys_base + DDR_BASE_CS_OFF(i),
  624. store_addr++);
  625. writel(base, store_addr++);
  626. writel(mbus->sdramwins_phys_base + DDR_SIZE_CS_OFF(i),
  627. store_addr++);
  628. writel(size, store_addr++);
  629. }
  630. /* We've written 16 words to the store address */
  631. return 16;
  632. }
  633. static void __init
  634. mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
  635. {
  636. int i;
  637. int cs;
  638. mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
  639. for (i = 0, cs = 0; i < 2; i++) {
  640. u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
  641. /*
  642. * Chip select enabled?
  643. */
  644. if (map & 1) {
  645. struct mbus_dram_window *w;
  646. w = &mvebu_mbus_dram_info.cs[cs++];
  647. w->cs_index = i;
  648. w->mbus_attr = 0; /* CS address decoding done inside */
  649. /* the DDR controller, no need to */
  650. /* provide attributes */
  651. w->base = map & 0xff800000;
  652. w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
  653. }
  654. }
  655. mvebu_mbus_dram_info.num_cs = cs;
  656. }
  657. static int
  658. mvebu_mbus_dove_save_cpu_target(struct mvebu_mbus_state *mbus,
  659. u32 __iomem *store_addr)
  660. {
  661. int i;
  662. for (i = 0; i < 2; i++) {
  663. u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
  664. writel(mbus->sdramwins_phys_base + DOVE_DDR_BASE_CS_OFF(i),
  665. store_addr++);
  666. writel(map, store_addr++);
  667. }
  668. /* We've written 4 words to the store address */
  669. return 4;
  670. }
  671. int mvebu_mbus_save_cpu_target(u32 __iomem *store_addr)
  672. {
  673. return mbus_state.soc->save_cpu_target(&mbus_state, store_addr);
  674. }
  675. static const struct mvebu_mbus_soc_data armada_370_mbus_data = {
  676. .num_wins = 20,
  677. .has_mbus_bridge = true,
  678. .win_cfg_offset = armada_370_xp_mbus_win_cfg_offset,
  679. .win_remap_offset = generic_mbus_win_remap_8_offset,
  680. .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
  681. .show_cpu_target = mvebu_sdram_debug_show_orion,
  682. .save_cpu_target = mvebu_mbus_default_save_cpu_target,
  683. };
  684. static const struct mvebu_mbus_soc_data armada_xp_mbus_data = {
  685. .num_wins = 20,
  686. .has_mbus_bridge = true,
  687. .win_cfg_offset = armada_370_xp_mbus_win_cfg_offset,
  688. .win_remap_offset = armada_xp_mbus_win_remap_offset,
  689. .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
  690. .show_cpu_target = mvebu_sdram_debug_show_orion,
  691. .save_cpu_target = mvebu_mbus_default_save_cpu_target,
  692. };
  693. static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
  694. .num_wins = 8,
  695. .win_cfg_offset = generic_mbus_win_cfg_offset,
  696. .save_cpu_target = mvebu_mbus_default_save_cpu_target,
  697. .win_remap_offset = generic_mbus_win_remap_4_offset,
  698. .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
  699. .show_cpu_target = mvebu_sdram_debug_show_orion,
  700. };
  701. static const struct mvebu_mbus_soc_data dove_mbus_data = {
  702. .num_wins = 8,
  703. .win_cfg_offset = generic_mbus_win_cfg_offset,
  704. .save_cpu_target = mvebu_mbus_dove_save_cpu_target,
  705. .win_remap_offset = generic_mbus_win_remap_4_offset,
  706. .setup_cpu_target = mvebu_mbus_dove_setup_cpu_target,
  707. .show_cpu_target = mvebu_sdram_debug_show_dove,
  708. };
  709. /*
  710. * Some variants of Orion5x have 4 remappable windows, some other have
  711. * only two of them.
  712. */
  713. static const struct mvebu_mbus_soc_data orion5x_4win_mbus_data = {
  714. .num_wins = 8,
  715. .win_cfg_offset = generic_mbus_win_cfg_offset,
  716. .save_cpu_target = mvebu_mbus_default_save_cpu_target,
  717. .win_remap_offset = generic_mbus_win_remap_4_offset,
  718. .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
  719. .show_cpu_target = mvebu_sdram_debug_show_orion,
  720. };
  721. static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
  722. .num_wins = 8,
  723. .win_cfg_offset = generic_mbus_win_cfg_offset,
  724. .save_cpu_target = mvebu_mbus_default_save_cpu_target,
  725. .win_remap_offset = generic_mbus_win_remap_2_offset,
  726. .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
  727. .show_cpu_target = mvebu_sdram_debug_show_orion,
  728. };
  729. static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
  730. .num_wins = 14,
  731. .win_cfg_offset = mv78xx0_mbus_win_cfg_offset,
  732. .save_cpu_target = mvebu_mbus_default_save_cpu_target,
  733. .win_remap_offset = generic_mbus_win_remap_8_offset,
  734. .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
  735. .show_cpu_target = mvebu_sdram_debug_show_orion,
  736. };
  737. static const struct of_device_id of_mvebu_mbus_ids[] = {
  738. { .compatible = "marvell,armada370-mbus",
  739. .data = &armada_370_mbus_data, },
  740. { .compatible = "marvell,armada375-mbus",
  741. .data = &armada_xp_mbus_data, },
  742. { .compatible = "marvell,armada380-mbus",
  743. .data = &armada_xp_mbus_data, },
  744. { .compatible = "marvell,armadaxp-mbus",
  745. .data = &armada_xp_mbus_data, },
  746. { .compatible = "marvell,kirkwood-mbus",
  747. .data = &kirkwood_mbus_data, },
  748. { .compatible = "marvell,dove-mbus",
  749. .data = &dove_mbus_data, },
  750. { .compatible = "marvell,orion5x-88f5281-mbus",
  751. .data = &orion5x_4win_mbus_data, },
  752. { .compatible = "marvell,orion5x-88f5182-mbus",
  753. .data = &orion5x_2win_mbus_data, },
  754. { .compatible = "marvell,orion5x-88f5181-mbus",
  755. .data = &orion5x_2win_mbus_data, },
  756. { .compatible = "marvell,orion5x-88f6183-mbus",
  757. .data = &orion5x_4win_mbus_data, },
  758. { .compatible = "marvell,mv78xx0-mbus",
  759. .data = &mv78xx0_mbus_data, },
  760. { },
  761. };
  762. /*
  763. * Public API of the driver
  764. */
  765. int mvebu_mbus_add_window_remap_by_id(unsigned int target,
  766. unsigned int attribute,
  767. phys_addr_t base, size_t size,
  768. phys_addr_t remap)
  769. {
  770. struct mvebu_mbus_state *s = &mbus_state;
  771. if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
  772. pr_err("cannot add window '%x:%x', conflicts with another window\n",
  773. target, attribute);
  774. return -EINVAL;
  775. }
  776. return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
  777. }
  778. int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
  779. phys_addr_t base, size_t size)
  780. {
  781. return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
  782. size, MVEBU_MBUS_NO_REMAP);
  783. }
  784. int mvebu_mbus_del_window(phys_addr_t base, size_t size)
  785. {
  786. int win;
  787. win = mvebu_mbus_find_window(&mbus_state, base, size);
  788. if (win < 0)
  789. return win;
  790. mvebu_mbus_disable_window(&mbus_state, win);
  791. return 0;
  792. }
  793. void mvebu_mbus_get_pcie_mem_aperture(struct resource *res)
  794. {
  795. if (!res)
  796. return;
  797. *res = mbus_state.pcie_mem_aperture;
  798. }
  799. void mvebu_mbus_get_pcie_io_aperture(struct resource *res)
  800. {
  801. if (!res)
  802. return;
  803. *res = mbus_state.pcie_io_aperture;
  804. }
  805. int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr)
  806. {
  807. const struct mbus_dram_target_info *dram;
  808. int i;
  809. /* Get dram info */
  810. dram = mv_mbus_dram_info();
  811. if (!dram) {
  812. pr_err("missing DRAM information\n");
  813. return -ENODEV;
  814. }
  815. /* Try to find matching DRAM window for phyaddr */
  816. for (i = 0; i < dram->num_cs; i++) {
  817. const struct mbus_dram_window *cs = dram->cs + i;
  818. if (cs->base <= phyaddr &&
  819. phyaddr <= (cs->base + cs->size - 1)) {
  820. *target = dram->mbus_dram_target_id;
  821. *attr = cs->mbus_attr;
  822. return 0;
  823. }
  824. }
  825. pr_err("invalid dram address %pa\n", &phyaddr);
  826. return -EINVAL;
  827. }
  828. EXPORT_SYMBOL_GPL(mvebu_mbus_get_dram_win_info);
  829. int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 *size, u8 *target,
  830. u8 *attr)
  831. {
  832. int win;
  833. for (win = 0; win < mbus_state.soc->num_wins; win++) {
  834. u64 wbase;
  835. int enabled;
  836. mvebu_mbus_read_window(&mbus_state, win, &enabled, &wbase,
  837. size, target, attr, NULL);
  838. if (!enabled)
  839. continue;
  840. if (wbase <= phyaddr && phyaddr <= wbase + *size)
  841. return win;
  842. }
  843. return -EINVAL;
  844. }
  845. EXPORT_SYMBOL_GPL(mvebu_mbus_get_io_win_info);
  846. static __init int mvebu_mbus_debugfs_init(void)
  847. {
  848. struct mvebu_mbus_state *s = &mbus_state;
  849. /*
  850. * If no base has been initialized, doesn't make sense to
  851. * register the debugfs entries. We may be on a multiplatform
  852. * kernel that isn't running a Marvell EBU SoC.
  853. */
  854. if (!s->mbuswins_base)
  855. return 0;
  856. s->debugfs_root = debugfs_create_dir("mvebu-mbus", NULL);
  857. if (s->debugfs_root) {
  858. s->debugfs_sdram = debugfs_create_file("sdram", S_IRUGO,
  859. s->debugfs_root, NULL,
  860. &mvebu_sdram_debug_fops);
  861. s->debugfs_devs = debugfs_create_file("devices", S_IRUGO,
  862. s->debugfs_root, NULL,
  863. &mvebu_devs_debug_fops);
  864. }
  865. return 0;
  866. }
  867. fs_initcall(mvebu_mbus_debugfs_init);
  868. static int mvebu_mbus_suspend(void)
  869. {
  870. struct mvebu_mbus_state *s = &mbus_state;
  871. int win;
  872. if (!s->mbusbridge_base)
  873. return -ENODEV;
  874. for (win = 0; win < s->soc->num_wins; win++) {
  875. void __iomem *addr = s->mbuswins_base +
  876. s->soc->win_cfg_offset(win);
  877. void __iomem *addr_rmp;
  878. s->wins[win].base = readl(addr + WIN_BASE_OFF);
  879. s->wins[win].ctrl = readl(addr + WIN_CTRL_OFF);
  880. if (!mvebu_mbus_window_is_remappable(s, win))
  881. continue;
  882. addr_rmp = s->mbuswins_base +
  883. s->soc->win_remap_offset(win);
  884. s->wins[win].remap_lo = readl(addr_rmp + WIN_REMAP_LO_OFF);
  885. s->wins[win].remap_hi = readl(addr_rmp + WIN_REMAP_HI_OFF);
  886. }
  887. s->mbus_bridge_ctrl = readl(s->mbusbridge_base +
  888. MBUS_BRIDGE_CTRL_OFF);
  889. s->mbus_bridge_base = readl(s->mbusbridge_base +
  890. MBUS_BRIDGE_BASE_OFF);
  891. return 0;
  892. }
  893. static void mvebu_mbus_resume(void)
  894. {
  895. struct mvebu_mbus_state *s = &mbus_state;
  896. int win;
  897. writel(s->mbus_bridge_ctrl,
  898. s->mbusbridge_base + MBUS_BRIDGE_CTRL_OFF);
  899. writel(s->mbus_bridge_base,
  900. s->mbusbridge_base + MBUS_BRIDGE_BASE_OFF);
  901. for (win = 0; win < s->soc->num_wins; win++) {
  902. void __iomem *addr = s->mbuswins_base +
  903. s->soc->win_cfg_offset(win);
  904. void __iomem *addr_rmp;
  905. writel(s->wins[win].base, addr + WIN_BASE_OFF);
  906. writel(s->wins[win].ctrl, addr + WIN_CTRL_OFF);
  907. if (!mvebu_mbus_window_is_remappable(s, win))
  908. continue;
  909. addr_rmp = s->mbuswins_base +
  910. s->soc->win_remap_offset(win);
  911. writel(s->wins[win].remap_lo, addr_rmp + WIN_REMAP_LO_OFF);
  912. writel(s->wins[win].remap_hi, addr_rmp + WIN_REMAP_HI_OFF);
  913. }
  914. }
  915. static struct syscore_ops mvebu_mbus_syscore_ops = {
  916. .suspend = mvebu_mbus_suspend,
  917. .resume = mvebu_mbus_resume,
  918. };
  919. static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus,
  920. phys_addr_t mbuswins_phys_base,
  921. size_t mbuswins_size,
  922. phys_addr_t sdramwins_phys_base,
  923. size_t sdramwins_size,
  924. phys_addr_t mbusbridge_phys_base,
  925. size_t mbusbridge_size,
  926. bool is_coherent)
  927. {
  928. int win;
  929. mbus->mbuswins_base = ioremap(mbuswins_phys_base, mbuswins_size);
  930. if (!mbus->mbuswins_base)
  931. return -ENOMEM;
  932. mbus->sdramwins_base = ioremap(sdramwins_phys_base, sdramwins_size);
  933. if (!mbus->sdramwins_base) {
  934. iounmap(mbus_state.mbuswins_base);
  935. return -ENOMEM;
  936. }
  937. mbus->sdramwins_phys_base = sdramwins_phys_base;
  938. if (mbusbridge_phys_base) {
  939. mbus->mbusbridge_base = ioremap(mbusbridge_phys_base,
  940. mbusbridge_size);
  941. if (!mbus->mbusbridge_base) {
  942. iounmap(mbus->sdramwins_base);
  943. iounmap(mbus->mbuswins_base);
  944. return -ENOMEM;
  945. }
  946. } else
  947. mbus->mbusbridge_base = NULL;
  948. for (win = 0; win < mbus->soc->num_wins; win++)
  949. mvebu_mbus_disable_window(mbus, win);
  950. mbus->soc->setup_cpu_target(mbus);
  951. mvebu_mbus_setup_cpu_target_nooverlap(mbus);
  952. if (is_coherent)
  953. writel(UNIT_SYNC_BARRIER_ALL,
  954. mbus->mbuswins_base + UNIT_SYNC_BARRIER_OFF);
  955. register_syscore_ops(&mvebu_mbus_syscore_ops);
  956. return 0;
  957. }
  958. int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
  959. size_t mbuswins_size,
  960. phys_addr_t sdramwins_phys_base,
  961. size_t sdramwins_size)
  962. {
  963. const struct of_device_id *of_id;
  964. for (of_id = of_mvebu_mbus_ids; of_id->compatible[0]; of_id++)
  965. if (!strcmp(of_id->compatible, soc))
  966. break;
  967. if (!of_id->compatible[0]) {
  968. pr_err("could not find a matching SoC family\n");
  969. return -ENODEV;
  970. }
  971. mbus_state.soc = of_id->data;
  972. return mvebu_mbus_common_init(&mbus_state,
  973. mbuswins_phys_base,
  974. mbuswins_size,
  975. sdramwins_phys_base,
  976. sdramwins_size, 0, 0, false);
  977. }
  978. #ifdef CONFIG_OF
  979. /*
  980. * The window IDs in the ranges DT property have the following format:
  981. * - bits 28 to 31: MBus custom field
  982. * - bits 24 to 27: window target ID
  983. * - bits 16 to 23: window attribute ID
  984. * - bits 0 to 15: unused
  985. */
  986. #define CUSTOM(id) (((id) & 0xF0000000) >> 24)
  987. #define TARGET(id) (((id) & 0x0F000000) >> 24)
  988. #define ATTR(id) (((id) & 0x00FF0000) >> 16)
  989. static int __init mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
  990. u32 base, u32 size,
  991. u8 target, u8 attr)
  992. {
  993. if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
  994. pr_err("cannot add window '%04x:%04x', conflicts with another window\n",
  995. target, attr);
  996. return -EBUSY;
  997. }
  998. if (mvebu_mbus_alloc_window(mbus, base, size, MVEBU_MBUS_NO_REMAP,
  999. target, attr)) {
  1000. pr_err("cannot add window '%04x:%04x', too many windows\n",
  1001. target, attr);
  1002. return -ENOMEM;
  1003. }
  1004. return 0;
  1005. }
  1006. static int __init
  1007. mbus_parse_ranges(struct device_node *node,
  1008. int *addr_cells, int *c_addr_cells, int *c_size_cells,
  1009. int *cell_count, const __be32 **ranges_start,
  1010. const __be32 **ranges_end)
  1011. {
  1012. const __be32 *prop;
  1013. int ranges_len, tuple_len;
  1014. /* Allow a node with no 'ranges' property */
  1015. *ranges_start = of_get_property(node, "ranges", &ranges_len);
  1016. if (*ranges_start == NULL) {
  1017. *addr_cells = *c_addr_cells = *c_size_cells = *cell_count = 0;
  1018. *ranges_start = *ranges_end = NULL;
  1019. return 0;
  1020. }
  1021. *ranges_end = *ranges_start + ranges_len / sizeof(__be32);
  1022. *addr_cells = of_n_addr_cells(node);
  1023. prop = of_get_property(node, "#address-cells", NULL);
  1024. *c_addr_cells = be32_to_cpup(prop);
  1025. prop = of_get_property(node, "#size-cells", NULL);
  1026. *c_size_cells = be32_to_cpup(prop);
  1027. *cell_count = *addr_cells + *c_addr_cells + *c_size_cells;
  1028. tuple_len = (*cell_count) * sizeof(__be32);
  1029. if (ranges_len % tuple_len) {
  1030. pr_warn("malformed ranges entry '%pOFn'\n", node);
  1031. return -EINVAL;
  1032. }
  1033. return 0;
  1034. }
  1035. static int __init mbus_dt_setup(struct mvebu_mbus_state *mbus,
  1036. struct device_node *np)
  1037. {
  1038. int addr_cells, c_addr_cells, c_size_cells;
  1039. int i, ret, cell_count;
  1040. const __be32 *r, *ranges_start, *ranges_end;
  1041. ret = mbus_parse_ranges(np, &addr_cells, &c_addr_cells,
  1042. &c_size_cells, &cell_count,
  1043. &ranges_start, &ranges_end);
  1044. if (ret < 0)
  1045. return ret;
  1046. for (i = 0, r = ranges_start; r < ranges_end; r += cell_count, i++) {
  1047. u32 windowid, base, size;
  1048. u8 target, attr;
  1049. /*
  1050. * An entry with a non-zero custom field do not
  1051. * correspond to a static window, so skip it.
  1052. */
  1053. windowid = of_read_number(r, 1);
  1054. if (CUSTOM(windowid))
  1055. continue;
  1056. target = TARGET(windowid);
  1057. attr = ATTR(windowid);
  1058. base = of_read_number(r + c_addr_cells, addr_cells);
  1059. size = of_read_number(r + c_addr_cells + addr_cells,
  1060. c_size_cells);
  1061. ret = mbus_dt_setup_win(mbus, base, size, target, attr);
  1062. if (ret < 0)
  1063. return ret;
  1064. }
  1065. return 0;
  1066. }
  1067. static void __init mvebu_mbus_get_pcie_resources(struct device_node *np,
  1068. struct resource *mem,
  1069. struct resource *io)
  1070. {
  1071. u32 reg[2];
  1072. int ret;
  1073. /*
  1074. * These are optional, so we make sure that resource_size(x) will
  1075. * return 0.
  1076. */
  1077. memset(mem, 0, sizeof(struct resource));
  1078. mem->end = -1;
  1079. memset(io, 0, sizeof(struct resource));
  1080. io->end = -1;
  1081. ret = of_property_read_u32_array(np, "pcie-mem-aperture", reg, ARRAY_SIZE(reg));
  1082. if (!ret) {
  1083. mem->start = reg[0];
  1084. mem->end = mem->start + reg[1] - 1;
  1085. mem->flags = IORESOURCE_MEM;
  1086. }
  1087. ret = of_property_read_u32_array(np, "pcie-io-aperture", reg, ARRAY_SIZE(reg));
  1088. if (!ret) {
  1089. io->start = reg[0];
  1090. io->end = io->start + reg[1] - 1;
  1091. io->flags = IORESOURCE_IO;
  1092. }
  1093. }
  1094. int __init mvebu_mbus_dt_init(bool is_coherent)
  1095. {
  1096. struct resource mbuswins_res, sdramwins_res, mbusbridge_res;
  1097. struct device_node *np, *controller;
  1098. const struct of_device_id *of_id;
  1099. const __be32 *prop;
  1100. int ret;
  1101. np = of_find_matching_node_and_match(NULL, of_mvebu_mbus_ids, &of_id);
  1102. if (!np) {
  1103. pr_err("could not find a matching SoC family\n");
  1104. return -ENODEV;
  1105. }
  1106. mbus_state.soc = of_id->data;
  1107. prop = of_get_property(np, "controller", NULL);
  1108. if (!prop) {
  1109. pr_err("required 'controller' property missing\n");
  1110. return -EINVAL;
  1111. }
  1112. controller = of_find_node_by_phandle(be32_to_cpup(prop));
  1113. if (!controller) {
  1114. pr_err("could not find an 'mbus-controller' node\n");
  1115. return -ENODEV;
  1116. }
  1117. if (of_address_to_resource(controller, 0, &mbuswins_res)) {
  1118. pr_err("cannot get MBUS register address\n");
  1119. return -EINVAL;
  1120. }
  1121. if (of_address_to_resource(controller, 1, &sdramwins_res)) {
  1122. pr_err("cannot get SDRAM register address\n");
  1123. return -EINVAL;
  1124. }
  1125. /*
  1126. * Set the resource to 0 so that it can be left unmapped by
  1127. * mvebu_mbus_common_init() if the DT doesn't carry the
  1128. * necessary information. This is needed to preserve backward
  1129. * compatibility.
  1130. */
  1131. memset(&mbusbridge_res, 0, sizeof(mbusbridge_res));
  1132. if (mbus_state.soc->has_mbus_bridge) {
  1133. if (of_address_to_resource(controller, 2, &mbusbridge_res))
  1134. pr_warn(FW_WARN "deprecated mbus-mvebu Device Tree, suspend/resume will not work\n");
  1135. }
  1136. mbus_state.hw_io_coherency = is_coherent;
  1137. /* Get optional pcie-{mem,io}-aperture properties */
  1138. mvebu_mbus_get_pcie_resources(np, &mbus_state.pcie_mem_aperture,
  1139. &mbus_state.pcie_io_aperture);
  1140. ret = mvebu_mbus_common_init(&mbus_state,
  1141. mbuswins_res.start,
  1142. resource_size(&mbuswins_res),
  1143. sdramwins_res.start,
  1144. resource_size(&sdramwins_res),
  1145. mbusbridge_res.start,
  1146. resource_size(&mbusbridge_res),
  1147. is_coherent);
  1148. if (ret)
  1149. return ret;
  1150. /* Setup statically declared windows in the DT */
  1151. return mbus_dt_setup(&mbus_state, np);
  1152. }
  1153. #endif