arm-cci.c 16 KB

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  1. /*
  2. * CCI cache coherent interconnect driver
  3. *
  4. * Copyright (C) 2013 ARM Ltd.
  5. * Author: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12. * kind, whether express or implied; without even the implied warranty
  13. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. */
  16. #include <linux/arm-cci.h>
  17. #include <linux/io.h>
  18. #include <linux/module.h>
  19. #include <linux/of_address.h>
  20. #include <linux/of_platform.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/slab.h>
  23. #include <asm/cacheflush.h>
  24. #include <asm/smp_plat.h>
  25. static void __iomem *cci_ctrl_base __ro_after_init;
  26. static unsigned long cci_ctrl_phys __ro_after_init;
  27. #ifdef CONFIG_ARM_CCI400_PORT_CTRL
  28. struct cci_nb_ports {
  29. unsigned int nb_ace;
  30. unsigned int nb_ace_lite;
  31. };
  32. static const struct cci_nb_ports cci400_ports = {
  33. .nb_ace = 2,
  34. .nb_ace_lite = 3
  35. };
  36. #define CCI400_PORTS_DATA (&cci400_ports)
  37. #else
  38. #define CCI400_PORTS_DATA (NULL)
  39. #endif
  40. static const struct of_device_id arm_cci_matches[] = {
  41. #ifdef CONFIG_ARM_CCI400_COMMON
  42. {.compatible = "arm,cci-400", .data = CCI400_PORTS_DATA },
  43. #endif
  44. #ifdef CONFIG_ARM_CCI5xx_PMU
  45. { .compatible = "arm,cci-500", },
  46. { .compatible = "arm,cci-550", },
  47. #endif
  48. {},
  49. };
  50. static const struct of_dev_auxdata arm_cci_auxdata[] = {
  51. OF_DEV_AUXDATA("arm,cci-400-pmu", 0, NULL, &cci_ctrl_base),
  52. OF_DEV_AUXDATA("arm,cci-400-pmu,r0", 0, NULL, &cci_ctrl_base),
  53. OF_DEV_AUXDATA("arm,cci-400-pmu,r1", 0, NULL, &cci_ctrl_base),
  54. OF_DEV_AUXDATA("arm,cci-500-pmu,r0", 0, NULL, &cci_ctrl_base),
  55. OF_DEV_AUXDATA("arm,cci-550-pmu,r0", 0, NULL, &cci_ctrl_base),
  56. {}
  57. };
  58. #define DRIVER_NAME "ARM-CCI"
  59. static int cci_platform_probe(struct platform_device *pdev)
  60. {
  61. if (!cci_probed())
  62. return -ENODEV;
  63. return of_platform_populate(pdev->dev.of_node, NULL,
  64. arm_cci_auxdata, &pdev->dev);
  65. }
  66. static struct platform_driver cci_platform_driver = {
  67. .driver = {
  68. .name = DRIVER_NAME,
  69. .of_match_table = arm_cci_matches,
  70. },
  71. .probe = cci_platform_probe,
  72. };
  73. static int __init cci_platform_init(void)
  74. {
  75. return platform_driver_register(&cci_platform_driver);
  76. }
  77. #ifdef CONFIG_ARM_CCI400_PORT_CTRL
  78. #define CCI_PORT_CTRL 0x0
  79. #define CCI_CTRL_STATUS 0xc
  80. #define CCI_ENABLE_SNOOP_REQ 0x1
  81. #define CCI_ENABLE_DVM_REQ 0x2
  82. #define CCI_ENABLE_REQ (CCI_ENABLE_SNOOP_REQ | CCI_ENABLE_DVM_REQ)
  83. enum cci_ace_port_type {
  84. ACE_INVALID_PORT = 0x0,
  85. ACE_PORT,
  86. ACE_LITE_PORT,
  87. };
  88. struct cci_ace_port {
  89. void __iomem *base;
  90. unsigned long phys;
  91. enum cci_ace_port_type type;
  92. struct device_node *dn;
  93. };
  94. static struct cci_ace_port *ports;
  95. static unsigned int nb_cci_ports;
  96. struct cpu_port {
  97. u64 mpidr;
  98. u32 port;
  99. };
  100. /*
  101. * Use the port MSB as valid flag, shift can be made dynamic
  102. * by computing number of bits required for port indexes.
  103. * Code disabling CCI cpu ports runs with D-cache invalidated
  104. * and SCTLR bit clear so data accesses must be kept to a minimum
  105. * to improve performance; for now shift is left static to
  106. * avoid one more data access while disabling the CCI port.
  107. */
  108. #define PORT_VALID_SHIFT 31
  109. #define PORT_VALID (0x1 << PORT_VALID_SHIFT)
  110. static inline void init_cpu_port(struct cpu_port *port, u32 index, u64 mpidr)
  111. {
  112. port->port = PORT_VALID | index;
  113. port->mpidr = mpidr;
  114. }
  115. static inline bool cpu_port_is_valid(struct cpu_port *port)
  116. {
  117. return !!(port->port & PORT_VALID);
  118. }
  119. static inline bool cpu_port_match(struct cpu_port *port, u64 mpidr)
  120. {
  121. return port->mpidr == (mpidr & MPIDR_HWID_BITMASK);
  122. }
  123. static struct cpu_port cpu_port[NR_CPUS];
  124. /**
  125. * __cci_ace_get_port - Function to retrieve the port index connected to
  126. * a cpu or device.
  127. *
  128. * @dn: device node of the device to look-up
  129. * @type: port type
  130. *
  131. * Return value:
  132. * - CCI port index if success
  133. * - -ENODEV if failure
  134. */
  135. static int __cci_ace_get_port(struct device_node *dn, int type)
  136. {
  137. int i;
  138. bool ace_match;
  139. struct device_node *cci_portn;
  140. cci_portn = of_parse_phandle(dn, "cci-control-port", 0);
  141. for (i = 0; i < nb_cci_ports; i++) {
  142. ace_match = ports[i].type == type;
  143. if (ace_match && cci_portn == ports[i].dn)
  144. return i;
  145. }
  146. return -ENODEV;
  147. }
  148. int cci_ace_get_port(struct device_node *dn)
  149. {
  150. return __cci_ace_get_port(dn, ACE_LITE_PORT);
  151. }
  152. EXPORT_SYMBOL_GPL(cci_ace_get_port);
  153. static void cci_ace_init_ports(void)
  154. {
  155. int port, cpu;
  156. struct device_node *cpun;
  157. /*
  158. * Port index look-up speeds up the function disabling ports by CPU,
  159. * since the logical to port index mapping is done once and does
  160. * not change after system boot.
  161. * The stashed index array is initialized for all possible CPUs
  162. * at probe time.
  163. */
  164. for_each_possible_cpu(cpu) {
  165. /* too early to use cpu->of_node */
  166. cpun = of_get_cpu_node(cpu, NULL);
  167. if (WARN(!cpun, "Missing cpu device node\n"))
  168. continue;
  169. port = __cci_ace_get_port(cpun, ACE_PORT);
  170. if (port < 0)
  171. continue;
  172. init_cpu_port(&cpu_port[cpu], port, cpu_logical_map(cpu));
  173. }
  174. for_each_possible_cpu(cpu) {
  175. WARN(!cpu_port_is_valid(&cpu_port[cpu]),
  176. "CPU %u does not have an associated CCI port\n",
  177. cpu);
  178. }
  179. }
  180. /*
  181. * Functions to enable/disable a CCI interconnect slave port
  182. *
  183. * They are called by low-level power management code to disable slave
  184. * interfaces snoops and DVM broadcast.
  185. * Since they may execute with cache data allocation disabled and
  186. * after the caches have been cleaned and invalidated the functions provide
  187. * no explicit locking since they may run with D-cache disabled, so normal
  188. * cacheable kernel locks based on ldrex/strex may not work.
  189. * Locking has to be provided by BSP implementations to ensure proper
  190. * operations.
  191. */
  192. /**
  193. * cci_port_control() - function to control a CCI port
  194. *
  195. * @port: index of the port to setup
  196. * @enable: if true enables the port, if false disables it
  197. */
  198. static void notrace cci_port_control(unsigned int port, bool enable)
  199. {
  200. void __iomem *base = ports[port].base;
  201. writel_relaxed(enable ? CCI_ENABLE_REQ : 0, base + CCI_PORT_CTRL);
  202. /*
  203. * This function is called from power down procedures
  204. * and must not execute any instruction that might
  205. * cause the processor to be put in a quiescent state
  206. * (eg wfi). Hence, cpu_relax() can not be added to this
  207. * read loop to optimize power, since it might hide possibly
  208. * disruptive operations.
  209. */
  210. while (readl_relaxed(cci_ctrl_base + CCI_CTRL_STATUS) & 0x1)
  211. ;
  212. }
  213. /**
  214. * cci_disable_port_by_cpu() - function to disable a CCI port by CPU
  215. * reference
  216. *
  217. * @mpidr: mpidr of the CPU whose CCI port should be disabled
  218. *
  219. * Disabling a CCI port for a CPU implies disabling the CCI port
  220. * controlling that CPU cluster. Code disabling CPU CCI ports
  221. * must make sure that the CPU running the code is the last active CPU
  222. * in the cluster ie all other CPUs are quiescent in a low power state.
  223. *
  224. * Return:
  225. * 0 on success
  226. * -ENODEV on port look-up failure
  227. */
  228. int notrace cci_disable_port_by_cpu(u64 mpidr)
  229. {
  230. int cpu;
  231. bool is_valid;
  232. for (cpu = 0; cpu < nr_cpu_ids; cpu++) {
  233. is_valid = cpu_port_is_valid(&cpu_port[cpu]);
  234. if (is_valid && cpu_port_match(&cpu_port[cpu], mpidr)) {
  235. cci_port_control(cpu_port[cpu].port, false);
  236. return 0;
  237. }
  238. }
  239. return -ENODEV;
  240. }
  241. EXPORT_SYMBOL_GPL(cci_disable_port_by_cpu);
  242. /**
  243. * cci_enable_port_for_self() - enable a CCI port for calling CPU
  244. *
  245. * Enabling a CCI port for the calling CPU implies enabling the CCI
  246. * port controlling that CPU's cluster. Caller must make sure that the
  247. * CPU running the code is the first active CPU in the cluster and all
  248. * other CPUs are quiescent in a low power state or waiting for this CPU
  249. * to complete the CCI initialization.
  250. *
  251. * Because this is called when the MMU is still off and with no stack,
  252. * the code must be position independent and ideally rely on callee
  253. * clobbered registers only. To achieve this we must code this function
  254. * entirely in assembler.
  255. *
  256. * On success this returns with the proper CCI port enabled. In case of
  257. * any failure this never returns as the inability to enable the CCI is
  258. * fatal and there is no possible recovery at this stage.
  259. */
  260. asmlinkage void __naked cci_enable_port_for_self(void)
  261. {
  262. asm volatile ("\n"
  263. " .arch armv7-a\n"
  264. " mrc p15, 0, r0, c0, c0, 5 @ get MPIDR value \n"
  265. " and r0, r0, #"__stringify(MPIDR_HWID_BITMASK)" \n"
  266. " adr r1, 5f \n"
  267. " ldr r2, [r1] \n"
  268. " add r1, r1, r2 @ &cpu_port \n"
  269. " add ip, r1, %[sizeof_cpu_port] \n"
  270. /* Loop over the cpu_port array looking for a matching MPIDR */
  271. "1: ldr r2, [r1, %[offsetof_cpu_port_mpidr_lsb]] \n"
  272. " cmp r2, r0 @ compare MPIDR \n"
  273. " bne 2f \n"
  274. /* Found a match, now test port validity */
  275. " ldr r3, [r1, %[offsetof_cpu_port_port]] \n"
  276. " tst r3, #"__stringify(PORT_VALID)" \n"
  277. " bne 3f \n"
  278. /* no match, loop with the next cpu_port entry */
  279. "2: add r1, r1, %[sizeof_struct_cpu_port] \n"
  280. " cmp r1, ip @ done? \n"
  281. " blo 1b \n"
  282. /* CCI port not found -- cheaply try to stall this CPU */
  283. "cci_port_not_found: \n"
  284. " wfi \n"
  285. " wfe \n"
  286. " b cci_port_not_found \n"
  287. /* Use matched port index to look up the corresponding ports entry */
  288. "3: bic r3, r3, #"__stringify(PORT_VALID)" \n"
  289. " adr r0, 6f \n"
  290. " ldmia r0, {r1, r2} \n"
  291. " sub r1, r1, r0 @ virt - phys \n"
  292. " ldr r0, [r0, r2] @ *(&ports) \n"
  293. " mov r2, %[sizeof_struct_ace_port] \n"
  294. " mla r0, r2, r3, r0 @ &ports[index] \n"
  295. " sub r0, r0, r1 @ virt_to_phys() \n"
  296. /* Enable the CCI port */
  297. " ldr r0, [r0, %[offsetof_port_phys]] \n"
  298. " mov r3, %[cci_enable_req]\n"
  299. " str r3, [r0, #"__stringify(CCI_PORT_CTRL)"] \n"
  300. /* poll the status reg for completion */
  301. " adr r1, 7f \n"
  302. " ldr r0, [r1] \n"
  303. " ldr r0, [r0, r1] @ cci_ctrl_base \n"
  304. "4: ldr r1, [r0, #"__stringify(CCI_CTRL_STATUS)"] \n"
  305. " tst r1, %[cci_control_status_bits] \n"
  306. " bne 4b \n"
  307. " mov r0, #0 \n"
  308. " bx lr \n"
  309. " .align 2 \n"
  310. "5: .word cpu_port - . \n"
  311. "6: .word . \n"
  312. " .word ports - 6b \n"
  313. "7: .word cci_ctrl_phys - . \n"
  314. : :
  315. [sizeof_cpu_port] "i" (sizeof(cpu_port)),
  316. [cci_enable_req] "i" cpu_to_le32(CCI_ENABLE_REQ),
  317. [cci_control_status_bits] "i" cpu_to_le32(1),
  318. #ifndef __ARMEB__
  319. [offsetof_cpu_port_mpidr_lsb] "i" (offsetof(struct cpu_port, mpidr)),
  320. #else
  321. [offsetof_cpu_port_mpidr_lsb] "i" (offsetof(struct cpu_port, mpidr)+4),
  322. #endif
  323. [offsetof_cpu_port_port] "i" (offsetof(struct cpu_port, port)),
  324. [sizeof_struct_cpu_port] "i" (sizeof(struct cpu_port)),
  325. [sizeof_struct_ace_port] "i" (sizeof(struct cci_ace_port)),
  326. [offsetof_port_phys] "i" (offsetof(struct cci_ace_port, phys)) );
  327. }
  328. /**
  329. * __cci_control_port_by_device() - function to control a CCI port by device
  330. * reference
  331. *
  332. * @dn: device node pointer of the device whose CCI port should be
  333. * controlled
  334. * @enable: if true enables the port, if false disables it
  335. *
  336. * Return:
  337. * 0 on success
  338. * -ENODEV on port look-up failure
  339. */
  340. int notrace __cci_control_port_by_device(struct device_node *dn, bool enable)
  341. {
  342. int port;
  343. if (!dn)
  344. return -ENODEV;
  345. port = __cci_ace_get_port(dn, ACE_LITE_PORT);
  346. if (WARN_ONCE(port < 0, "node %pOF ACE lite port look-up failure\n",
  347. dn))
  348. return -ENODEV;
  349. cci_port_control(port, enable);
  350. return 0;
  351. }
  352. EXPORT_SYMBOL_GPL(__cci_control_port_by_device);
  353. /**
  354. * __cci_control_port_by_index() - function to control a CCI port by port index
  355. *
  356. * @port: port index previously retrieved with cci_ace_get_port()
  357. * @enable: if true enables the port, if false disables it
  358. *
  359. * Return:
  360. * 0 on success
  361. * -ENODEV on port index out of range
  362. * -EPERM if operation carried out on an ACE PORT
  363. */
  364. int notrace __cci_control_port_by_index(u32 port, bool enable)
  365. {
  366. if (port >= nb_cci_ports || ports[port].type == ACE_INVALID_PORT)
  367. return -ENODEV;
  368. /*
  369. * CCI control for ports connected to CPUS is extremely fragile
  370. * and must be made to go through a specific and controlled
  371. * interface (ie cci_disable_port_by_cpu(); control by general purpose
  372. * indexing is therefore disabled for ACE ports.
  373. */
  374. if (ports[port].type == ACE_PORT)
  375. return -EPERM;
  376. cci_port_control(port, enable);
  377. return 0;
  378. }
  379. EXPORT_SYMBOL_GPL(__cci_control_port_by_index);
  380. static const struct of_device_id arm_cci_ctrl_if_matches[] = {
  381. {.compatible = "arm,cci-400-ctrl-if", },
  382. {},
  383. };
  384. static int cci_probe_ports(struct device_node *np)
  385. {
  386. struct cci_nb_ports const *cci_config;
  387. int ret, i, nb_ace = 0, nb_ace_lite = 0;
  388. struct device_node *cp;
  389. struct resource res;
  390. const char *match_str;
  391. bool is_ace;
  392. cci_config = of_match_node(arm_cci_matches, np)->data;
  393. if (!cci_config)
  394. return -ENODEV;
  395. nb_cci_ports = cci_config->nb_ace + cci_config->nb_ace_lite;
  396. ports = kcalloc(nb_cci_ports, sizeof(*ports), GFP_KERNEL);
  397. if (!ports)
  398. return -ENOMEM;
  399. for_each_available_child_of_node(np, cp) {
  400. if (!of_match_node(arm_cci_ctrl_if_matches, cp))
  401. continue;
  402. i = nb_ace + nb_ace_lite;
  403. if (i >= nb_cci_ports)
  404. break;
  405. if (of_property_read_string(cp, "interface-type",
  406. &match_str)) {
  407. WARN(1, "node %pOF missing interface-type property\n",
  408. cp);
  409. continue;
  410. }
  411. is_ace = strcmp(match_str, "ace") == 0;
  412. if (!is_ace && strcmp(match_str, "ace-lite")) {
  413. WARN(1, "node %pOF containing invalid interface-type property, skipping it\n",
  414. cp);
  415. continue;
  416. }
  417. ret = of_address_to_resource(cp, 0, &res);
  418. if (!ret) {
  419. ports[i].base = ioremap(res.start, resource_size(&res));
  420. ports[i].phys = res.start;
  421. }
  422. if (ret || !ports[i].base) {
  423. WARN(1, "unable to ioremap CCI port %d\n", i);
  424. continue;
  425. }
  426. if (is_ace) {
  427. if (WARN_ON(nb_ace >= cci_config->nb_ace))
  428. continue;
  429. ports[i].type = ACE_PORT;
  430. ++nb_ace;
  431. } else {
  432. if (WARN_ON(nb_ace_lite >= cci_config->nb_ace_lite))
  433. continue;
  434. ports[i].type = ACE_LITE_PORT;
  435. ++nb_ace_lite;
  436. }
  437. ports[i].dn = cp;
  438. }
  439. /*
  440. * If there is no CCI port that is under kernel control
  441. * return early and report probe status.
  442. */
  443. if (!nb_ace && !nb_ace_lite)
  444. return -ENODEV;
  445. /* initialize a stashed array of ACE ports to speed-up look-up */
  446. cci_ace_init_ports();
  447. /*
  448. * Multi-cluster systems may need this data when non-coherent, during
  449. * cluster power-up/power-down. Make sure it reaches main memory.
  450. */
  451. sync_cache_w(&cci_ctrl_base);
  452. sync_cache_w(&cci_ctrl_phys);
  453. sync_cache_w(&ports);
  454. sync_cache_w(&cpu_port);
  455. __sync_cache_range_w(ports, sizeof(*ports) * nb_cci_ports);
  456. pr_info("ARM CCI driver probed\n");
  457. return 0;
  458. }
  459. #else /* !CONFIG_ARM_CCI400_PORT_CTRL */
  460. static inline int cci_probe_ports(struct device_node *np)
  461. {
  462. return 0;
  463. }
  464. #endif /* CONFIG_ARM_CCI400_PORT_CTRL */
  465. static int cci_probe(void)
  466. {
  467. int ret;
  468. struct device_node *np;
  469. struct resource res;
  470. np = of_find_matching_node(NULL, arm_cci_matches);
  471. if (!of_device_is_available(np))
  472. return -ENODEV;
  473. ret = of_address_to_resource(np, 0, &res);
  474. if (!ret) {
  475. cci_ctrl_base = ioremap(res.start, resource_size(&res));
  476. cci_ctrl_phys = res.start;
  477. }
  478. if (ret || !cci_ctrl_base) {
  479. WARN(1, "unable to ioremap CCI ctrl\n");
  480. return -ENXIO;
  481. }
  482. return cci_probe_ports(np);
  483. }
  484. static int cci_init_status = -EAGAIN;
  485. static DEFINE_MUTEX(cci_probing);
  486. static int cci_init(void)
  487. {
  488. if (cci_init_status != -EAGAIN)
  489. return cci_init_status;
  490. mutex_lock(&cci_probing);
  491. if (cci_init_status == -EAGAIN)
  492. cci_init_status = cci_probe();
  493. mutex_unlock(&cci_probing);
  494. return cci_init_status;
  495. }
  496. /*
  497. * To sort out early init calls ordering a helper function is provided to
  498. * check if the CCI driver has beed initialized. Function check if the driver
  499. * has been initialized, if not it calls the init function that probes
  500. * the driver and updates the return value.
  501. */
  502. bool cci_probed(void)
  503. {
  504. return cci_init() == 0;
  505. }
  506. EXPORT_SYMBOL_GPL(cci_probed);
  507. early_initcall(cci_init);
  508. core_initcall(cci_platform_init);
  509. MODULE_LICENSE("GPL");
  510. MODULE_DESCRIPTION("ARM CCI support");