horizon.h 16 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. Madge Horizon ATM Adapter driver.
  4. Copyright (C) 1995-1999 Madge Networks Ltd.
  5. */
  6. /*
  7. IMPORTANT NOTE: Madge Networks no longer makes the adapters
  8. supported by this driver and makes no commitment to maintain it.
  9. */
  10. /* too many macros - change to inline functions */
  11. #ifndef DRIVER_ATM_HORIZON_H
  12. #define DRIVER_ATM_HORIZON_H
  13. #ifdef CONFIG_ATM_HORIZON_DEBUG
  14. #define DEBUG_HORIZON
  15. #endif
  16. #define DEV_LABEL "hrz"
  17. #ifndef PCI_VENDOR_ID_MADGE
  18. #define PCI_VENDOR_ID_MADGE 0x10B6
  19. #endif
  20. #ifndef PCI_DEVICE_ID_MADGE_HORIZON
  21. #define PCI_DEVICE_ID_MADGE_HORIZON 0x1000
  22. #endif
  23. // diagnostic output
  24. #define PRINTK(severity,format,args...) \
  25. printk(severity DEV_LABEL ": " format "\n" , ## args)
  26. #ifdef DEBUG_HORIZON
  27. #define DBG_ERR 0x0001
  28. #define DBG_WARN 0x0002
  29. #define DBG_INFO 0x0004
  30. #define DBG_VCC 0x0008
  31. #define DBG_QOS 0x0010
  32. #define DBG_TX 0x0020
  33. #define DBG_RX 0x0040
  34. #define DBG_SKB 0x0080
  35. #define DBG_IRQ 0x0100
  36. #define DBG_FLOW 0x0200
  37. #define DBG_BUS 0x0400
  38. #define DBG_REGS 0x0800
  39. #define DBG_DATA 0x1000
  40. #define DBG_MASK 0x1fff
  41. /* the ## prevents the annoying double expansion of the macro arguments */
  42. /* KERN_INFO is used since KERN_DEBUG often does not make it to the console */
  43. #define PRINTDB(bits,format,args...) \
  44. ( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format , ## args) : 1 )
  45. #define PRINTDM(bits,format,args...) \
  46. ( (debug & (bits)) ? printk (format , ## args) : 1 )
  47. #define PRINTDE(bits,format,args...) \
  48. ( (debug & (bits)) ? printk (format "\n" , ## args) : 1 )
  49. #define PRINTD(bits,format,args...) \
  50. ( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format "\n" , ## args) : 1 )
  51. #else
  52. #define PRINTD(bits,format,args...)
  53. #define PRINTDB(bits,format,args...)
  54. #define PRINTDM(bits,format,args...)
  55. #define PRINTDE(bits,format,args...)
  56. #endif
  57. #define PRINTDD(sec,fmt,args...)
  58. #define PRINTDDB(sec,fmt,args...)
  59. #define PRINTDDM(sec,fmt,args...)
  60. #define PRINTDDE(sec,fmt,args...)
  61. // fixed constants
  62. #define SPARE_BUFFER_POOL_SIZE MAX_VCS
  63. #define HRZ_MAX_VPI 4
  64. #define MIN_PCI_LATENCY 48 // 24 IS TOO SMALL
  65. /* Horizon specific bits */
  66. /* Register offsets */
  67. #define HRZ_IO_EXTENT 0x80
  68. #define DATA_PORT_OFF 0x00
  69. #define TX_CHANNEL_PORT_OFF 0x04
  70. #define TX_DESCRIPTOR_PORT_OFF 0x08
  71. #define MEMORY_PORT_OFF 0x0C
  72. #define MEM_WR_ADDR_REG_OFF 0x14
  73. #define MEM_RD_ADDR_REG_OFF 0x18
  74. #define CONTROL_0_REG 0x1C
  75. #define INT_SOURCE_REG_OFF 0x20
  76. #define INT_ENABLE_REG_OFF 0x24
  77. #define MASTER_RX_ADDR_REG_OFF 0x28
  78. #define MASTER_RX_COUNT_REG_OFF 0x2C
  79. #define MASTER_TX_ADDR_REG_OFF 0x30
  80. #define MASTER_TX_COUNT_REG_OFF 0x34
  81. #define TX_DESCRIPTOR_REG_OFF 0x38
  82. #define TX_CHANNEL_CONFIG_COMMAND_OFF 0x40
  83. #define TX_CHANNEL_CONFIG_DATA_OFF 0x44
  84. #define TX_FREE_BUFFER_COUNT_OFF 0x48
  85. #define RX_FREE_BUFFER_COUNT_OFF 0x4C
  86. #define TX_CONFIG_OFF 0x50
  87. #define TX_STATUS_OFF 0x54
  88. #define RX_CONFIG_OFF 0x58
  89. #define RX_LINE_CONFIG_OFF 0x5C
  90. #define RX_QUEUE_RD_PTR_OFF 0x60
  91. #define RX_QUEUE_WR_PTR_OFF 0x64
  92. #define MAX_AAL5_CELL_COUNT_OFF 0x68
  93. #define RX_CHANNEL_PORT_OFF 0x6C
  94. #define TX_CELL_COUNT_OFF 0x70
  95. #define RX_CELL_COUNT_OFF 0x74
  96. #define HEC_ERROR_COUNT_OFF 0x78
  97. #define UNASSIGNED_CELL_COUNT_OFF 0x7C
  98. /* Register bit definitions */
  99. /* Control 0 register */
  100. #define SEEPROM_DO 0x00000001
  101. #define SEEPROM_DI 0x00000002
  102. #define SEEPROM_SK 0x00000004
  103. #define SEEPROM_CS 0x00000008
  104. #define DEBUG_BIT_0 0x00000010
  105. #define DEBUG_BIT_1 0x00000020
  106. #define DEBUG_BIT_2 0x00000040
  107. // RESERVED 0x00000080
  108. #define DEBUG_BIT_0_OE 0x00000100
  109. #define DEBUG_BIT_1_OE 0x00000200
  110. #define DEBUG_BIT_2_OE 0x00000400
  111. // RESERVED 0x00000800
  112. #define DEBUG_BIT_0_STATE 0x00001000
  113. #define DEBUG_BIT_1_STATE 0x00002000
  114. #define DEBUG_BIT_2_STATE 0x00004000
  115. // RESERVED 0x00008000
  116. #define GENERAL_BIT_0 0x00010000
  117. #define GENERAL_BIT_1 0x00020000
  118. #define GENERAL_BIT_2 0x00040000
  119. #define GENERAL_BIT_3 0x00080000
  120. #define RESET_HORIZON 0x00100000
  121. #define RESET_ATM 0x00200000
  122. #define RESET_RX 0x00400000
  123. #define RESET_TX 0x00800000
  124. #define RESET_HOST 0x01000000
  125. // RESERVED 0x02000000
  126. #define TARGET_RETRY_DISABLE 0x04000000
  127. #define ATM_LAYER_SELECT 0x08000000
  128. #define ATM_LAYER_STATUS 0x10000000
  129. // RESERVED 0xE0000000
  130. /* Interrupt source and enable registers */
  131. #define RX_DATA_AV 0x00000001
  132. #define RX_DISABLED 0x00000002
  133. #define TIMING_MARKER 0x00000004
  134. #define FORCED 0x00000008
  135. #define RX_BUS_MASTER_COMPLETE 0x00000010
  136. #define TX_BUS_MASTER_COMPLETE 0x00000020
  137. #define ABR_TX_CELL_COUNT_INT 0x00000040
  138. #define DEBUG_INT 0x00000080
  139. // RESERVED 0xFFFFFF00
  140. /* PIO and Bus Mastering */
  141. #define MAX_PIO_COUNT 0x000000ff // 255 - make tunable?
  142. // 8188 is a hard limit for bus mastering
  143. #define MAX_TRANSFER_COUNT 0x00001ffc // 8188
  144. #define MASTER_TX_AUTO_APPEND_DESC 0x80000000
  145. /* TX channel config command port */
  146. #define PCR_TIMER_ACCESS 0x0000
  147. #define SCR_TIMER_ACCESS 0x0001
  148. #define BUCKET_CAPACITY_ACCESS 0x0002
  149. #define BUCKET_FULLNESS_ACCESS 0x0003
  150. #define RATE_TYPE_ACCESS 0x0004
  151. // UNUSED 0x00F8
  152. #define TX_CHANNEL_CONFIG_MULT 0x0100
  153. // UNUSED 0xF800
  154. #define BUCKET_MAX_SIZE 0x003f
  155. /* TX channel config data port */
  156. #define CLOCK_SELECT_SHIFT 4
  157. #define CLOCK_DISABLE 0x00ff
  158. #define IDLE_RATE_TYPE 0x0
  159. #define ABR_RATE_TYPE 0x1
  160. #define VBR_RATE_TYPE 0x2
  161. #define CBR_RATE_TYPE 0x3
  162. /* TX config register */
  163. #define DRVR_DRVRBAR_ENABLE 0x0001
  164. #define TXCLK_MUX_SELECT_RCLK 0x0002
  165. #define TRANSMIT_TIMING_MARKER 0x0004
  166. #define LOOPBACK_TIMING_MARKER 0x0008
  167. #define TX_TEST_MODE_16MHz 0x0000
  168. #define TX_TEST_MODE_8MHz 0x0010
  169. #define TX_TEST_MODE_5_33MHz 0x0020
  170. #define TX_TEST_MODE_4MHz 0x0030
  171. #define TX_TEST_MODE_3_2MHz 0x0040
  172. #define TX_TEST_MODE_2_66MHz 0x0050
  173. #define TX_TEST_MODE_2_29MHz 0x0060
  174. #define TX_NORMAL_OPERATION 0x0070
  175. #define ABR_ROUND_ROBIN 0x0080
  176. /* TX status register */
  177. #define IDLE_CHANNELS_MASK 0x00FF
  178. #define ABR_CELL_COUNT_REACHED_MULT 0x0100
  179. #define ABR_CELL_COUNT_REACHED_MASK 0xFF
  180. /* RX config register */
  181. #define NON_USER_CELLS_IN_ONE_CHANNEL 0x0008
  182. #define RX_ENABLE 0x0010
  183. #define IGNORE_UNUSED_VPI_VCI_BITS_SET 0x0000
  184. #define NON_USER_UNUSED_VPI_VCI_BITS_SET 0x0020
  185. #define DISCARD_UNUSED_VPI_VCI_BITS_SET 0x0040
  186. /* RX line config register */
  187. #define SIGNAL_LOSS 0x0001
  188. #define FREQUENCY_DETECT_ERROR 0x0002
  189. #define LOCK_DETECT_ERROR 0x0004
  190. #define SELECT_INTERNAL_LOOPBACK 0x0008
  191. #define LOCK_DETECT_ENABLE 0x0010
  192. #define FREQUENCY_DETECT_ENABLE 0x0020
  193. #define USER_FRAQ 0x0040
  194. #define GXTALOUT_SELECT_DIV4 0x0080
  195. #define GXTALOUT_SELECT_NO_GATING 0x0100
  196. #define TIMING_MARKER_RECEIVED 0x0200
  197. /* RX channel port */
  198. #define RX_CHANNEL_MASK 0x03FF
  199. // UNUSED 0x3C00
  200. #define FLUSH_CHANNEL 0x4000
  201. #define RX_CHANNEL_UPDATE_IN_PROGRESS 0x8000
  202. /* Receive queue entry */
  203. #define RX_Q_ENTRY_LENGTH_MASK 0x0000FFFF
  204. #define RX_Q_ENTRY_CHANNEL_SHIFT 16
  205. #define SIMONS_DODGEY_MARKER 0x08000000
  206. #define RX_CONGESTION_EXPERIENCED 0x10000000
  207. #define RX_CRC_10_OK 0x20000000
  208. #define RX_CRC_32_OK 0x40000000
  209. #define RX_COMPLETE_FRAME 0x80000000
  210. /* Offsets and constants for use with the buffer memory */
  211. /* Buffer pointers and channel types */
  212. #define BUFFER_PTR_MASK 0x0000FFFF
  213. #define RX_INT_THRESHOLD_MULT 0x00010000
  214. #define RX_INT_THRESHOLD_MASK 0x07FF
  215. #define INT_EVERY_N_CELLS 0x08000000
  216. #define CONGESTION_EXPERIENCED 0x10000000
  217. #define FIRST_CELL_OF_AAL5_FRAME 0x20000000
  218. #define CHANNEL_TYPE_AAL5 0x00000000
  219. #define CHANNEL_TYPE_RAW_CELLS 0x40000000
  220. #define CHANNEL_TYPE_AAL3_4 0x80000000
  221. /* Buffer status stuff */
  222. #define BUFF_STATUS_MASK 0x00030000
  223. #define BUFF_STATUS_EMPTY 0x00000000
  224. #define BUFF_STATUS_CELL_AV 0x00010000
  225. #define BUFF_STATUS_LAST_CELL_AV 0x00020000
  226. /* Transmit channel stuff */
  227. /* Receive channel stuff */
  228. #define RX_CHANNEL_DISABLED 0x00000000
  229. #define RX_CHANNEL_IDLE 0x00000001
  230. /* General things */
  231. #define INITIAL_CRC 0xFFFFFFFF
  232. // A Horizon u32, a byte! Really nasty. Horizon pointers are (32 bit)
  233. // word addresses and so standard C pointer operations break (as they
  234. // assume byte addresses); so we pretend that Horizon words (and word
  235. // pointers) are bytes (and byte pointers) for the purposes of having
  236. // a memory map that works.
  237. typedef u8 HDW;
  238. typedef struct cell_buf {
  239. HDW payload[12];
  240. HDW next;
  241. HDW cell_count; // AAL5 rx bufs
  242. HDW res;
  243. union {
  244. HDW partial_crc; // AAL5 rx bufs
  245. HDW cell_header; // RAW bufs
  246. } u;
  247. } cell_buf;
  248. typedef struct tx_ch_desc {
  249. HDW rd_buf_type;
  250. HDW wr_buf_type;
  251. HDW partial_crc;
  252. HDW cell_header;
  253. } tx_ch_desc;
  254. typedef struct rx_ch_desc {
  255. HDW wr_buf_type;
  256. HDW rd_buf_type;
  257. } rx_ch_desc;
  258. typedef struct rx_q_entry {
  259. HDW entry;
  260. } rx_q_entry;
  261. #define TX_CHANS 8
  262. #define RX_CHANS 1024
  263. #define RX_QS 1024
  264. #define MAX_VCS RX_CHANS
  265. /* Horizon buffer memory map */
  266. // TX Channel Descriptors 2
  267. // TX Initial Buffers 8 // TX_CHANS
  268. #define BUFN1_SIZE 118 // (126 - TX_CHANS)
  269. // RX/TX Start/End Buffers 4
  270. #define BUFN2_SIZE 124
  271. // RX Queue Entries 64
  272. #define BUFN3_SIZE 192
  273. // RX Channel Descriptors 128
  274. #define BUFN4_SIZE 1408
  275. // TOTAL cell_buff chunks 2048
  276. // cell_buf bufs[2048];
  277. // HDW dws[32768];
  278. typedef struct MEMMAP {
  279. tx_ch_desc tx_descs[TX_CHANS]; // 8 * 4 = 32 , 0x0020
  280. cell_buf inittxbufs[TX_CHANS]; // these are really
  281. cell_buf bufn1[BUFN1_SIZE]; // part of this pool
  282. cell_buf txfreebufstart;
  283. cell_buf txfreebufend;
  284. cell_buf rxfreebufstart;
  285. cell_buf rxfreebufend; // 8+118+1+1+1+1+124 = 254
  286. cell_buf bufn2[BUFN2_SIZE]; // 16 * 254 = 4064 , 0x1000
  287. rx_q_entry rx_q_entries[RX_QS]; // 1 * 1024 = 1024 , 0x1400
  288. cell_buf bufn3[BUFN3_SIZE]; // 16 * 192 = 3072 , 0x2000
  289. rx_ch_desc rx_descs[MAX_VCS]; // 2 * 1024 = 2048 , 0x2800
  290. cell_buf bufn4[BUFN4_SIZE]; // 16 * 1408 = 22528 , 0x8000
  291. } MEMMAP;
  292. #define memmap ((MEMMAP *)0)
  293. /* end horizon specific bits */
  294. typedef enum {
  295. aal0,
  296. aal34,
  297. aal5
  298. } hrz_aal;
  299. typedef enum {
  300. tx_busy,
  301. rx_busy,
  302. ultra
  303. } hrz_flags;
  304. // a single struct pointed to by atm_vcc->dev_data
  305. typedef struct {
  306. unsigned int tx_rate;
  307. unsigned int rx_rate;
  308. u16 channel;
  309. u16 tx_xbr_bits;
  310. u16 tx_pcr_bits;
  311. #if 0
  312. u16 tx_scr_bits;
  313. u16 tx_bucket_bits;
  314. #endif
  315. hrz_aal aal;
  316. } hrz_vcc;
  317. struct hrz_dev {
  318. u32 iobase;
  319. u32 * membase;
  320. struct sk_buff * rx_skb; // skb being RXed
  321. unsigned int rx_bytes; // bytes remaining to RX within region
  322. void * rx_addr; // addr to send bytes to (for PIO)
  323. unsigned int rx_channel; // channel that the skb is going out on
  324. struct sk_buff * tx_skb; // skb being TXed
  325. unsigned int tx_bytes; // bytes remaining to TX within region
  326. void * tx_addr; // addr to send bytes from (for PIO)
  327. struct iovec * tx_iovec; // remaining regions
  328. unsigned int tx_regions; // number of remaining regions
  329. spinlock_t mem_lock;
  330. wait_queue_head_t tx_queue;
  331. u8 irq;
  332. unsigned long flags;
  333. u8 tx_last;
  334. u8 tx_idle;
  335. rx_q_entry * rx_q_reset;
  336. rx_q_entry * rx_q_entry;
  337. rx_q_entry * rx_q_wrap;
  338. struct atm_dev * atm_dev;
  339. u32 last_vc;
  340. int noof_spare_buffers;
  341. u16 spare_buffers[SPARE_BUFFER_POOL_SIZE];
  342. u16 tx_channel_record[TX_CHANS];
  343. // this is what we follow when we get incoming data
  344. u32 txer[MAX_VCS/32];
  345. struct atm_vcc * rxer[MAX_VCS];
  346. // cell rate allocation
  347. spinlock_t rate_lock;
  348. unsigned int rx_avail;
  349. unsigned int tx_avail;
  350. // dev stats
  351. unsigned long tx_cell_count;
  352. unsigned long rx_cell_count;
  353. unsigned long hec_error_count;
  354. unsigned long unassigned_cell_count;
  355. struct pci_dev * pci_dev;
  356. struct timer_list housekeeping;
  357. };
  358. typedef struct hrz_dev hrz_dev;
  359. /* macros for use later */
  360. #define BUF_PTR(cbptr) ((cbptr) - (cell_buf *) 0)
  361. #define INTERESTING_INTERRUPTS \
  362. (RX_DATA_AV | RX_DISABLED | TX_BUS_MASTER_COMPLETE | RX_BUS_MASTER_COMPLETE)
  363. // 190 cells by default (192 TX buffers - 2 elbow room, see docs)
  364. #define TX_AAL5_LIMIT (190*ATM_CELL_PAYLOAD-ATM_AAL5_TRAILER) // 9112
  365. // Have enough RX buffers (unless we allow other buffer splits)
  366. #define RX_AAL5_LIMIT ATM_MAX_AAL5_PDU
  367. /* multi-statement macro protector */
  368. #define DW(x) do{ x } while(0)
  369. #define HRZ_DEV(atm_dev) ((hrz_dev *) (atm_dev)->dev_data)
  370. #define HRZ_VCC(atm_vcc) ((hrz_vcc *) (atm_vcc)->dev_data)
  371. /* Turn the LEDs on and off */
  372. // The LEDs bits are upside down in that setting the bit in the debug
  373. // register will turn the appropriate LED off.
  374. #define YELLOW_LED DEBUG_BIT_0
  375. #define GREEN_LED DEBUG_BIT_1
  376. #define YELLOW_LED_OE DEBUG_BIT_0_OE
  377. #define GREEN_LED_OE DEBUG_BIT_1_OE
  378. #define GREEN_LED_OFF(dev) \
  379. wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) | GREEN_LED)
  380. #define GREEN_LED_ON(dev) \
  381. wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) &~ GREEN_LED)
  382. #define YELLOW_LED_OFF(dev) \
  383. wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) | YELLOW_LED)
  384. #define YELLOW_LED_ON(dev) \
  385. wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) &~ YELLOW_LED)
  386. typedef enum {
  387. round_up,
  388. round_down,
  389. round_nearest
  390. } rounding;
  391. #endif /* DRIVER_ATM_HORIZON_H */