aspeed_wdt.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2016 IBM Corporation
  4. *
  5. * Joel Stanley <joel@jms.id.au>
  6. */
  7. #include <linux/delay.h>
  8. #include <linux/io.h>
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/of.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/watchdog.h>
  14. struct aspeed_wdt {
  15. struct watchdog_device wdd;
  16. void __iomem *base;
  17. u32 ctrl;
  18. };
  19. struct aspeed_wdt_config {
  20. u32 ext_pulse_width_mask;
  21. };
  22. static const struct aspeed_wdt_config ast2400_config = {
  23. .ext_pulse_width_mask = 0xff,
  24. };
  25. static const struct aspeed_wdt_config ast2500_config = {
  26. .ext_pulse_width_mask = 0xfffff,
  27. };
  28. static const struct of_device_id aspeed_wdt_of_table[] = {
  29. { .compatible = "aspeed,ast2400-wdt", .data = &ast2400_config },
  30. { .compatible = "aspeed,ast2500-wdt", .data = &ast2500_config },
  31. { .compatible = "aspeed,ast2600-wdt", .data = &ast2500_config },
  32. { },
  33. };
  34. MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table);
  35. #define WDT_STATUS 0x00
  36. #define WDT_RELOAD_VALUE 0x04
  37. #define WDT_RESTART 0x08
  38. #define WDT_CTRL 0x0C
  39. #define WDT_CTRL_BOOT_SECONDARY BIT(7)
  40. #define WDT_CTRL_RESET_MODE_SOC (0x00 << 5)
  41. #define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)
  42. #define WDT_CTRL_RESET_MODE_ARM_CPU (0x10 << 5)
  43. #define WDT_CTRL_1MHZ_CLK BIT(4)
  44. #define WDT_CTRL_WDT_EXT BIT(3)
  45. #define WDT_CTRL_WDT_INTR BIT(2)
  46. #define WDT_CTRL_RESET_SYSTEM BIT(1)
  47. #define WDT_CTRL_ENABLE BIT(0)
  48. #define WDT_TIMEOUT_STATUS 0x10
  49. #define WDT_TIMEOUT_STATUS_BOOT_SECONDARY BIT(1)
  50. #define WDT_CLEAR_TIMEOUT_STATUS 0x14
  51. #define WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION BIT(0)
  52. /*
  53. * WDT_RESET_WIDTH controls the characteristics of the external pulse (if
  54. * enabled), specifically:
  55. *
  56. * * Pulse duration
  57. * * Drive mode: push-pull vs open-drain
  58. * * Polarity: Active high or active low
  59. *
  60. * Pulse duration configuration is available on both the AST2400 and AST2500,
  61. * though the field changes between SoCs:
  62. *
  63. * AST2400: Bits 7:0
  64. * AST2500: Bits 19:0
  65. *
  66. * This difference is captured in struct aspeed_wdt_config.
  67. *
  68. * The AST2500 exposes the drive mode and polarity options, but not in a
  69. * regular fashion. For read purposes, bit 31 represents active high or low,
  70. * and bit 30 represents push-pull or open-drain. With respect to write, magic
  71. * values need to be written to the top byte to change the state of the drive
  72. * mode and polarity bits. Any other value written to the top byte has no
  73. * effect on the state of the drive mode or polarity bits. However, the pulse
  74. * width value must be preserved (as desired) if written.
  75. */
  76. #define WDT_RESET_WIDTH 0x18
  77. #define WDT_RESET_WIDTH_ACTIVE_HIGH BIT(31)
  78. #define WDT_ACTIVE_HIGH_MAGIC (0xA5 << 24)
  79. #define WDT_ACTIVE_LOW_MAGIC (0x5A << 24)
  80. #define WDT_RESET_WIDTH_PUSH_PULL BIT(30)
  81. #define WDT_PUSH_PULL_MAGIC (0xA8 << 24)
  82. #define WDT_OPEN_DRAIN_MAGIC (0x8A << 24)
  83. #define WDT_RESTART_MAGIC 0x4755
  84. /* 32 bits at 1MHz, in milliseconds */
  85. #define WDT_MAX_TIMEOUT_MS 4294967
  86. #define WDT_DEFAULT_TIMEOUT 30
  87. #define WDT_RATE_1MHZ 1000000
  88. static struct aspeed_wdt *to_aspeed_wdt(struct watchdog_device *wdd)
  89. {
  90. return container_of(wdd, struct aspeed_wdt, wdd);
  91. }
  92. static void aspeed_wdt_enable(struct aspeed_wdt *wdt, int count)
  93. {
  94. wdt->ctrl |= WDT_CTRL_ENABLE;
  95. writel(0, wdt->base + WDT_CTRL);
  96. writel(count, wdt->base + WDT_RELOAD_VALUE);
  97. writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
  98. writel(wdt->ctrl, wdt->base + WDT_CTRL);
  99. }
  100. static int aspeed_wdt_start(struct watchdog_device *wdd)
  101. {
  102. struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
  103. aspeed_wdt_enable(wdt, wdd->timeout * WDT_RATE_1MHZ);
  104. return 0;
  105. }
  106. static int aspeed_wdt_stop(struct watchdog_device *wdd)
  107. {
  108. struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
  109. wdt->ctrl &= ~WDT_CTRL_ENABLE;
  110. writel(wdt->ctrl, wdt->base + WDT_CTRL);
  111. return 0;
  112. }
  113. static int aspeed_wdt_ping(struct watchdog_device *wdd)
  114. {
  115. struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
  116. writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
  117. return 0;
  118. }
  119. static int aspeed_wdt_set_timeout(struct watchdog_device *wdd,
  120. unsigned int timeout)
  121. {
  122. struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
  123. u32 actual;
  124. wdd->timeout = timeout;
  125. actual = min(timeout, wdd->max_hw_heartbeat_ms / 1000);
  126. writel(actual * WDT_RATE_1MHZ, wdt->base + WDT_RELOAD_VALUE);
  127. writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
  128. return 0;
  129. }
  130. static int aspeed_wdt_restart(struct watchdog_device *wdd,
  131. unsigned long action, void *data)
  132. {
  133. struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
  134. wdt->ctrl &= ~WDT_CTRL_BOOT_SECONDARY;
  135. aspeed_wdt_enable(wdt, 128 * WDT_RATE_1MHZ / 1000);
  136. mdelay(1000);
  137. return 0;
  138. }
  139. /* access_cs0 shows if cs0 is accessible, hence the reverted bit */
  140. static ssize_t access_cs0_show(struct device *dev,
  141. struct device_attribute *attr, char *buf)
  142. {
  143. struct aspeed_wdt *wdt = dev_get_drvdata(dev);
  144. u32 status = readl(wdt->base + WDT_TIMEOUT_STATUS);
  145. return sprintf(buf, "%u\n",
  146. !(status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY));
  147. }
  148. static ssize_t access_cs0_store(struct device *dev,
  149. struct device_attribute *attr, const char *buf,
  150. size_t size)
  151. {
  152. struct aspeed_wdt *wdt = dev_get_drvdata(dev);
  153. unsigned long val;
  154. if (kstrtoul(buf, 10, &val))
  155. return -EINVAL;
  156. if (val)
  157. writel(WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION,
  158. wdt->base + WDT_CLEAR_TIMEOUT_STATUS);
  159. return size;
  160. }
  161. /*
  162. * This attribute exists only if the system has booted from the alternate
  163. * flash with 'alt-boot' option.
  164. *
  165. * At alternate flash the 'access_cs0' sysfs node provides:
  166. * ast2400: a way to get access to the primary SPI flash chip at CS0
  167. * after booting from the alternate chip at CS1.
  168. * ast2500: a way to restore the normal address mapping from
  169. * (CS0->CS1, CS1->CS0) to (CS0->CS0, CS1->CS1).
  170. *
  171. * Clearing the boot code selection and timeout counter also resets to the
  172. * initial state the chip select line mapping. When the SoC is in normal
  173. * mapping state (i.e. booted from CS0), clearing those bits does nothing for
  174. * both versions of the SoC. For alternate boot mode (booted from CS1 due to
  175. * wdt2 expiration) the behavior differs as described above.
  176. *
  177. * This option can be used with wdt2 (watchdog1) only.
  178. */
  179. static DEVICE_ATTR_RW(access_cs0);
  180. static struct attribute *bswitch_attrs[] = {
  181. &dev_attr_access_cs0.attr,
  182. NULL
  183. };
  184. ATTRIBUTE_GROUPS(bswitch);
  185. static const struct watchdog_ops aspeed_wdt_ops = {
  186. .start = aspeed_wdt_start,
  187. .stop = aspeed_wdt_stop,
  188. .ping = aspeed_wdt_ping,
  189. .set_timeout = aspeed_wdt_set_timeout,
  190. .restart = aspeed_wdt_restart,
  191. .owner = THIS_MODULE,
  192. };
  193. static const struct watchdog_info aspeed_wdt_info = {
  194. .options = WDIOF_KEEPALIVEPING
  195. | WDIOF_MAGICCLOSE
  196. | WDIOF_SETTIMEOUT,
  197. .identity = KBUILD_MODNAME,
  198. };
  199. static int aspeed_wdt_probe(struct platform_device *pdev)
  200. {
  201. struct device *dev = &pdev->dev;
  202. const struct aspeed_wdt_config *config;
  203. const struct of_device_id *ofdid;
  204. struct aspeed_wdt *wdt;
  205. struct device_node *np;
  206. const char *reset_type;
  207. u32 duration;
  208. u32 status;
  209. int ret;
  210. wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
  211. if (!wdt)
  212. return -ENOMEM;
  213. wdt->base = devm_platform_ioremap_resource(pdev, 0);
  214. if (IS_ERR(wdt->base))
  215. return PTR_ERR(wdt->base);
  216. wdt->wdd.info = &aspeed_wdt_info;
  217. wdt->wdd.ops = &aspeed_wdt_ops;
  218. wdt->wdd.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT_MS;
  219. wdt->wdd.parent = dev;
  220. wdt->wdd.timeout = WDT_DEFAULT_TIMEOUT;
  221. watchdog_init_timeout(&wdt->wdd, 0, dev);
  222. np = dev->of_node;
  223. ofdid = of_match_node(aspeed_wdt_of_table, np);
  224. if (!ofdid)
  225. return -EINVAL;
  226. config = ofdid->data;
  227. /*
  228. * On clock rates:
  229. * - ast2400 wdt can run at PCLK, or 1MHz
  230. * - ast2500 only runs at 1MHz, hard coding bit 4 to 1
  231. * - ast2600 always runs at 1MHz
  232. *
  233. * Set the ast2400 to run at 1MHz as it simplifies the driver.
  234. */
  235. if (of_device_is_compatible(np, "aspeed,ast2400-wdt"))
  236. wdt->ctrl = WDT_CTRL_1MHZ_CLK;
  237. /*
  238. * Control reset on a per-device basis to ensure the
  239. * host is not affected by a BMC reboot
  240. */
  241. ret = of_property_read_string(np, "aspeed,reset-type", &reset_type);
  242. if (ret) {
  243. wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | WDT_CTRL_RESET_SYSTEM;
  244. } else {
  245. if (!strcmp(reset_type, "cpu"))
  246. wdt->ctrl |= WDT_CTRL_RESET_MODE_ARM_CPU |
  247. WDT_CTRL_RESET_SYSTEM;
  248. else if (!strcmp(reset_type, "soc"))
  249. wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC |
  250. WDT_CTRL_RESET_SYSTEM;
  251. else if (!strcmp(reset_type, "system"))
  252. wdt->ctrl |= WDT_CTRL_RESET_MODE_FULL_CHIP |
  253. WDT_CTRL_RESET_SYSTEM;
  254. else if (strcmp(reset_type, "none"))
  255. return -EINVAL;
  256. }
  257. if (of_property_read_bool(np, "aspeed,external-signal"))
  258. wdt->ctrl |= WDT_CTRL_WDT_EXT;
  259. if (of_property_read_bool(np, "aspeed,alt-boot"))
  260. wdt->ctrl |= WDT_CTRL_BOOT_SECONDARY;
  261. if (readl(wdt->base + WDT_CTRL) & WDT_CTRL_ENABLE) {
  262. /*
  263. * The watchdog is running, but invoke aspeed_wdt_start() to
  264. * write wdt->ctrl to WDT_CTRL to ensure the watchdog's
  265. * configuration conforms to the driver's expectations.
  266. * Primarily, ensure we're using the 1MHz clock source.
  267. */
  268. aspeed_wdt_start(&wdt->wdd);
  269. set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
  270. }
  271. if ((of_device_is_compatible(np, "aspeed,ast2500-wdt")) ||
  272. (of_device_is_compatible(np, "aspeed,ast2600-wdt"))) {
  273. u32 reg = readl(wdt->base + WDT_RESET_WIDTH);
  274. reg &= config->ext_pulse_width_mask;
  275. if (of_property_read_bool(np, "aspeed,ext-push-pull"))
  276. reg |= WDT_PUSH_PULL_MAGIC;
  277. else
  278. reg |= WDT_OPEN_DRAIN_MAGIC;
  279. writel(reg, wdt->base + WDT_RESET_WIDTH);
  280. reg &= config->ext_pulse_width_mask;
  281. if (of_property_read_bool(np, "aspeed,ext-active-high"))
  282. reg |= WDT_ACTIVE_HIGH_MAGIC;
  283. else
  284. reg |= WDT_ACTIVE_LOW_MAGIC;
  285. writel(reg, wdt->base + WDT_RESET_WIDTH);
  286. }
  287. if (!of_property_read_u32(np, "aspeed,ext-pulse-duration", &duration)) {
  288. u32 max_duration = config->ext_pulse_width_mask + 1;
  289. if (duration == 0 || duration > max_duration) {
  290. dev_err(dev, "Invalid pulse duration: %uus\n",
  291. duration);
  292. duration = max(1U, min(max_duration, duration));
  293. dev_info(dev, "Pulse duration set to %uus\n",
  294. duration);
  295. }
  296. /*
  297. * The watchdog is always configured with a 1MHz source, so
  298. * there is no need to scale the microsecond value. However we
  299. * need to offset it - from the datasheet:
  300. *
  301. * "This register decides the asserting duration of wdt_ext and
  302. * wdt_rstarm signal. The default value is 0xFF. It means the
  303. * default asserting duration of wdt_ext and wdt_rstarm is
  304. * 256us."
  305. *
  306. * This implies a value of 0 gives a 1us pulse.
  307. */
  308. writel(duration - 1, wdt->base + WDT_RESET_WIDTH);
  309. }
  310. status = readl(wdt->base + WDT_TIMEOUT_STATUS);
  311. if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY) {
  312. wdt->wdd.bootstatus = WDIOF_CARDRESET;
  313. if (of_device_is_compatible(np, "aspeed,ast2400-wdt") ||
  314. of_device_is_compatible(np, "aspeed,ast2500-wdt"))
  315. wdt->wdd.groups = bswitch_groups;
  316. }
  317. dev_set_drvdata(dev, wdt);
  318. return devm_watchdog_register_device(dev, &wdt->wdd);
  319. }
  320. static struct platform_driver aspeed_watchdog_driver = {
  321. .probe = aspeed_wdt_probe,
  322. .driver = {
  323. .name = KBUILD_MODNAME,
  324. .of_match_table = of_match_ptr(aspeed_wdt_of_table),
  325. },
  326. };
  327. static int __init aspeed_wdt_init(void)
  328. {
  329. return platform_driver_register(&aspeed_watchdog_driver);
  330. }
  331. arch_initcall(aspeed_wdt_init);
  332. static void __exit aspeed_wdt_exit(void)
  333. {
  334. platform_driver_unregister(&aspeed_watchdog_driver);
  335. }
  336. module_exit(aspeed_wdt_exit);
  337. MODULE_DESCRIPTION("Aspeed Watchdog Driver");
  338. MODULE_LICENSE("GPL");