timbuart.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * timbuart.c timberdale FPGA UART driver
  4. * Copyright (c) 2009 Intel Corporation
  5. */
  6. /* Supports:
  7. * Timberdale FPGA UART
  8. */
  9. #include <linux/pci.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/serial_core.h>
  12. #include <linux/tty.h>
  13. #include <linux/tty_flip.h>
  14. #include <linux/kernel.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/ioport.h>
  17. #include <linux/slab.h>
  18. #include <linux/module.h>
  19. #include "timbuart.h"
  20. struct timbuart_port {
  21. struct uart_port port;
  22. struct tasklet_struct tasklet;
  23. int usedma;
  24. u32 last_ier;
  25. struct platform_device *dev;
  26. };
  27. static int baudrates[] = {9600, 19200, 38400, 57600, 115200, 230400, 460800,
  28. 921600, 1843200, 3250000};
  29. static void timbuart_mctrl_check(struct uart_port *port, u32 isr, u32 *ier);
  30. static irqreturn_t timbuart_handleinterrupt(int irq, void *devid);
  31. static void timbuart_stop_rx(struct uart_port *port)
  32. {
  33. /* spin lock held by upper layer, disable all RX interrupts */
  34. u32 ier = ioread32(port->membase + TIMBUART_IER) & ~RXFLAGS;
  35. iowrite32(ier, port->membase + TIMBUART_IER);
  36. }
  37. static void timbuart_stop_tx(struct uart_port *port)
  38. {
  39. /* spinlock held by upper layer, disable TX interrupt */
  40. u32 ier = ioread32(port->membase + TIMBUART_IER) & ~TXBAE;
  41. iowrite32(ier, port->membase + TIMBUART_IER);
  42. }
  43. static void timbuart_start_tx(struct uart_port *port)
  44. {
  45. struct timbuart_port *uart =
  46. container_of(port, struct timbuart_port, port);
  47. /* do not transfer anything here -> fire off the tasklet */
  48. tasklet_schedule(&uart->tasklet);
  49. }
  50. static unsigned int timbuart_tx_empty(struct uart_port *port)
  51. {
  52. u32 isr = ioread32(port->membase + TIMBUART_ISR);
  53. return (isr & TXBE) ? TIOCSER_TEMT : 0;
  54. }
  55. static void timbuart_flush_buffer(struct uart_port *port)
  56. {
  57. if (!timbuart_tx_empty(port)) {
  58. u8 ctl = ioread8(port->membase + TIMBUART_CTRL) |
  59. TIMBUART_CTRL_FLSHTX;
  60. iowrite8(ctl, port->membase + TIMBUART_CTRL);
  61. iowrite32(TXBF, port->membase + TIMBUART_ISR);
  62. }
  63. }
  64. static void timbuart_rx_chars(struct uart_port *port)
  65. {
  66. struct tty_port *tport = &port->state->port;
  67. while (ioread32(port->membase + TIMBUART_ISR) & RXDP) {
  68. u8 ch = ioread8(port->membase + TIMBUART_RXFIFO);
  69. port->icount.rx++;
  70. tty_insert_flip_char(tport, ch, TTY_NORMAL);
  71. }
  72. spin_unlock(&port->lock);
  73. tty_flip_buffer_push(tport);
  74. spin_lock(&port->lock);
  75. dev_dbg(port->dev, "%s - total read %d bytes\n",
  76. __func__, port->icount.rx);
  77. }
  78. static void timbuart_tx_chars(struct uart_port *port)
  79. {
  80. struct circ_buf *xmit = &port->state->xmit;
  81. while (!(ioread32(port->membase + TIMBUART_ISR) & TXBF) &&
  82. !uart_circ_empty(xmit)) {
  83. iowrite8(xmit->buf[xmit->tail],
  84. port->membase + TIMBUART_TXFIFO);
  85. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  86. port->icount.tx++;
  87. }
  88. dev_dbg(port->dev,
  89. "%s - total written %d bytes, CTL: %x, RTS: %x, baud: %x\n",
  90. __func__,
  91. port->icount.tx,
  92. ioread8(port->membase + TIMBUART_CTRL),
  93. port->mctrl & TIOCM_RTS,
  94. ioread8(port->membase + TIMBUART_BAUDRATE));
  95. }
  96. static void timbuart_handle_tx_port(struct uart_port *port, u32 isr, u32 *ier)
  97. {
  98. struct timbuart_port *uart =
  99. container_of(port, struct timbuart_port, port);
  100. struct circ_buf *xmit = &port->state->xmit;
  101. if (uart_circ_empty(xmit) || uart_tx_stopped(port))
  102. return;
  103. if (port->x_char)
  104. return;
  105. if (isr & TXFLAGS) {
  106. timbuart_tx_chars(port);
  107. /* clear all TX interrupts */
  108. iowrite32(TXFLAGS, port->membase + TIMBUART_ISR);
  109. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  110. uart_write_wakeup(port);
  111. } else
  112. /* Re-enable any tx interrupt */
  113. *ier |= uart->last_ier & TXFLAGS;
  114. /* enable interrupts if there are chars in the transmit buffer,
  115. * Or if we delivered some bytes and want the almost empty interrupt
  116. * we wake up the upper layer later when we got the interrupt
  117. * to give it some time to go out...
  118. */
  119. if (!uart_circ_empty(xmit))
  120. *ier |= TXBAE;
  121. dev_dbg(port->dev, "%s - leaving\n", __func__);
  122. }
  123. static void timbuart_handle_rx_port(struct uart_port *port, u32 isr, u32 *ier)
  124. {
  125. if (isr & RXFLAGS) {
  126. /* Some RX status is set */
  127. if (isr & RXBF) {
  128. u8 ctl = ioread8(port->membase + TIMBUART_CTRL) |
  129. TIMBUART_CTRL_FLSHRX;
  130. iowrite8(ctl, port->membase + TIMBUART_CTRL);
  131. port->icount.overrun++;
  132. } else if (isr & (RXDP))
  133. timbuart_rx_chars(port);
  134. /* ack all RX interrupts */
  135. iowrite32(RXFLAGS, port->membase + TIMBUART_ISR);
  136. }
  137. /* always have the RX interrupts enabled */
  138. *ier |= RXBAF | RXBF | RXTT;
  139. dev_dbg(port->dev, "%s - leaving\n", __func__);
  140. }
  141. static void timbuart_tasklet(unsigned long arg)
  142. {
  143. struct timbuart_port *uart = (struct timbuart_port *)arg;
  144. u32 isr, ier = 0;
  145. spin_lock(&uart->port.lock);
  146. isr = ioread32(uart->port.membase + TIMBUART_ISR);
  147. dev_dbg(uart->port.dev, "%s ISR: %x\n", __func__, isr);
  148. if (!uart->usedma)
  149. timbuart_handle_tx_port(&uart->port, isr, &ier);
  150. timbuart_mctrl_check(&uart->port, isr, &ier);
  151. if (!uart->usedma)
  152. timbuart_handle_rx_port(&uart->port, isr, &ier);
  153. iowrite32(ier, uart->port.membase + TIMBUART_IER);
  154. spin_unlock(&uart->port.lock);
  155. dev_dbg(uart->port.dev, "%s leaving\n", __func__);
  156. }
  157. static unsigned int timbuart_get_mctrl(struct uart_port *port)
  158. {
  159. u8 cts = ioread8(port->membase + TIMBUART_CTRL);
  160. dev_dbg(port->dev, "%s - cts %x\n", __func__, cts);
  161. if (cts & TIMBUART_CTRL_CTS)
  162. return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
  163. else
  164. return TIOCM_DSR | TIOCM_CAR;
  165. }
  166. static void timbuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
  167. {
  168. dev_dbg(port->dev, "%s - %x\n", __func__, mctrl);
  169. if (mctrl & TIOCM_RTS)
  170. iowrite8(TIMBUART_CTRL_RTS, port->membase + TIMBUART_CTRL);
  171. else
  172. iowrite8(0, port->membase + TIMBUART_CTRL);
  173. }
  174. static void timbuart_mctrl_check(struct uart_port *port, u32 isr, u32 *ier)
  175. {
  176. unsigned int cts;
  177. if (isr & CTS_DELTA) {
  178. /* ack */
  179. iowrite32(CTS_DELTA, port->membase + TIMBUART_ISR);
  180. cts = timbuart_get_mctrl(port);
  181. uart_handle_cts_change(port, cts & TIOCM_CTS);
  182. wake_up_interruptible(&port->state->port.delta_msr_wait);
  183. }
  184. *ier |= CTS_DELTA;
  185. }
  186. static void timbuart_break_ctl(struct uart_port *port, int ctl)
  187. {
  188. /* N/A */
  189. }
  190. static int timbuart_startup(struct uart_port *port)
  191. {
  192. struct timbuart_port *uart =
  193. container_of(port, struct timbuart_port, port);
  194. dev_dbg(port->dev, "%s\n", __func__);
  195. iowrite8(TIMBUART_CTRL_FLSHRX, port->membase + TIMBUART_CTRL);
  196. iowrite32(0x1ff, port->membase + TIMBUART_ISR);
  197. /* Enable all but TX interrupts */
  198. iowrite32(RXBAF | RXBF | RXTT | CTS_DELTA,
  199. port->membase + TIMBUART_IER);
  200. return request_irq(port->irq, timbuart_handleinterrupt, IRQF_SHARED,
  201. "timb-uart", uart);
  202. }
  203. static void timbuart_shutdown(struct uart_port *port)
  204. {
  205. struct timbuart_port *uart =
  206. container_of(port, struct timbuart_port, port);
  207. dev_dbg(port->dev, "%s\n", __func__);
  208. free_irq(port->irq, uart);
  209. iowrite32(0, port->membase + TIMBUART_IER);
  210. timbuart_flush_buffer(port);
  211. }
  212. static int get_bindex(int baud)
  213. {
  214. int i;
  215. for (i = 0; i < ARRAY_SIZE(baudrates); i++)
  216. if (baud <= baudrates[i])
  217. return i;
  218. return -1;
  219. }
  220. static void timbuart_set_termios(struct uart_port *port,
  221. struct ktermios *termios,
  222. struct ktermios *old)
  223. {
  224. unsigned int baud;
  225. short bindex;
  226. unsigned long flags;
  227. baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
  228. bindex = get_bindex(baud);
  229. dev_dbg(port->dev, "%s - bindex %d\n", __func__, bindex);
  230. if (bindex < 0)
  231. bindex = 0;
  232. baud = baudrates[bindex];
  233. /* The serial layer calls into this once with old = NULL when setting
  234. up initially */
  235. if (old)
  236. tty_termios_copy_hw(termios, old);
  237. tty_termios_encode_baud_rate(termios, baud, baud);
  238. spin_lock_irqsave(&port->lock, flags);
  239. iowrite8((u8)bindex, port->membase + TIMBUART_BAUDRATE);
  240. uart_update_timeout(port, termios->c_cflag, baud);
  241. spin_unlock_irqrestore(&port->lock, flags);
  242. }
  243. static const char *timbuart_type(struct uart_port *port)
  244. {
  245. return port->type == PORT_UNKNOWN ? "timbuart" : NULL;
  246. }
  247. /* We do not request/release mappings of the registers here,
  248. * currently it's done in the proble function.
  249. */
  250. static void timbuart_release_port(struct uart_port *port)
  251. {
  252. struct platform_device *pdev = to_platform_device(port->dev);
  253. int size =
  254. resource_size(platform_get_resource(pdev, IORESOURCE_MEM, 0));
  255. if (port->flags & UPF_IOREMAP) {
  256. iounmap(port->membase);
  257. port->membase = NULL;
  258. }
  259. release_mem_region(port->mapbase, size);
  260. }
  261. static int timbuart_request_port(struct uart_port *port)
  262. {
  263. struct platform_device *pdev = to_platform_device(port->dev);
  264. int size =
  265. resource_size(platform_get_resource(pdev, IORESOURCE_MEM, 0));
  266. if (!request_mem_region(port->mapbase, size, "timb-uart"))
  267. return -EBUSY;
  268. if (port->flags & UPF_IOREMAP) {
  269. port->membase = ioremap(port->mapbase, size);
  270. if (port->membase == NULL) {
  271. release_mem_region(port->mapbase, size);
  272. return -ENOMEM;
  273. }
  274. }
  275. return 0;
  276. }
  277. static irqreturn_t timbuart_handleinterrupt(int irq, void *devid)
  278. {
  279. struct timbuart_port *uart = (struct timbuart_port *)devid;
  280. if (ioread8(uart->port.membase + TIMBUART_IPR)) {
  281. uart->last_ier = ioread32(uart->port.membase + TIMBUART_IER);
  282. /* disable interrupts, the tasklet enables them again */
  283. iowrite32(0, uart->port.membase + TIMBUART_IER);
  284. /* fire off bottom half */
  285. tasklet_schedule(&uart->tasklet);
  286. return IRQ_HANDLED;
  287. } else
  288. return IRQ_NONE;
  289. }
  290. /*
  291. * Configure/autoconfigure the port.
  292. */
  293. static void timbuart_config_port(struct uart_port *port, int flags)
  294. {
  295. if (flags & UART_CONFIG_TYPE) {
  296. port->type = PORT_TIMBUART;
  297. timbuart_request_port(port);
  298. }
  299. }
  300. static int timbuart_verify_port(struct uart_port *port,
  301. struct serial_struct *ser)
  302. {
  303. /* we don't want the core code to modify any port params */
  304. return -EINVAL;
  305. }
  306. static const struct uart_ops timbuart_ops = {
  307. .tx_empty = timbuart_tx_empty,
  308. .set_mctrl = timbuart_set_mctrl,
  309. .get_mctrl = timbuart_get_mctrl,
  310. .stop_tx = timbuart_stop_tx,
  311. .start_tx = timbuart_start_tx,
  312. .flush_buffer = timbuart_flush_buffer,
  313. .stop_rx = timbuart_stop_rx,
  314. .break_ctl = timbuart_break_ctl,
  315. .startup = timbuart_startup,
  316. .shutdown = timbuart_shutdown,
  317. .set_termios = timbuart_set_termios,
  318. .type = timbuart_type,
  319. .release_port = timbuart_release_port,
  320. .request_port = timbuart_request_port,
  321. .config_port = timbuart_config_port,
  322. .verify_port = timbuart_verify_port
  323. };
  324. static struct uart_driver timbuart_driver = {
  325. .owner = THIS_MODULE,
  326. .driver_name = "timberdale_uart",
  327. .dev_name = "ttyTU",
  328. .major = TIMBUART_MAJOR,
  329. .minor = TIMBUART_MINOR,
  330. .nr = 1
  331. };
  332. static int timbuart_probe(struct platform_device *dev)
  333. {
  334. int err, irq;
  335. struct timbuart_port *uart;
  336. struct resource *iomem;
  337. dev_dbg(&dev->dev, "%s\n", __func__);
  338. uart = kzalloc(sizeof(*uart), GFP_KERNEL);
  339. if (!uart) {
  340. err = -EINVAL;
  341. goto err_mem;
  342. }
  343. uart->usedma = 0;
  344. uart->port.uartclk = 3250000 * 16;
  345. uart->port.fifosize = TIMBUART_FIFO_SIZE;
  346. uart->port.regshift = 2;
  347. uart->port.iotype = UPIO_MEM;
  348. uart->port.ops = &timbuart_ops;
  349. uart->port.irq = 0;
  350. uart->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
  351. uart->port.line = 0;
  352. uart->port.dev = &dev->dev;
  353. iomem = platform_get_resource(dev, IORESOURCE_MEM, 0);
  354. if (!iomem) {
  355. err = -ENOMEM;
  356. goto err_register;
  357. }
  358. uart->port.mapbase = iomem->start;
  359. uart->port.membase = NULL;
  360. irq = platform_get_irq(dev, 0);
  361. if (irq < 0) {
  362. err = -EINVAL;
  363. goto err_register;
  364. }
  365. uart->port.irq = irq;
  366. tasklet_init(&uart->tasklet, timbuart_tasklet, (unsigned long)uart);
  367. err = uart_register_driver(&timbuart_driver);
  368. if (err)
  369. goto err_register;
  370. err = uart_add_one_port(&timbuart_driver, &uart->port);
  371. if (err)
  372. goto err_add_port;
  373. platform_set_drvdata(dev, uart);
  374. return 0;
  375. err_add_port:
  376. uart_unregister_driver(&timbuart_driver);
  377. err_register:
  378. kfree(uart);
  379. err_mem:
  380. printk(KERN_ERR "timberdale: Failed to register Timberdale UART: %d\n",
  381. err);
  382. return err;
  383. }
  384. static int timbuart_remove(struct platform_device *dev)
  385. {
  386. struct timbuart_port *uart = platform_get_drvdata(dev);
  387. tasklet_kill(&uart->tasklet);
  388. uart_remove_one_port(&timbuart_driver, &uart->port);
  389. uart_unregister_driver(&timbuart_driver);
  390. kfree(uart);
  391. return 0;
  392. }
  393. static struct platform_driver timbuart_platform_driver = {
  394. .driver = {
  395. .name = "timb-uart",
  396. },
  397. .probe = timbuart_probe,
  398. .remove = timbuart_remove,
  399. };
  400. module_platform_driver(timbuart_platform_driver);
  401. MODULE_DESCRIPTION("Timberdale UART driver");
  402. MODULE_LICENSE("GPL v2");
  403. MODULE_ALIAS("platform:timb-uart");