sprd_serial.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2012-2015 Spreadtrum Communications Inc.
  4. */
  5. #if defined(CONFIG_SERIAL_SPRD_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  6. #define SUPPORT_SYSRQ
  7. #endif
  8. #include <linux/clk.h>
  9. #include <linux/console.h>
  10. #include <linux/delay.h>
  11. #include <linux/dmaengine.h>
  12. #include <linux/dma-mapping.h>
  13. #include <linux/dma/sprd-dma.h>
  14. #include <linux/io.h>
  15. #include <linux/ioport.h>
  16. #include <linux/kernel.h>
  17. #include <linux/module.h>
  18. #include <linux/of.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/serial_core.h>
  21. #include <linux/serial.h>
  22. #include <linux/slab.h>
  23. #include <linux/tty.h>
  24. #include <linux/tty_flip.h>
  25. /* device name */
  26. #define UART_NR_MAX 8
  27. #define SPRD_TTY_NAME "ttyS"
  28. #define SPRD_FIFO_SIZE 128
  29. #define SPRD_DEF_RATE 26000000
  30. #define SPRD_BAUD_IO_LIMIT 3000000
  31. #define SPRD_TIMEOUT 256000
  32. /* the offset of serial registers and BITs for them */
  33. /* data registers */
  34. #define SPRD_TXD 0x0000
  35. #define SPRD_RXD 0x0004
  36. /* line status register and its BITs */
  37. #define SPRD_LSR 0x0008
  38. #define SPRD_LSR_OE BIT(4)
  39. #define SPRD_LSR_FE BIT(3)
  40. #define SPRD_LSR_PE BIT(2)
  41. #define SPRD_LSR_BI BIT(7)
  42. #define SPRD_LSR_TX_OVER BIT(15)
  43. /* data number in TX and RX fifo */
  44. #define SPRD_STS1 0x000C
  45. #define SPRD_RX_FIFO_CNT_MASK GENMASK(7, 0)
  46. #define SPRD_TX_FIFO_CNT_MASK GENMASK(15, 8)
  47. /* interrupt enable register and its BITs */
  48. #define SPRD_IEN 0x0010
  49. #define SPRD_IEN_RX_FULL BIT(0)
  50. #define SPRD_IEN_TX_EMPTY BIT(1)
  51. #define SPRD_IEN_BREAK_DETECT BIT(7)
  52. #define SPRD_IEN_TIMEOUT BIT(13)
  53. /* interrupt clear register */
  54. #define SPRD_ICLR 0x0014
  55. #define SPRD_ICLR_TIMEOUT BIT(13)
  56. /* line control register */
  57. #define SPRD_LCR 0x0018
  58. #define SPRD_LCR_STOP_1BIT 0x10
  59. #define SPRD_LCR_STOP_2BIT 0x30
  60. #define SPRD_LCR_DATA_LEN (BIT(2) | BIT(3))
  61. #define SPRD_LCR_DATA_LEN5 0x0
  62. #define SPRD_LCR_DATA_LEN6 0x4
  63. #define SPRD_LCR_DATA_LEN7 0x8
  64. #define SPRD_LCR_DATA_LEN8 0xc
  65. #define SPRD_LCR_PARITY (BIT(0) | BIT(1))
  66. #define SPRD_LCR_PARITY_EN 0x2
  67. #define SPRD_LCR_EVEN_PAR 0x0
  68. #define SPRD_LCR_ODD_PAR 0x1
  69. /* control register 1 */
  70. #define SPRD_CTL1 0x001C
  71. #define SPRD_DMA_EN BIT(15)
  72. #define SPRD_LOOPBACK_EN BIT(14)
  73. #define RX_HW_FLOW_CTL_THLD BIT(6)
  74. #define RX_HW_FLOW_CTL_EN BIT(7)
  75. #define TX_HW_FLOW_CTL_EN BIT(8)
  76. #define RX_TOUT_THLD_DEF 0x3E00
  77. #define RX_HFC_THLD_DEF 0x40
  78. /* fifo threshold register */
  79. #define SPRD_CTL2 0x0020
  80. #define THLD_TX_EMPTY 0x40
  81. #define THLD_TX_EMPTY_SHIFT 8
  82. #define THLD_RX_FULL 0x40
  83. #define THLD_RX_FULL_MASK GENMASK(6, 0)
  84. /* config baud rate register */
  85. #define SPRD_CLKD0 0x0024
  86. #define SPRD_CLKD0_MASK GENMASK(15, 0)
  87. #define SPRD_CLKD1 0x0028
  88. #define SPRD_CLKD1_MASK GENMASK(20, 16)
  89. #define SPRD_CLKD1_SHIFT 16
  90. /* interrupt mask status register */
  91. #define SPRD_IMSR 0x002C
  92. #define SPRD_IMSR_RX_FIFO_FULL BIT(0)
  93. #define SPRD_IMSR_TX_FIFO_EMPTY BIT(1)
  94. #define SPRD_IMSR_BREAK_DETECT BIT(7)
  95. #define SPRD_IMSR_TIMEOUT BIT(13)
  96. #define SPRD_DEFAULT_SOURCE_CLK 26000000
  97. #define SPRD_RX_DMA_STEP 1
  98. #define SPRD_RX_FIFO_FULL 1
  99. #define SPRD_TX_FIFO_FULL 0x20
  100. #define SPRD_UART_RX_SIZE (UART_XMIT_SIZE / 4)
  101. struct sprd_uart_dma {
  102. struct dma_chan *chn;
  103. unsigned char *virt;
  104. dma_addr_t phys_addr;
  105. dma_cookie_t cookie;
  106. u32 trans_len;
  107. bool enable;
  108. };
  109. struct sprd_uart_port {
  110. struct uart_port port;
  111. char name[16];
  112. struct clk *clk;
  113. struct sprd_uart_dma tx_dma;
  114. struct sprd_uart_dma rx_dma;
  115. dma_addr_t pos;
  116. unsigned char *rx_buf_tail;
  117. };
  118. static struct sprd_uart_port *sprd_port[UART_NR_MAX];
  119. static int sprd_ports_num;
  120. static int sprd_start_dma_rx(struct uart_port *port);
  121. static int sprd_tx_dma_config(struct uart_port *port);
  122. static inline unsigned int serial_in(struct uart_port *port,
  123. unsigned int offset)
  124. {
  125. return readl_relaxed(port->membase + offset);
  126. }
  127. static inline void serial_out(struct uart_port *port, unsigned int offset,
  128. int value)
  129. {
  130. writel_relaxed(value, port->membase + offset);
  131. }
  132. static unsigned int sprd_tx_empty(struct uart_port *port)
  133. {
  134. if (serial_in(port, SPRD_STS1) & SPRD_TX_FIFO_CNT_MASK)
  135. return 0;
  136. else
  137. return TIOCSER_TEMT;
  138. }
  139. static unsigned int sprd_get_mctrl(struct uart_port *port)
  140. {
  141. return TIOCM_DSR | TIOCM_CTS;
  142. }
  143. static void sprd_set_mctrl(struct uart_port *port, unsigned int mctrl)
  144. {
  145. u32 val = serial_in(port, SPRD_CTL1);
  146. if (mctrl & TIOCM_LOOP)
  147. val |= SPRD_LOOPBACK_EN;
  148. else
  149. val &= ~SPRD_LOOPBACK_EN;
  150. serial_out(port, SPRD_CTL1, val);
  151. }
  152. static void sprd_stop_rx(struct uart_port *port)
  153. {
  154. struct sprd_uart_port *sp =
  155. container_of(port, struct sprd_uart_port, port);
  156. unsigned int ien, iclr;
  157. if (sp->rx_dma.enable)
  158. dmaengine_terminate_all(sp->rx_dma.chn);
  159. iclr = serial_in(port, SPRD_ICLR);
  160. ien = serial_in(port, SPRD_IEN);
  161. ien &= ~(SPRD_IEN_RX_FULL | SPRD_IEN_BREAK_DETECT);
  162. iclr |= SPRD_IEN_RX_FULL | SPRD_IEN_BREAK_DETECT;
  163. serial_out(port, SPRD_IEN, ien);
  164. serial_out(port, SPRD_ICLR, iclr);
  165. }
  166. static void sprd_uart_dma_enable(struct uart_port *port, bool enable)
  167. {
  168. u32 val = serial_in(port, SPRD_CTL1);
  169. if (enable)
  170. val |= SPRD_DMA_EN;
  171. else
  172. val &= ~SPRD_DMA_EN;
  173. serial_out(port, SPRD_CTL1, val);
  174. }
  175. static void sprd_stop_tx_dma(struct uart_port *port)
  176. {
  177. struct sprd_uart_port *sp =
  178. container_of(port, struct sprd_uart_port, port);
  179. struct circ_buf *xmit = &port->state->xmit;
  180. struct dma_tx_state state;
  181. u32 trans_len;
  182. dmaengine_pause(sp->tx_dma.chn);
  183. dmaengine_tx_status(sp->tx_dma.chn, sp->tx_dma.cookie, &state);
  184. if (state.residue) {
  185. trans_len = state.residue - sp->tx_dma.phys_addr;
  186. xmit->tail = (xmit->tail + trans_len) & (UART_XMIT_SIZE - 1);
  187. port->icount.tx += trans_len;
  188. dma_unmap_single(port->dev, sp->tx_dma.phys_addr,
  189. sp->tx_dma.trans_len, DMA_TO_DEVICE);
  190. }
  191. dmaengine_terminate_all(sp->tx_dma.chn);
  192. sp->tx_dma.trans_len = 0;
  193. }
  194. static int sprd_tx_buf_remap(struct uart_port *port)
  195. {
  196. struct sprd_uart_port *sp =
  197. container_of(port, struct sprd_uart_port, port);
  198. struct circ_buf *xmit = &port->state->xmit;
  199. sp->tx_dma.trans_len =
  200. CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
  201. sp->tx_dma.phys_addr = dma_map_single(port->dev,
  202. (void *)&(xmit->buf[xmit->tail]),
  203. sp->tx_dma.trans_len,
  204. DMA_TO_DEVICE);
  205. return dma_mapping_error(port->dev, sp->tx_dma.phys_addr);
  206. }
  207. static void sprd_complete_tx_dma(void *data)
  208. {
  209. struct uart_port *port = (struct uart_port *)data;
  210. struct sprd_uart_port *sp =
  211. container_of(port, struct sprd_uart_port, port);
  212. struct circ_buf *xmit = &port->state->xmit;
  213. unsigned long flags;
  214. spin_lock_irqsave(&port->lock, flags);
  215. dma_unmap_single(port->dev, sp->tx_dma.phys_addr,
  216. sp->tx_dma.trans_len, DMA_TO_DEVICE);
  217. xmit->tail = (xmit->tail + sp->tx_dma.trans_len) & (UART_XMIT_SIZE - 1);
  218. port->icount.tx += sp->tx_dma.trans_len;
  219. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  220. uart_write_wakeup(port);
  221. if (uart_circ_empty(xmit) || sprd_tx_buf_remap(port) ||
  222. sprd_tx_dma_config(port))
  223. sp->tx_dma.trans_len = 0;
  224. spin_unlock_irqrestore(&port->lock, flags);
  225. }
  226. static int sprd_uart_dma_submit(struct uart_port *port,
  227. struct sprd_uart_dma *ud, u32 trans_len,
  228. enum dma_transfer_direction direction,
  229. dma_async_tx_callback callback)
  230. {
  231. struct dma_async_tx_descriptor *dma_des;
  232. unsigned long flags;
  233. flags = SPRD_DMA_FLAGS(SPRD_DMA_CHN_MODE_NONE,
  234. SPRD_DMA_NO_TRG,
  235. SPRD_DMA_FRAG_REQ,
  236. SPRD_DMA_TRANS_INT);
  237. dma_des = dmaengine_prep_slave_single(ud->chn, ud->phys_addr, trans_len,
  238. direction, flags);
  239. if (!dma_des)
  240. return -ENODEV;
  241. dma_des->callback = callback;
  242. dma_des->callback_param = port;
  243. ud->cookie = dmaengine_submit(dma_des);
  244. if (dma_submit_error(ud->cookie))
  245. return dma_submit_error(ud->cookie);
  246. dma_async_issue_pending(ud->chn);
  247. return 0;
  248. }
  249. static int sprd_tx_dma_config(struct uart_port *port)
  250. {
  251. struct sprd_uart_port *sp =
  252. container_of(port, struct sprd_uart_port, port);
  253. u32 burst = sp->tx_dma.trans_len > SPRD_TX_FIFO_FULL ?
  254. SPRD_TX_FIFO_FULL : sp->tx_dma.trans_len;
  255. int ret;
  256. struct dma_slave_config cfg = {
  257. .dst_addr = port->mapbase + SPRD_TXD,
  258. .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
  259. .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
  260. .src_maxburst = burst,
  261. };
  262. ret = dmaengine_slave_config(sp->tx_dma.chn, &cfg);
  263. if (ret < 0)
  264. return ret;
  265. return sprd_uart_dma_submit(port, &sp->tx_dma, sp->tx_dma.trans_len,
  266. DMA_MEM_TO_DEV, sprd_complete_tx_dma);
  267. }
  268. static void sprd_start_tx_dma(struct uart_port *port)
  269. {
  270. struct sprd_uart_port *sp =
  271. container_of(port, struct sprd_uart_port, port);
  272. struct circ_buf *xmit = &port->state->xmit;
  273. if (port->x_char) {
  274. serial_out(port, SPRD_TXD, port->x_char);
  275. port->icount.tx++;
  276. port->x_char = 0;
  277. return;
  278. }
  279. if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
  280. sprd_stop_tx_dma(port);
  281. return;
  282. }
  283. if (sp->tx_dma.trans_len)
  284. return;
  285. if (sprd_tx_buf_remap(port) || sprd_tx_dma_config(port))
  286. sp->tx_dma.trans_len = 0;
  287. }
  288. static void sprd_rx_full_thld(struct uart_port *port, u32 thld)
  289. {
  290. u32 val = serial_in(port, SPRD_CTL2);
  291. val &= ~THLD_RX_FULL_MASK;
  292. val |= thld & THLD_RX_FULL_MASK;
  293. serial_out(port, SPRD_CTL2, val);
  294. }
  295. static int sprd_rx_alloc_buf(struct sprd_uart_port *sp)
  296. {
  297. sp->rx_dma.virt = dma_alloc_coherent(sp->port.dev, SPRD_UART_RX_SIZE,
  298. &sp->rx_dma.phys_addr, GFP_KERNEL);
  299. if (!sp->rx_dma.virt)
  300. return -ENOMEM;
  301. return 0;
  302. }
  303. static void sprd_rx_free_buf(struct sprd_uart_port *sp)
  304. {
  305. if (sp->rx_dma.virt)
  306. dma_free_coherent(sp->port.dev, SPRD_UART_RX_SIZE,
  307. sp->rx_dma.virt, sp->rx_dma.phys_addr);
  308. }
  309. static int sprd_rx_dma_config(struct uart_port *port, u32 burst)
  310. {
  311. struct sprd_uart_port *sp =
  312. container_of(port, struct sprd_uart_port, port);
  313. struct dma_slave_config cfg = {
  314. .src_addr = port->mapbase + SPRD_RXD,
  315. .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
  316. .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
  317. .src_maxburst = burst,
  318. };
  319. return dmaengine_slave_config(sp->rx_dma.chn, &cfg);
  320. }
  321. static void sprd_uart_dma_rx(struct uart_port *port)
  322. {
  323. struct sprd_uart_port *sp =
  324. container_of(port, struct sprd_uart_port, port);
  325. struct tty_port *tty = &port->state->port;
  326. port->icount.rx += sp->rx_dma.trans_len;
  327. tty_insert_flip_string(tty, sp->rx_buf_tail, sp->rx_dma.trans_len);
  328. tty_flip_buffer_push(tty);
  329. }
  330. static void sprd_uart_dma_irq(struct uart_port *port)
  331. {
  332. struct sprd_uart_port *sp =
  333. container_of(port, struct sprd_uart_port, port);
  334. struct dma_tx_state state;
  335. enum dma_status status;
  336. status = dmaengine_tx_status(sp->rx_dma.chn,
  337. sp->rx_dma.cookie, &state);
  338. if (status == DMA_ERROR)
  339. sprd_stop_rx(port);
  340. if (!state.residue && sp->pos == sp->rx_dma.phys_addr)
  341. return;
  342. if (!state.residue) {
  343. sp->rx_dma.trans_len = SPRD_UART_RX_SIZE +
  344. sp->rx_dma.phys_addr - sp->pos;
  345. sp->pos = sp->rx_dma.phys_addr;
  346. } else {
  347. sp->rx_dma.trans_len = state.residue - sp->pos;
  348. sp->pos = state.residue;
  349. }
  350. sprd_uart_dma_rx(port);
  351. sp->rx_buf_tail += sp->rx_dma.trans_len;
  352. }
  353. static void sprd_complete_rx_dma(void *data)
  354. {
  355. struct uart_port *port = (struct uart_port *)data;
  356. struct sprd_uart_port *sp =
  357. container_of(port, struct sprd_uart_port, port);
  358. struct dma_tx_state state;
  359. enum dma_status status;
  360. unsigned long flags;
  361. spin_lock_irqsave(&port->lock, flags);
  362. status = dmaengine_tx_status(sp->rx_dma.chn,
  363. sp->rx_dma.cookie, &state);
  364. if (status != DMA_COMPLETE) {
  365. sprd_stop_rx(port);
  366. spin_unlock_irqrestore(&port->lock, flags);
  367. return;
  368. }
  369. if (sp->pos != sp->rx_dma.phys_addr) {
  370. sp->rx_dma.trans_len = SPRD_UART_RX_SIZE +
  371. sp->rx_dma.phys_addr - sp->pos;
  372. sprd_uart_dma_rx(port);
  373. sp->rx_buf_tail += sp->rx_dma.trans_len;
  374. }
  375. if (sprd_start_dma_rx(port))
  376. sprd_stop_rx(port);
  377. spin_unlock_irqrestore(&port->lock, flags);
  378. }
  379. static int sprd_start_dma_rx(struct uart_port *port)
  380. {
  381. struct sprd_uart_port *sp =
  382. container_of(port, struct sprd_uart_port, port);
  383. int ret;
  384. if (!sp->rx_dma.enable)
  385. return 0;
  386. sp->pos = sp->rx_dma.phys_addr;
  387. sp->rx_buf_tail = sp->rx_dma.virt;
  388. sprd_rx_full_thld(port, SPRD_RX_FIFO_FULL);
  389. ret = sprd_rx_dma_config(port, SPRD_RX_DMA_STEP);
  390. if (ret)
  391. return ret;
  392. return sprd_uart_dma_submit(port, &sp->rx_dma, SPRD_UART_RX_SIZE,
  393. DMA_DEV_TO_MEM, sprd_complete_rx_dma);
  394. }
  395. static void sprd_release_dma(struct uart_port *port)
  396. {
  397. struct sprd_uart_port *sp =
  398. container_of(port, struct sprd_uart_port, port);
  399. sprd_uart_dma_enable(port, false);
  400. if (sp->rx_dma.enable)
  401. dma_release_channel(sp->rx_dma.chn);
  402. if (sp->tx_dma.enable)
  403. dma_release_channel(sp->tx_dma.chn);
  404. sp->tx_dma.enable = false;
  405. sp->rx_dma.enable = false;
  406. }
  407. static void sprd_request_dma(struct uart_port *port)
  408. {
  409. struct sprd_uart_port *sp =
  410. container_of(port, struct sprd_uart_port, port);
  411. sp->tx_dma.enable = true;
  412. sp->rx_dma.enable = true;
  413. sp->tx_dma.chn = dma_request_chan(port->dev, "tx");
  414. if (IS_ERR(sp->tx_dma.chn)) {
  415. dev_err(port->dev, "request TX DMA channel failed, ret = %ld\n",
  416. PTR_ERR(sp->tx_dma.chn));
  417. sp->tx_dma.enable = false;
  418. }
  419. sp->rx_dma.chn = dma_request_chan(port->dev, "rx");
  420. if (IS_ERR(sp->rx_dma.chn)) {
  421. dev_err(port->dev, "request RX DMA channel failed, ret = %ld\n",
  422. PTR_ERR(sp->rx_dma.chn));
  423. sp->rx_dma.enable = false;
  424. }
  425. }
  426. static void sprd_stop_tx(struct uart_port *port)
  427. {
  428. struct sprd_uart_port *sp = container_of(port, struct sprd_uart_port,
  429. port);
  430. unsigned int ien, iclr;
  431. if (sp->tx_dma.enable) {
  432. sprd_stop_tx_dma(port);
  433. return;
  434. }
  435. iclr = serial_in(port, SPRD_ICLR);
  436. ien = serial_in(port, SPRD_IEN);
  437. iclr |= SPRD_IEN_TX_EMPTY;
  438. ien &= ~SPRD_IEN_TX_EMPTY;
  439. serial_out(port, SPRD_IEN, ien);
  440. serial_out(port, SPRD_ICLR, iclr);
  441. }
  442. static void sprd_start_tx(struct uart_port *port)
  443. {
  444. struct sprd_uart_port *sp = container_of(port, struct sprd_uart_port,
  445. port);
  446. unsigned int ien;
  447. if (sp->tx_dma.enable) {
  448. sprd_start_tx_dma(port);
  449. return;
  450. }
  451. ien = serial_in(port, SPRD_IEN);
  452. if (!(ien & SPRD_IEN_TX_EMPTY)) {
  453. ien |= SPRD_IEN_TX_EMPTY;
  454. serial_out(port, SPRD_IEN, ien);
  455. }
  456. }
  457. /* The Sprd serial does not support this function. */
  458. static void sprd_break_ctl(struct uart_port *port, int break_state)
  459. {
  460. /* nothing to do */
  461. }
  462. static int handle_lsr_errors(struct uart_port *port,
  463. unsigned int *flag,
  464. unsigned int *lsr)
  465. {
  466. int ret = 0;
  467. /* statistics */
  468. if (*lsr & SPRD_LSR_BI) {
  469. *lsr &= ~(SPRD_LSR_FE | SPRD_LSR_PE);
  470. port->icount.brk++;
  471. ret = uart_handle_break(port);
  472. if (ret)
  473. return ret;
  474. } else if (*lsr & SPRD_LSR_PE)
  475. port->icount.parity++;
  476. else if (*lsr & SPRD_LSR_FE)
  477. port->icount.frame++;
  478. if (*lsr & SPRD_LSR_OE)
  479. port->icount.overrun++;
  480. /* mask off conditions which should be ignored */
  481. *lsr &= port->read_status_mask;
  482. if (*lsr & SPRD_LSR_BI)
  483. *flag = TTY_BREAK;
  484. else if (*lsr & SPRD_LSR_PE)
  485. *flag = TTY_PARITY;
  486. else if (*lsr & SPRD_LSR_FE)
  487. *flag = TTY_FRAME;
  488. return ret;
  489. }
  490. static inline void sprd_rx(struct uart_port *port)
  491. {
  492. struct sprd_uart_port *sp = container_of(port, struct sprd_uart_port,
  493. port);
  494. struct tty_port *tty = &port->state->port;
  495. unsigned int ch, flag, lsr, max_count = SPRD_TIMEOUT;
  496. if (sp->rx_dma.enable) {
  497. sprd_uart_dma_irq(port);
  498. return;
  499. }
  500. while ((serial_in(port, SPRD_STS1) & SPRD_RX_FIFO_CNT_MASK) &&
  501. max_count--) {
  502. lsr = serial_in(port, SPRD_LSR);
  503. ch = serial_in(port, SPRD_RXD);
  504. flag = TTY_NORMAL;
  505. port->icount.rx++;
  506. if (lsr & (SPRD_LSR_BI | SPRD_LSR_PE |
  507. SPRD_LSR_FE | SPRD_LSR_OE))
  508. if (handle_lsr_errors(port, &flag, &lsr))
  509. continue;
  510. if (uart_handle_sysrq_char(port, ch))
  511. continue;
  512. uart_insert_char(port, lsr, SPRD_LSR_OE, ch, flag);
  513. }
  514. tty_flip_buffer_push(tty);
  515. }
  516. static inline void sprd_tx(struct uart_port *port)
  517. {
  518. struct circ_buf *xmit = &port->state->xmit;
  519. int count;
  520. if (port->x_char) {
  521. serial_out(port, SPRD_TXD, port->x_char);
  522. port->icount.tx++;
  523. port->x_char = 0;
  524. return;
  525. }
  526. if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
  527. sprd_stop_tx(port);
  528. return;
  529. }
  530. count = THLD_TX_EMPTY;
  531. do {
  532. serial_out(port, SPRD_TXD, xmit->buf[xmit->tail]);
  533. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  534. port->icount.tx++;
  535. if (uart_circ_empty(xmit))
  536. break;
  537. } while (--count > 0);
  538. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  539. uart_write_wakeup(port);
  540. if (uart_circ_empty(xmit))
  541. sprd_stop_tx(port);
  542. }
  543. /* this handles the interrupt from one port */
  544. static irqreturn_t sprd_handle_irq(int irq, void *dev_id)
  545. {
  546. struct uart_port *port = dev_id;
  547. unsigned int ims;
  548. spin_lock(&port->lock);
  549. ims = serial_in(port, SPRD_IMSR);
  550. if (!ims) {
  551. spin_unlock(&port->lock);
  552. return IRQ_NONE;
  553. }
  554. if (ims & SPRD_IMSR_TIMEOUT)
  555. serial_out(port, SPRD_ICLR, SPRD_ICLR_TIMEOUT);
  556. if (ims & SPRD_IMSR_BREAK_DETECT)
  557. serial_out(port, SPRD_ICLR, SPRD_IMSR_BREAK_DETECT);
  558. if (ims & (SPRD_IMSR_RX_FIFO_FULL | SPRD_IMSR_BREAK_DETECT |
  559. SPRD_IMSR_TIMEOUT))
  560. sprd_rx(port);
  561. if (ims & SPRD_IMSR_TX_FIFO_EMPTY)
  562. sprd_tx(port);
  563. spin_unlock(&port->lock);
  564. return IRQ_HANDLED;
  565. }
  566. static void sprd_uart_dma_startup(struct uart_port *port,
  567. struct sprd_uart_port *sp)
  568. {
  569. int ret;
  570. sprd_request_dma(port);
  571. if (!(sp->rx_dma.enable || sp->tx_dma.enable))
  572. return;
  573. ret = sprd_start_dma_rx(port);
  574. if (ret) {
  575. sp->rx_dma.enable = false;
  576. dma_release_channel(sp->rx_dma.chn);
  577. dev_warn(port->dev, "fail to start RX dma mode\n");
  578. }
  579. sprd_uart_dma_enable(port, true);
  580. }
  581. static int sprd_startup(struct uart_port *port)
  582. {
  583. int ret = 0;
  584. unsigned int ien, fc;
  585. unsigned int timeout;
  586. struct sprd_uart_port *sp;
  587. unsigned long flags;
  588. serial_out(port, SPRD_CTL2,
  589. THLD_TX_EMPTY << THLD_TX_EMPTY_SHIFT | THLD_RX_FULL);
  590. /* clear rx fifo */
  591. timeout = SPRD_TIMEOUT;
  592. while (timeout-- && serial_in(port, SPRD_STS1) & SPRD_RX_FIFO_CNT_MASK)
  593. serial_in(port, SPRD_RXD);
  594. /* clear tx fifo */
  595. timeout = SPRD_TIMEOUT;
  596. while (timeout-- && serial_in(port, SPRD_STS1) & SPRD_TX_FIFO_CNT_MASK)
  597. cpu_relax();
  598. /* clear interrupt */
  599. serial_out(port, SPRD_IEN, 0);
  600. serial_out(port, SPRD_ICLR, ~0);
  601. /* allocate irq */
  602. sp = container_of(port, struct sprd_uart_port, port);
  603. snprintf(sp->name, sizeof(sp->name), "sprd_serial%d", port->line);
  604. sprd_uart_dma_startup(port, sp);
  605. ret = devm_request_irq(port->dev, port->irq, sprd_handle_irq,
  606. IRQF_SHARED, sp->name, port);
  607. if (ret) {
  608. dev_err(port->dev, "fail to request serial irq %d, ret=%d\n",
  609. port->irq, ret);
  610. return ret;
  611. }
  612. fc = serial_in(port, SPRD_CTL1);
  613. fc |= RX_TOUT_THLD_DEF | RX_HFC_THLD_DEF;
  614. serial_out(port, SPRD_CTL1, fc);
  615. /* enable interrupt */
  616. spin_lock_irqsave(&port->lock, flags);
  617. ien = serial_in(port, SPRD_IEN);
  618. ien |= SPRD_IEN_BREAK_DETECT | SPRD_IEN_TIMEOUT;
  619. if (!sp->rx_dma.enable)
  620. ien |= SPRD_IEN_RX_FULL;
  621. serial_out(port, SPRD_IEN, ien);
  622. spin_unlock_irqrestore(&port->lock, flags);
  623. return 0;
  624. }
  625. static void sprd_shutdown(struct uart_port *port)
  626. {
  627. sprd_release_dma(port);
  628. serial_out(port, SPRD_IEN, 0);
  629. serial_out(port, SPRD_ICLR, ~0);
  630. devm_free_irq(port->dev, port->irq, port);
  631. }
  632. static void sprd_set_termios(struct uart_port *port,
  633. struct ktermios *termios,
  634. struct ktermios *old)
  635. {
  636. unsigned int baud, quot;
  637. unsigned int lcr = 0, fc;
  638. unsigned long flags;
  639. /* ask the core to calculate the divisor for us */
  640. baud = uart_get_baud_rate(port, termios, old, 0, SPRD_BAUD_IO_LIMIT);
  641. quot = port->uartclk / baud;
  642. /* set data length */
  643. switch (termios->c_cflag & CSIZE) {
  644. case CS5:
  645. lcr |= SPRD_LCR_DATA_LEN5;
  646. break;
  647. case CS6:
  648. lcr |= SPRD_LCR_DATA_LEN6;
  649. break;
  650. case CS7:
  651. lcr |= SPRD_LCR_DATA_LEN7;
  652. break;
  653. case CS8:
  654. default:
  655. lcr |= SPRD_LCR_DATA_LEN8;
  656. break;
  657. }
  658. /* calculate stop bits */
  659. lcr &= ~(SPRD_LCR_STOP_1BIT | SPRD_LCR_STOP_2BIT);
  660. if (termios->c_cflag & CSTOPB)
  661. lcr |= SPRD_LCR_STOP_2BIT;
  662. else
  663. lcr |= SPRD_LCR_STOP_1BIT;
  664. /* calculate parity */
  665. lcr &= ~SPRD_LCR_PARITY;
  666. termios->c_cflag &= ~CMSPAR; /* no support mark/space */
  667. if (termios->c_cflag & PARENB) {
  668. lcr |= SPRD_LCR_PARITY_EN;
  669. if (termios->c_cflag & PARODD)
  670. lcr |= SPRD_LCR_ODD_PAR;
  671. else
  672. lcr |= SPRD_LCR_EVEN_PAR;
  673. }
  674. spin_lock_irqsave(&port->lock, flags);
  675. /* update the per-port timeout */
  676. uart_update_timeout(port, termios->c_cflag, baud);
  677. port->read_status_mask = SPRD_LSR_OE;
  678. if (termios->c_iflag & INPCK)
  679. port->read_status_mask |= SPRD_LSR_FE | SPRD_LSR_PE;
  680. if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
  681. port->read_status_mask |= SPRD_LSR_BI;
  682. /* characters to ignore */
  683. port->ignore_status_mask = 0;
  684. if (termios->c_iflag & IGNPAR)
  685. port->ignore_status_mask |= SPRD_LSR_PE | SPRD_LSR_FE;
  686. if (termios->c_iflag & IGNBRK) {
  687. port->ignore_status_mask |= SPRD_LSR_BI;
  688. /*
  689. * If we're ignoring parity and break indicators,
  690. * ignore overruns too (for real raw support).
  691. */
  692. if (termios->c_iflag & IGNPAR)
  693. port->ignore_status_mask |= SPRD_LSR_OE;
  694. }
  695. /* flow control */
  696. fc = serial_in(port, SPRD_CTL1);
  697. fc &= ~(RX_HW_FLOW_CTL_THLD | RX_HW_FLOW_CTL_EN | TX_HW_FLOW_CTL_EN);
  698. if (termios->c_cflag & CRTSCTS) {
  699. fc |= RX_HW_FLOW_CTL_THLD;
  700. fc |= RX_HW_FLOW_CTL_EN;
  701. fc |= TX_HW_FLOW_CTL_EN;
  702. }
  703. /* clock divider bit0~bit15 */
  704. serial_out(port, SPRD_CLKD0, quot & SPRD_CLKD0_MASK);
  705. /* clock divider bit16~bit20 */
  706. serial_out(port, SPRD_CLKD1,
  707. (quot & SPRD_CLKD1_MASK) >> SPRD_CLKD1_SHIFT);
  708. serial_out(port, SPRD_LCR, lcr);
  709. fc |= RX_TOUT_THLD_DEF | RX_HFC_THLD_DEF;
  710. serial_out(port, SPRD_CTL1, fc);
  711. spin_unlock_irqrestore(&port->lock, flags);
  712. /* Don't rewrite B0 */
  713. if (tty_termios_baud_rate(termios))
  714. tty_termios_encode_baud_rate(termios, baud, baud);
  715. }
  716. static const char *sprd_type(struct uart_port *port)
  717. {
  718. return "SPX";
  719. }
  720. static void sprd_release_port(struct uart_port *port)
  721. {
  722. /* nothing to do */
  723. }
  724. static int sprd_request_port(struct uart_port *port)
  725. {
  726. return 0;
  727. }
  728. static void sprd_config_port(struct uart_port *port, int flags)
  729. {
  730. if (flags & UART_CONFIG_TYPE)
  731. port->type = PORT_SPRD;
  732. }
  733. static int sprd_verify_port(struct uart_port *port, struct serial_struct *ser)
  734. {
  735. if (ser->type != PORT_SPRD)
  736. return -EINVAL;
  737. if (port->irq != ser->irq)
  738. return -EINVAL;
  739. if (port->iotype != ser->io_type)
  740. return -EINVAL;
  741. return 0;
  742. }
  743. static void sprd_pm(struct uart_port *port, unsigned int state,
  744. unsigned int oldstate)
  745. {
  746. struct sprd_uart_port *sup =
  747. container_of(port, struct sprd_uart_port, port);
  748. switch (state) {
  749. case UART_PM_STATE_ON:
  750. clk_prepare_enable(sup->clk);
  751. break;
  752. case UART_PM_STATE_OFF:
  753. clk_disable_unprepare(sup->clk);
  754. break;
  755. }
  756. }
  757. static const struct uart_ops serial_sprd_ops = {
  758. .tx_empty = sprd_tx_empty,
  759. .get_mctrl = sprd_get_mctrl,
  760. .set_mctrl = sprd_set_mctrl,
  761. .stop_tx = sprd_stop_tx,
  762. .start_tx = sprd_start_tx,
  763. .stop_rx = sprd_stop_rx,
  764. .break_ctl = sprd_break_ctl,
  765. .startup = sprd_startup,
  766. .shutdown = sprd_shutdown,
  767. .set_termios = sprd_set_termios,
  768. .type = sprd_type,
  769. .release_port = sprd_release_port,
  770. .request_port = sprd_request_port,
  771. .config_port = sprd_config_port,
  772. .verify_port = sprd_verify_port,
  773. .pm = sprd_pm,
  774. };
  775. #ifdef CONFIG_SERIAL_SPRD_CONSOLE
  776. static void wait_for_xmitr(struct uart_port *port)
  777. {
  778. unsigned int status, tmout = 10000;
  779. /* wait up to 10ms for the character(s) to be sent */
  780. do {
  781. status = serial_in(port, SPRD_STS1);
  782. if (--tmout == 0)
  783. break;
  784. udelay(1);
  785. } while (status & SPRD_TX_FIFO_CNT_MASK);
  786. }
  787. static void sprd_console_putchar(struct uart_port *port, int ch)
  788. {
  789. wait_for_xmitr(port);
  790. serial_out(port, SPRD_TXD, ch);
  791. }
  792. static void sprd_console_write(struct console *co, const char *s,
  793. unsigned int count)
  794. {
  795. struct uart_port *port = &sprd_port[co->index]->port;
  796. int locked = 1;
  797. unsigned long flags;
  798. if (port->sysrq)
  799. locked = 0;
  800. else if (oops_in_progress)
  801. locked = spin_trylock_irqsave(&port->lock, flags);
  802. else
  803. spin_lock_irqsave(&port->lock, flags);
  804. uart_console_write(port, s, count, sprd_console_putchar);
  805. /* wait for transmitter to become empty */
  806. wait_for_xmitr(port);
  807. if (locked)
  808. spin_unlock_irqrestore(&port->lock, flags);
  809. }
  810. static int __init sprd_console_setup(struct console *co, char *options)
  811. {
  812. struct sprd_uart_port *sprd_uart_port;
  813. int baud = 115200;
  814. int bits = 8;
  815. int parity = 'n';
  816. int flow = 'n';
  817. if (co->index >= UART_NR_MAX || co->index < 0)
  818. co->index = 0;
  819. sprd_uart_port = sprd_port[co->index];
  820. if (!sprd_uart_port || !sprd_uart_port->port.membase) {
  821. pr_info("serial port %d not yet initialized\n", co->index);
  822. return -ENODEV;
  823. }
  824. if (options)
  825. uart_parse_options(options, &baud, &parity, &bits, &flow);
  826. return uart_set_options(&sprd_uart_port->port, co, baud,
  827. parity, bits, flow);
  828. }
  829. static struct uart_driver sprd_uart_driver;
  830. static struct console sprd_console = {
  831. .name = SPRD_TTY_NAME,
  832. .write = sprd_console_write,
  833. .device = uart_console_device,
  834. .setup = sprd_console_setup,
  835. .flags = CON_PRINTBUFFER,
  836. .index = -1,
  837. .data = &sprd_uart_driver,
  838. };
  839. static int __init sprd_serial_console_init(void)
  840. {
  841. register_console(&sprd_console);
  842. return 0;
  843. }
  844. console_initcall(sprd_serial_console_init);
  845. #define SPRD_CONSOLE (&sprd_console)
  846. /* Support for earlycon */
  847. static void sprd_putc(struct uart_port *port, int c)
  848. {
  849. unsigned int timeout = SPRD_TIMEOUT;
  850. while (timeout-- &&
  851. !(readl(port->membase + SPRD_LSR) & SPRD_LSR_TX_OVER))
  852. cpu_relax();
  853. writeb(c, port->membase + SPRD_TXD);
  854. }
  855. static void sprd_early_write(struct console *con, const char *s, unsigned int n)
  856. {
  857. struct earlycon_device *dev = con->data;
  858. uart_console_write(&dev->port, s, n, sprd_putc);
  859. }
  860. static int __init sprd_early_console_setup(struct earlycon_device *device,
  861. const char *opt)
  862. {
  863. if (!device->port.membase)
  864. return -ENODEV;
  865. device->con->write = sprd_early_write;
  866. return 0;
  867. }
  868. OF_EARLYCON_DECLARE(sprd_serial, "sprd,sc9836-uart",
  869. sprd_early_console_setup);
  870. #else /* !CONFIG_SERIAL_SPRD_CONSOLE */
  871. #define SPRD_CONSOLE NULL
  872. #endif
  873. static struct uart_driver sprd_uart_driver = {
  874. .owner = THIS_MODULE,
  875. .driver_name = "sprd_serial",
  876. .dev_name = SPRD_TTY_NAME,
  877. .major = 0,
  878. .minor = 0,
  879. .nr = UART_NR_MAX,
  880. .cons = SPRD_CONSOLE,
  881. };
  882. static int sprd_probe_dt_alias(int index, struct device *dev)
  883. {
  884. struct device_node *np;
  885. int ret = index;
  886. if (!IS_ENABLED(CONFIG_OF))
  887. return ret;
  888. np = dev->of_node;
  889. if (!np)
  890. return ret;
  891. ret = of_alias_get_id(np, "serial");
  892. if (ret < 0)
  893. ret = index;
  894. else if (ret >= ARRAY_SIZE(sprd_port) || sprd_port[ret] != NULL) {
  895. dev_warn(dev, "requested serial port %d not available.\n", ret);
  896. ret = index;
  897. }
  898. return ret;
  899. }
  900. static int sprd_remove(struct platform_device *dev)
  901. {
  902. struct sprd_uart_port *sup = platform_get_drvdata(dev);
  903. if (sup) {
  904. uart_remove_one_port(&sprd_uart_driver, &sup->port);
  905. sprd_port[sup->port.line] = NULL;
  906. sprd_rx_free_buf(sup);
  907. sprd_ports_num--;
  908. }
  909. if (!sprd_ports_num)
  910. uart_unregister_driver(&sprd_uart_driver);
  911. return 0;
  912. }
  913. static bool sprd_uart_is_console(struct uart_port *uport)
  914. {
  915. struct console *cons = sprd_uart_driver.cons;
  916. if (cons && cons->index >= 0 && cons->index == uport->line)
  917. return true;
  918. return false;
  919. }
  920. static int sprd_clk_init(struct uart_port *uport)
  921. {
  922. struct clk *clk_uart, *clk_parent;
  923. struct sprd_uart_port *u = sprd_port[uport->line];
  924. clk_uart = devm_clk_get(uport->dev, "uart");
  925. if (IS_ERR(clk_uart)) {
  926. dev_warn(uport->dev, "uart%d can't get uart clock\n",
  927. uport->line);
  928. clk_uart = NULL;
  929. }
  930. clk_parent = devm_clk_get(uport->dev, "source");
  931. if (IS_ERR(clk_parent)) {
  932. dev_warn(uport->dev, "uart%d can't get source clock\n",
  933. uport->line);
  934. clk_parent = NULL;
  935. }
  936. if (!clk_uart || clk_set_parent(clk_uart, clk_parent))
  937. uport->uartclk = SPRD_DEFAULT_SOURCE_CLK;
  938. else
  939. uport->uartclk = clk_get_rate(clk_uart);
  940. u->clk = devm_clk_get(uport->dev, "enable");
  941. if (IS_ERR(u->clk)) {
  942. if (PTR_ERR(u->clk) == -EPROBE_DEFER)
  943. return -EPROBE_DEFER;
  944. dev_warn(uport->dev, "uart%d can't get enable clock\n",
  945. uport->line);
  946. /* To keep console alive even if the error occurred */
  947. if (!sprd_uart_is_console(uport))
  948. return PTR_ERR(u->clk);
  949. u->clk = NULL;
  950. }
  951. return 0;
  952. }
  953. static int sprd_probe(struct platform_device *pdev)
  954. {
  955. struct resource *res;
  956. struct uart_port *up;
  957. int irq;
  958. int index;
  959. int ret;
  960. for (index = 0; index < ARRAY_SIZE(sprd_port); index++)
  961. if (sprd_port[index] == NULL)
  962. break;
  963. if (index == ARRAY_SIZE(sprd_port))
  964. return -EBUSY;
  965. index = sprd_probe_dt_alias(index, &pdev->dev);
  966. sprd_port[index] = devm_kzalloc(&pdev->dev, sizeof(*sprd_port[index]),
  967. GFP_KERNEL);
  968. if (!sprd_port[index])
  969. return -ENOMEM;
  970. up = &sprd_port[index]->port;
  971. up->dev = &pdev->dev;
  972. up->line = index;
  973. up->type = PORT_SPRD;
  974. up->iotype = UPIO_MEM;
  975. up->uartclk = SPRD_DEF_RATE;
  976. up->fifosize = SPRD_FIFO_SIZE;
  977. up->ops = &serial_sprd_ops;
  978. up->flags = UPF_BOOT_AUTOCONF;
  979. ret = sprd_clk_init(up);
  980. if (ret)
  981. return ret;
  982. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  983. up->membase = devm_ioremap_resource(&pdev->dev, res);
  984. if (IS_ERR(up->membase))
  985. return PTR_ERR(up->membase);
  986. up->mapbase = res->start;
  987. irq = platform_get_irq(pdev, 0);
  988. if (irq < 0)
  989. return irq;
  990. up->irq = irq;
  991. /*
  992. * Allocate one dma buffer to prepare for receive transfer, in case
  993. * memory allocation failure at runtime.
  994. */
  995. ret = sprd_rx_alloc_buf(sprd_port[index]);
  996. if (ret)
  997. return ret;
  998. if (!sprd_ports_num) {
  999. ret = uart_register_driver(&sprd_uart_driver);
  1000. if (ret < 0) {
  1001. pr_err("Failed to register SPRD-UART driver\n");
  1002. return ret;
  1003. }
  1004. }
  1005. sprd_ports_num++;
  1006. ret = uart_add_one_port(&sprd_uart_driver, up);
  1007. if (ret) {
  1008. sprd_port[index] = NULL;
  1009. sprd_remove(pdev);
  1010. }
  1011. platform_set_drvdata(pdev, up);
  1012. return ret;
  1013. }
  1014. #ifdef CONFIG_PM_SLEEP
  1015. static int sprd_suspend(struct device *dev)
  1016. {
  1017. struct sprd_uart_port *sup = dev_get_drvdata(dev);
  1018. uart_suspend_port(&sprd_uart_driver, &sup->port);
  1019. return 0;
  1020. }
  1021. static int sprd_resume(struct device *dev)
  1022. {
  1023. struct sprd_uart_port *sup = dev_get_drvdata(dev);
  1024. uart_resume_port(&sprd_uart_driver, &sup->port);
  1025. return 0;
  1026. }
  1027. #endif
  1028. static SIMPLE_DEV_PM_OPS(sprd_pm_ops, sprd_suspend, sprd_resume);
  1029. static const struct of_device_id serial_ids[] = {
  1030. {.compatible = "sprd,sc9836-uart",},
  1031. {}
  1032. };
  1033. MODULE_DEVICE_TABLE(of, serial_ids);
  1034. static struct platform_driver sprd_platform_driver = {
  1035. .probe = sprd_probe,
  1036. .remove = sprd_remove,
  1037. .driver = {
  1038. .name = "sprd_serial",
  1039. .of_match_table = of_match_ptr(serial_ids),
  1040. .pm = &sprd_pm_ops,
  1041. },
  1042. };
  1043. module_platform_driver(sprd_platform_driver);
  1044. MODULE_LICENSE("GPL v2");
  1045. MODULE_DESCRIPTION("Spreadtrum SoC serial driver series");