sirfsoc_uart.c 47 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Driver for CSR SiRFprimaII onboard UARTs.
  4. *
  5. * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
  6. */
  7. #include <linux/module.h>
  8. #include <linux/ioport.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/init.h>
  11. #include <linux/sysrq.h>
  12. #include <linux/console.h>
  13. #include <linux/tty.h>
  14. #include <linux/tty_flip.h>
  15. #include <linux/serial_core.h>
  16. #include <linux/serial.h>
  17. #include <linux/clk.h>
  18. #include <linux/of.h>
  19. #include <linux/slab.h>
  20. #include <linux/io.h>
  21. #include <linux/of_gpio.h>
  22. #include <linux/dmaengine.h>
  23. #include <linux/dma-direction.h>
  24. #include <linux/dma-mapping.h>
  25. #include <asm/irq.h>
  26. #include <asm/mach/irq.h>
  27. #include "sirfsoc_uart.h"
  28. static unsigned int
  29. sirfsoc_uart_pio_tx_chars(struct sirfsoc_uart_port *sirfport, int count);
  30. static unsigned int
  31. sirfsoc_uart_pio_rx_chars(struct uart_port *port, unsigned int max_rx_count);
  32. static struct uart_driver sirfsoc_uart_drv;
  33. static void sirfsoc_uart_tx_dma_complete_callback(void *param);
  34. static const struct sirfsoc_baudrate_to_regv baudrate_to_regv[] = {
  35. {4000000, 2359296},
  36. {3500000, 1310721},
  37. {3000000, 1572865},
  38. {2500000, 1245186},
  39. {2000000, 1572866},
  40. {1500000, 1245188},
  41. {1152000, 1638404},
  42. {1000000, 1572869},
  43. {921600, 1114120},
  44. {576000, 1245196},
  45. {500000, 1245198},
  46. {460800, 1572876},
  47. {230400, 1310750},
  48. {115200, 1310781},
  49. {57600, 1310843},
  50. {38400, 1114328},
  51. {19200, 1114545},
  52. {9600, 1114979},
  53. };
  54. static struct sirfsoc_uart_port *sirf_ports[SIRFSOC_UART_NR];
  55. static inline struct sirfsoc_uart_port *to_sirfport(struct uart_port *port)
  56. {
  57. return container_of(port, struct sirfsoc_uart_port, port);
  58. }
  59. static inline unsigned int sirfsoc_uart_tx_empty(struct uart_port *port)
  60. {
  61. unsigned long reg;
  62. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  63. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  64. struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
  65. reg = rd_regl(port, ureg->sirfsoc_tx_fifo_status);
  66. return (reg & ufifo_st->ff_empty(port)) ? TIOCSER_TEMT : 0;
  67. }
  68. static unsigned int sirfsoc_uart_get_mctrl(struct uart_port *port)
  69. {
  70. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  71. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  72. if (!sirfport->hw_flow_ctrl || !sirfport->ms_enabled)
  73. goto cts_asserted;
  74. if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
  75. if (!(rd_regl(port, ureg->sirfsoc_afc_ctrl) &
  76. SIRFUART_AFC_CTS_STATUS))
  77. goto cts_asserted;
  78. else
  79. goto cts_deasserted;
  80. } else {
  81. if (!gpio_get_value(sirfport->cts_gpio))
  82. goto cts_asserted;
  83. else
  84. goto cts_deasserted;
  85. }
  86. cts_deasserted:
  87. return TIOCM_CAR | TIOCM_DSR;
  88. cts_asserted:
  89. return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
  90. }
  91. static void sirfsoc_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
  92. {
  93. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  94. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  95. unsigned int assert = mctrl & TIOCM_RTS;
  96. unsigned int val = assert ? SIRFUART_AFC_CTRL_RX_THD : 0x0;
  97. unsigned int current_val;
  98. if (mctrl & TIOCM_LOOP) {
  99. if (sirfport->uart_reg->uart_type == SIRF_REAL_UART)
  100. wr_regl(port, ureg->sirfsoc_line_ctrl,
  101. rd_regl(port, ureg->sirfsoc_line_ctrl) |
  102. SIRFUART_LOOP_BACK);
  103. else
  104. wr_regl(port, ureg->sirfsoc_mode1,
  105. rd_regl(port, ureg->sirfsoc_mode1) |
  106. SIRFSOC_USP_LOOP_BACK_CTRL);
  107. } else {
  108. if (sirfport->uart_reg->uart_type == SIRF_REAL_UART)
  109. wr_regl(port, ureg->sirfsoc_line_ctrl,
  110. rd_regl(port, ureg->sirfsoc_line_ctrl) &
  111. ~SIRFUART_LOOP_BACK);
  112. else
  113. wr_regl(port, ureg->sirfsoc_mode1,
  114. rd_regl(port, ureg->sirfsoc_mode1) &
  115. ~SIRFSOC_USP_LOOP_BACK_CTRL);
  116. }
  117. if (!sirfport->hw_flow_ctrl || !sirfport->ms_enabled)
  118. return;
  119. if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
  120. current_val = rd_regl(port, ureg->sirfsoc_afc_ctrl) & ~0xFF;
  121. val |= current_val;
  122. wr_regl(port, ureg->sirfsoc_afc_ctrl, val);
  123. } else {
  124. if (!val)
  125. gpio_set_value(sirfport->rts_gpio, 1);
  126. else
  127. gpio_set_value(sirfport->rts_gpio, 0);
  128. }
  129. }
  130. static void sirfsoc_uart_stop_tx(struct uart_port *port)
  131. {
  132. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  133. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  134. struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
  135. if (sirfport->tx_dma_chan) {
  136. if (sirfport->tx_dma_state == TX_DMA_RUNNING) {
  137. dmaengine_pause(sirfport->tx_dma_chan);
  138. sirfport->tx_dma_state = TX_DMA_PAUSE;
  139. } else {
  140. if (!sirfport->is_atlas7)
  141. wr_regl(port, ureg->sirfsoc_int_en_reg,
  142. rd_regl(port, ureg->sirfsoc_int_en_reg) &
  143. ~uint_en->sirfsoc_txfifo_empty_en);
  144. else
  145. wr_regl(port, ureg->sirfsoc_int_en_clr_reg,
  146. uint_en->sirfsoc_txfifo_empty_en);
  147. }
  148. } else {
  149. if (sirfport->uart_reg->uart_type == SIRF_USP_UART)
  150. wr_regl(port, ureg->sirfsoc_tx_rx_en, rd_regl(port,
  151. ureg->sirfsoc_tx_rx_en) & ~SIRFUART_TX_EN);
  152. if (!sirfport->is_atlas7)
  153. wr_regl(port, ureg->sirfsoc_int_en_reg,
  154. rd_regl(port, ureg->sirfsoc_int_en_reg) &
  155. ~uint_en->sirfsoc_txfifo_empty_en);
  156. else
  157. wr_regl(port, ureg->sirfsoc_int_en_clr_reg,
  158. uint_en->sirfsoc_txfifo_empty_en);
  159. }
  160. }
  161. static void sirfsoc_uart_tx_with_dma(struct sirfsoc_uart_port *sirfport)
  162. {
  163. struct uart_port *port = &sirfport->port;
  164. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  165. struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
  166. struct circ_buf *xmit = &port->state->xmit;
  167. unsigned long tran_size;
  168. unsigned long tran_start;
  169. unsigned long pio_tx_size;
  170. tran_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
  171. tran_start = (unsigned long)(xmit->buf + xmit->tail);
  172. if (uart_circ_empty(xmit) || uart_tx_stopped(port) ||
  173. !tran_size)
  174. return;
  175. if (sirfport->tx_dma_state == TX_DMA_PAUSE) {
  176. dmaengine_resume(sirfport->tx_dma_chan);
  177. return;
  178. }
  179. if (sirfport->tx_dma_state == TX_DMA_RUNNING)
  180. return;
  181. if (!sirfport->is_atlas7)
  182. wr_regl(port, ureg->sirfsoc_int_en_reg,
  183. rd_regl(port, ureg->sirfsoc_int_en_reg)&
  184. ~(uint_en->sirfsoc_txfifo_empty_en));
  185. else
  186. wr_regl(port, ureg->sirfsoc_int_en_clr_reg,
  187. uint_en->sirfsoc_txfifo_empty_en);
  188. /*
  189. * DMA requires buffer address and buffer length are both aligned with
  190. * 4 bytes, so we use PIO for
  191. * 1. if address is not aligned with 4bytes, use PIO for the first 1~3
  192. * bytes, and move to DMA for the left part aligned with 4bytes
  193. * 2. if buffer length is not aligned with 4bytes, use DMA for aligned
  194. * part first, move to PIO for the left 1~3 bytes
  195. */
  196. if (tran_size < 4 || BYTES_TO_ALIGN(tran_start)) {
  197. wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_STOP);
  198. wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl,
  199. rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl)|
  200. SIRFUART_IO_MODE);
  201. if (BYTES_TO_ALIGN(tran_start)) {
  202. pio_tx_size = sirfsoc_uart_pio_tx_chars(sirfport,
  203. BYTES_TO_ALIGN(tran_start));
  204. tran_size -= pio_tx_size;
  205. }
  206. if (tran_size < 4)
  207. sirfsoc_uart_pio_tx_chars(sirfport, tran_size);
  208. if (!sirfport->is_atlas7)
  209. wr_regl(port, ureg->sirfsoc_int_en_reg,
  210. rd_regl(port, ureg->sirfsoc_int_en_reg)|
  211. uint_en->sirfsoc_txfifo_empty_en);
  212. else
  213. wr_regl(port, ureg->sirfsoc_int_en_reg,
  214. uint_en->sirfsoc_txfifo_empty_en);
  215. wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_START);
  216. } else {
  217. /* tx transfer mode switch into dma mode */
  218. wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_STOP);
  219. wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl,
  220. rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl)&
  221. ~SIRFUART_IO_MODE);
  222. wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_START);
  223. tran_size &= ~(0x3);
  224. sirfport->tx_dma_addr = dma_map_single(port->dev,
  225. xmit->buf + xmit->tail,
  226. tran_size, DMA_TO_DEVICE);
  227. sirfport->tx_dma_desc = dmaengine_prep_slave_single(
  228. sirfport->tx_dma_chan, sirfport->tx_dma_addr,
  229. tran_size, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
  230. if (!sirfport->tx_dma_desc) {
  231. dev_err(port->dev, "DMA prep slave single fail\n");
  232. return;
  233. }
  234. sirfport->tx_dma_desc->callback =
  235. sirfsoc_uart_tx_dma_complete_callback;
  236. sirfport->tx_dma_desc->callback_param = (void *)sirfport;
  237. sirfport->transfer_size = tran_size;
  238. dmaengine_submit(sirfport->tx_dma_desc);
  239. dma_async_issue_pending(sirfport->tx_dma_chan);
  240. sirfport->tx_dma_state = TX_DMA_RUNNING;
  241. }
  242. }
  243. static void sirfsoc_uart_start_tx(struct uart_port *port)
  244. {
  245. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  246. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  247. struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
  248. if (sirfport->tx_dma_chan)
  249. sirfsoc_uart_tx_with_dma(sirfport);
  250. else {
  251. if (sirfport->uart_reg->uart_type == SIRF_USP_UART)
  252. wr_regl(port, ureg->sirfsoc_tx_rx_en, rd_regl(port,
  253. ureg->sirfsoc_tx_rx_en) | SIRFUART_TX_EN);
  254. wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_STOP);
  255. sirfsoc_uart_pio_tx_chars(sirfport, port->fifosize);
  256. wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_START);
  257. if (!sirfport->is_atlas7)
  258. wr_regl(port, ureg->sirfsoc_int_en_reg,
  259. rd_regl(port, ureg->sirfsoc_int_en_reg)|
  260. uint_en->sirfsoc_txfifo_empty_en);
  261. else
  262. wr_regl(port, ureg->sirfsoc_int_en_reg,
  263. uint_en->sirfsoc_txfifo_empty_en);
  264. }
  265. }
  266. static void sirfsoc_uart_stop_rx(struct uart_port *port)
  267. {
  268. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  269. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  270. struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
  271. wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
  272. if (sirfport->rx_dma_chan) {
  273. if (!sirfport->is_atlas7)
  274. wr_regl(port, ureg->sirfsoc_int_en_reg,
  275. rd_regl(port, ureg->sirfsoc_int_en_reg) &
  276. ~(SIRFUART_RX_DMA_INT_EN(uint_en,
  277. sirfport->uart_reg->uart_type) |
  278. uint_en->sirfsoc_rx_done_en));
  279. else
  280. wr_regl(port, ureg->sirfsoc_int_en_clr_reg,
  281. SIRFUART_RX_DMA_INT_EN(uint_en,
  282. sirfport->uart_reg->uart_type)|
  283. uint_en->sirfsoc_rx_done_en);
  284. dmaengine_terminate_all(sirfport->rx_dma_chan);
  285. } else {
  286. if (!sirfport->is_atlas7)
  287. wr_regl(port, ureg->sirfsoc_int_en_reg,
  288. rd_regl(port, ureg->sirfsoc_int_en_reg)&
  289. ~(SIRFUART_RX_IO_INT_EN(uint_en,
  290. sirfport->uart_reg->uart_type)));
  291. else
  292. wr_regl(port, ureg->sirfsoc_int_en_clr_reg,
  293. SIRFUART_RX_IO_INT_EN(uint_en,
  294. sirfport->uart_reg->uart_type));
  295. }
  296. }
  297. static void sirfsoc_uart_disable_ms(struct uart_port *port)
  298. {
  299. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  300. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  301. struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
  302. if (!sirfport->hw_flow_ctrl)
  303. return;
  304. sirfport->ms_enabled = false;
  305. if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
  306. wr_regl(port, ureg->sirfsoc_afc_ctrl,
  307. rd_regl(port, ureg->sirfsoc_afc_ctrl) & ~0x3FF);
  308. if (!sirfport->is_atlas7)
  309. wr_regl(port, ureg->sirfsoc_int_en_reg,
  310. rd_regl(port, ureg->sirfsoc_int_en_reg)&
  311. ~uint_en->sirfsoc_cts_en);
  312. else
  313. wr_regl(port, ureg->sirfsoc_int_en_clr_reg,
  314. uint_en->sirfsoc_cts_en);
  315. } else
  316. disable_irq(gpio_to_irq(sirfport->cts_gpio));
  317. }
  318. static irqreturn_t sirfsoc_uart_usp_cts_handler(int irq, void *dev_id)
  319. {
  320. struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)dev_id;
  321. struct uart_port *port = &sirfport->port;
  322. spin_lock(&port->lock);
  323. if (gpio_is_valid(sirfport->cts_gpio) && sirfport->ms_enabled)
  324. uart_handle_cts_change(port,
  325. !gpio_get_value(sirfport->cts_gpio));
  326. spin_unlock(&port->lock);
  327. return IRQ_HANDLED;
  328. }
  329. static void sirfsoc_uart_enable_ms(struct uart_port *port)
  330. {
  331. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  332. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  333. struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
  334. if (!sirfport->hw_flow_ctrl)
  335. return;
  336. sirfport->ms_enabled = true;
  337. if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
  338. wr_regl(port, ureg->sirfsoc_afc_ctrl,
  339. rd_regl(port, ureg->sirfsoc_afc_ctrl) |
  340. SIRFUART_AFC_TX_EN | SIRFUART_AFC_RX_EN |
  341. SIRFUART_AFC_CTRL_RX_THD);
  342. if (!sirfport->is_atlas7)
  343. wr_regl(port, ureg->sirfsoc_int_en_reg,
  344. rd_regl(port, ureg->sirfsoc_int_en_reg)
  345. | uint_en->sirfsoc_cts_en);
  346. else
  347. wr_regl(port, ureg->sirfsoc_int_en_reg,
  348. uint_en->sirfsoc_cts_en);
  349. } else
  350. enable_irq(gpio_to_irq(sirfport->cts_gpio));
  351. }
  352. static void sirfsoc_uart_break_ctl(struct uart_port *port, int break_state)
  353. {
  354. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  355. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  356. if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
  357. unsigned long ulcon = rd_regl(port, ureg->sirfsoc_line_ctrl);
  358. if (break_state)
  359. ulcon |= SIRFUART_SET_BREAK;
  360. else
  361. ulcon &= ~SIRFUART_SET_BREAK;
  362. wr_regl(port, ureg->sirfsoc_line_ctrl, ulcon);
  363. }
  364. }
  365. static unsigned int
  366. sirfsoc_uart_pio_rx_chars(struct uart_port *port, unsigned int max_rx_count)
  367. {
  368. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  369. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  370. struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
  371. unsigned int ch, rx_count = 0;
  372. struct tty_struct *tty;
  373. tty = tty_port_tty_get(&port->state->port);
  374. if (!tty)
  375. return -ENODEV;
  376. while (!(rd_regl(port, ureg->sirfsoc_rx_fifo_status) &
  377. ufifo_st->ff_empty(port))) {
  378. ch = rd_regl(port, ureg->sirfsoc_rx_fifo_data) |
  379. SIRFUART_DUMMY_READ;
  380. if (unlikely(uart_handle_sysrq_char(port, ch)))
  381. continue;
  382. uart_insert_char(port, 0, 0, ch, TTY_NORMAL);
  383. rx_count++;
  384. if (rx_count >= max_rx_count)
  385. break;
  386. }
  387. port->icount.rx += rx_count;
  388. return rx_count;
  389. }
  390. static unsigned int
  391. sirfsoc_uart_pio_tx_chars(struct sirfsoc_uart_port *sirfport, int count)
  392. {
  393. struct uart_port *port = &sirfport->port;
  394. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  395. struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
  396. struct circ_buf *xmit = &port->state->xmit;
  397. unsigned int num_tx = 0;
  398. while (!uart_circ_empty(xmit) &&
  399. !(rd_regl(port, ureg->sirfsoc_tx_fifo_status) &
  400. ufifo_st->ff_full(port)) &&
  401. count--) {
  402. wr_regl(port, ureg->sirfsoc_tx_fifo_data,
  403. xmit->buf[xmit->tail]);
  404. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  405. port->icount.tx++;
  406. num_tx++;
  407. }
  408. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  409. uart_write_wakeup(port);
  410. return num_tx;
  411. }
  412. static void sirfsoc_uart_tx_dma_complete_callback(void *param)
  413. {
  414. struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)param;
  415. struct uart_port *port = &sirfport->port;
  416. struct circ_buf *xmit = &port->state->xmit;
  417. unsigned long flags;
  418. spin_lock_irqsave(&port->lock, flags);
  419. xmit->tail = (xmit->tail + sirfport->transfer_size) &
  420. (UART_XMIT_SIZE - 1);
  421. port->icount.tx += sirfport->transfer_size;
  422. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  423. uart_write_wakeup(port);
  424. if (sirfport->tx_dma_addr)
  425. dma_unmap_single(port->dev, sirfport->tx_dma_addr,
  426. sirfport->transfer_size, DMA_TO_DEVICE);
  427. sirfport->tx_dma_state = TX_DMA_IDLE;
  428. sirfsoc_uart_tx_with_dma(sirfport);
  429. spin_unlock_irqrestore(&port->lock, flags);
  430. }
  431. static irqreturn_t sirfsoc_uart_isr(int irq, void *dev_id)
  432. {
  433. unsigned long intr_status;
  434. unsigned long cts_status;
  435. unsigned long flag = TTY_NORMAL;
  436. struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)dev_id;
  437. struct uart_port *port = &sirfport->port;
  438. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  439. struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
  440. struct sirfsoc_int_status *uint_st = &sirfport->uart_reg->uart_int_st;
  441. struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
  442. struct uart_state *state = port->state;
  443. struct circ_buf *xmit = &port->state->xmit;
  444. spin_lock(&port->lock);
  445. intr_status = rd_regl(port, ureg->sirfsoc_int_st_reg);
  446. wr_regl(port, ureg->sirfsoc_int_st_reg, intr_status);
  447. intr_status &= rd_regl(port, ureg->sirfsoc_int_en_reg);
  448. if (unlikely(intr_status & (SIRFUART_ERR_INT_STAT(uint_st,
  449. sirfport->uart_reg->uart_type)))) {
  450. if (intr_status & uint_st->sirfsoc_rxd_brk) {
  451. port->icount.brk++;
  452. if (uart_handle_break(port))
  453. goto recv_char;
  454. }
  455. if (intr_status & uint_st->sirfsoc_rx_oflow) {
  456. port->icount.overrun++;
  457. flag = TTY_OVERRUN;
  458. }
  459. if (intr_status & uint_st->sirfsoc_frm_err) {
  460. port->icount.frame++;
  461. flag = TTY_FRAME;
  462. }
  463. if (intr_status & uint_st->sirfsoc_parity_err) {
  464. port->icount.parity++;
  465. flag = TTY_PARITY;
  466. }
  467. wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_RESET);
  468. wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
  469. wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_START);
  470. intr_status &= port->read_status_mask;
  471. uart_insert_char(port, intr_status,
  472. uint_en->sirfsoc_rx_oflow_en, 0, flag);
  473. }
  474. recv_char:
  475. if ((sirfport->uart_reg->uart_type == SIRF_REAL_UART) &&
  476. (intr_status & SIRFUART_CTS_INT_ST(uint_st)) &&
  477. !sirfport->tx_dma_state) {
  478. cts_status = rd_regl(port, ureg->sirfsoc_afc_ctrl) &
  479. SIRFUART_AFC_CTS_STATUS;
  480. if (cts_status != 0)
  481. cts_status = 0;
  482. else
  483. cts_status = 1;
  484. uart_handle_cts_change(port, cts_status);
  485. wake_up_interruptible(&state->port.delta_msr_wait);
  486. }
  487. if (!sirfport->rx_dma_chan &&
  488. (intr_status & SIRFUART_RX_IO_INT_ST(uint_st))) {
  489. /*
  490. * chip will trigger continuous RX_TIMEOUT interrupt
  491. * in RXFIFO empty and not trigger if RXFIFO recevice
  492. * data in limit time, original method use RX_TIMEOUT
  493. * will trigger lots of useless interrupt in RXFIFO
  494. * empty.RXFIFO received one byte will trigger RX_DONE
  495. * interrupt.use RX_DONE to wait for data received
  496. * into RXFIFO, use RX_THD/RX_FULL for lots data receive
  497. * and use RX_TIMEOUT for the last left data.
  498. */
  499. if (intr_status & uint_st->sirfsoc_rx_done) {
  500. if (!sirfport->is_atlas7) {
  501. wr_regl(port, ureg->sirfsoc_int_en_reg,
  502. rd_regl(port, ureg->sirfsoc_int_en_reg)
  503. & ~(uint_en->sirfsoc_rx_done_en));
  504. wr_regl(port, ureg->sirfsoc_int_en_reg,
  505. rd_regl(port, ureg->sirfsoc_int_en_reg)
  506. | (uint_en->sirfsoc_rx_timeout_en));
  507. } else {
  508. wr_regl(port, ureg->sirfsoc_int_en_clr_reg,
  509. uint_en->sirfsoc_rx_done_en);
  510. wr_regl(port, ureg->sirfsoc_int_en_reg,
  511. uint_en->sirfsoc_rx_timeout_en);
  512. }
  513. } else {
  514. if (intr_status & uint_st->sirfsoc_rx_timeout) {
  515. if (!sirfport->is_atlas7) {
  516. wr_regl(port, ureg->sirfsoc_int_en_reg,
  517. rd_regl(port, ureg->sirfsoc_int_en_reg)
  518. & ~(uint_en->sirfsoc_rx_timeout_en));
  519. wr_regl(port, ureg->sirfsoc_int_en_reg,
  520. rd_regl(port, ureg->sirfsoc_int_en_reg)
  521. | (uint_en->sirfsoc_rx_done_en));
  522. } else {
  523. wr_regl(port,
  524. ureg->sirfsoc_int_en_clr_reg,
  525. uint_en->sirfsoc_rx_timeout_en);
  526. wr_regl(port, ureg->sirfsoc_int_en_reg,
  527. uint_en->sirfsoc_rx_done_en);
  528. }
  529. }
  530. sirfsoc_uart_pio_rx_chars(port, port->fifosize);
  531. }
  532. }
  533. spin_unlock(&port->lock);
  534. tty_flip_buffer_push(&state->port);
  535. spin_lock(&port->lock);
  536. if (intr_status & uint_st->sirfsoc_txfifo_empty) {
  537. if (sirfport->tx_dma_chan)
  538. sirfsoc_uart_tx_with_dma(sirfport);
  539. else {
  540. if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
  541. spin_unlock(&port->lock);
  542. return IRQ_HANDLED;
  543. } else {
  544. sirfsoc_uart_pio_tx_chars(sirfport,
  545. port->fifosize);
  546. if ((uart_circ_empty(xmit)) &&
  547. (rd_regl(port, ureg->sirfsoc_tx_fifo_status) &
  548. ufifo_st->ff_empty(port)))
  549. sirfsoc_uart_stop_tx(port);
  550. }
  551. }
  552. }
  553. spin_unlock(&port->lock);
  554. return IRQ_HANDLED;
  555. }
  556. static void sirfsoc_uart_rx_dma_complete_callback(void *param)
  557. {
  558. }
  559. /* submit rx dma task into dmaengine */
  560. static void sirfsoc_uart_start_next_rx_dma(struct uart_port *port)
  561. {
  562. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  563. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  564. struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
  565. wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
  566. rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) &
  567. ~SIRFUART_IO_MODE);
  568. sirfport->rx_dma_items.xmit.tail =
  569. sirfport->rx_dma_items.xmit.head = 0;
  570. sirfport->rx_dma_items.desc =
  571. dmaengine_prep_dma_cyclic(sirfport->rx_dma_chan,
  572. sirfport->rx_dma_items.dma_addr, SIRFSOC_RX_DMA_BUF_SIZE,
  573. SIRFSOC_RX_DMA_BUF_SIZE / 2,
  574. DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
  575. if (IS_ERR_OR_NULL(sirfport->rx_dma_items.desc)) {
  576. dev_err(port->dev, "DMA slave single fail\n");
  577. return;
  578. }
  579. sirfport->rx_dma_items.desc->callback =
  580. sirfsoc_uart_rx_dma_complete_callback;
  581. sirfport->rx_dma_items.desc->callback_param = sirfport;
  582. sirfport->rx_dma_items.cookie =
  583. dmaengine_submit(sirfport->rx_dma_items.desc);
  584. dma_async_issue_pending(sirfport->rx_dma_chan);
  585. if (!sirfport->is_atlas7)
  586. wr_regl(port, ureg->sirfsoc_int_en_reg,
  587. rd_regl(port, ureg->sirfsoc_int_en_reg) |
  588. SIRFUART_RX_DMA_INT_EN(uint_en,
  589. sirfport->uart_reg->uart_type));
  590. else
  591. wr_regl(port, ureg->sirfsoc_int_en_reg,
  592. SIRFUART_RX_DMA_INT_EN(uint_en,
  593. sirfport->uart_reg->uart_type));
  594. }
  595. static unsigned int
  596. sirfsoc_usp_calc_sample_div(unsigned long set_rate,
  597. unsigned long ioclk_rate, unsigned long *sample_reg)
  598. {
  599. unsigned long min_delta = ~0UL;
  600. unsigned short sample_div;
  601. unsigned long ioclk_div = 0;
  602. unsigned long temp_delta;
  603. for (sample_div = SIRF_USP_MIN_SAMPLE_DIV;
  604. sample_div <= SIRF_MAX_SAMPLE_DIV; sample_div++) {
  605. temp_delta = ioclk_rate -
  606. (ioclk_rate + (set_rate * sample_div) / 2)
  607. / (set_rate * sample_div) * set_rate * sample_div;
  608. temp_delta = (temp_delta > 0) ? temp_delta : -temp_delta;
  609. if (temp_delta < min_delta) {
  610. ioclk_div = (2 * ioclk_rate /
  611. (set_rate * sample_div) + 1) / 2 - 1;
  612. if (ioclk_div > SIRF_IOCLK_DIV_MAX)
  613. continue;
  614. min_delta = temp_delta;
  615. *sample_reg = sample_div;
  616. if (!temp_delta)
  617. break;
  618. }
  619. }
  620. return ioclk_div;
  621. }
  622. static unsigned int
  623. sirfsoc_uart_calc_sample_div(unsigned long baud_rate,
  624. unsigned long ioclk_rate, unsigned long *set_baud)
  625. {
  626. unsigned long min_delta = ~0UL;
  627. unsigned short sample_div;
  628. unsigned int regv = 0;
  629. unsigned long ioclk_div;
  630. unsigned long baud_tmp;
  631. int temp_delta;
  632. for (sample_div = SIRF_MIN_SAMPLE_DIV;
  633. sample_div <= SIRF_MAX_SAMPLE_DIV; sample_div++) {
  634. ioclk_div = (ioclk_rate / (baud_rate * (sample_div + 1))) - 1;
  635. if (ioclk_div > SIRF_IOCLK_DIV_MAX)
  636. continue;
  637. baud_tmp = ioclk_rate / ((ioclk_div + 1) * (sample_div + 1));
  638. temp_delta = baud_tmp - baud_rate;
  639. temp_delta = (temp_delta > 0) ? temp_delta : -temp_delta;
  640. if (temp_delta < min_delta) {
  641. regv = regv & (~SIRF_IOCLK_DIV_MASK);
  642. regv = regv | ioclk_div;
  643. regv = regv & (~SIRF_SAMPLE_DIV_MASK);
  644. regv = regv | (sample_div << SIRF_SAMPLE_DIV_SHIFT);
  645. min_delta = temp_delta;
  646. *set_baud = baud_tmp;
  647. }
  648. }
  649. return regv;
  650. }
  651. static void sirfsoc_uart_set_termios(struct uart_port *port,
  652. struct ktermios *termios,
  653. struct ktermios *old)
  654. {
  655. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  656. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  657. struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
  658. unsigned long config_reg = 0;
  659. unsigned long baud_rate;
  660. unsigned long set_baud;
  661. unsigned long flags;
  662. unsigned long ic;
  663. unsigned int clk_div_reg = 0;
  664. unsigned long txfifo_op_reg, ioclk_rate;
  665. unsigned long rx_time_out;
  666. int threshold_div;
  667. u32 data_bit_len, stop_bit_len, len_val;
  668. unsigned long sample_div_reg = 0xf;
  669. ioclk_rate = port->uartclk;
  670. switch (termios->c_cflag & CSIZE) {
  671. default:
  672. case CS8:
  673. data_bit_len = 8;
  674. config_reg |= SIRFUART_DATA_BIT_LEN_8;
  675. break;
  676. case CS7:
  677. data_bit_len = 7;
  678. config_reg |= SIRFUART_DATA_BIT_LEN_7;
  679. break;
  680. case CS6:
  681. data_bit_len = 6;
  682. config_reg |= SIRFUART_DATA_BIT_LEN_6;
  683. break;
  684. case CS5:
  685. data_bit_len = 5;
  686. config_reg |= SIRFUART_DATA_BIT_LEN_5;
  687. break;
  688. }
  689. if (termios->c_cflag & CSTOPB) {
  690. config_reg |= SIRFUART_STOP_BIT_LEN_2;
  691. stop_bit_len = 2;
  692. } else
  693. stop_bit_len = 1;
  694. spin_lock_irqsave(&port->lock, flags);
  695. port->read_status_mask = uint_en->sirfsoc_rx_oflow_en;
  696. port->ignore_status_mask = 0;
  697. if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
  698. if (termios->c_iflag & INPCK)
  699. port->read_status_mask |= uint_en->sirfsoc_frm_err_en |
  700. uint_en->sirfsoc_parity_err_en;
  701. } else {
  702. if (termios->c_iflag & INPCK)
  703. port->read_status_mask |= uint_en->sirfsoc_frm_err_en;
  704. }
  705. if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
  706. port->read_status_mask |= uint_en->sirfsoc_rxd_brk_en;
  707. if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
  708. if (termios->c_iflag & IGNPAR)
  709. port->ignore_status_mask |=
  710. uint_en->sirfsoc_frm_err_en |
  711. uint_en->sirfsoc_parity_err_en;
  712. if (termios->c_cflag & PARENB) {
  713. if (termios->c_cflag & CMSPAR) {
  714. if (termios->c_cflag & PARODD)
  715. config_reg |= SIRFUART_STICK_BIT_MARK;
  716. else
  717. config_reg |= SIRFUART_STICK_BIT_SPACE;
  718. } else {
  719. if (termios->c_cflag & PARODD)
  720. config_reg |= SIRFUART_STICK_BIT_ODD;
  721. else
  722. config_reg |= SIRFUART_STICK_BIT_EVEN;
  723. }
  724. }
  725. } else {
  726. if (termios->c_iflag & IGNPAR)
  727. port->ignore_status_mask |=
  728. uint_en->sirfsoc_frm_err_en;
  729. if (termios->c_cflag & PARENB)
  730. dev_warn(port->dev,
  731. "USP-UART not support parity err\n");
  732. }
  733. if (termios->c_iflag & IGNBRK) {
  734. port->ignore_status_mask |=
  735. uint_en->sirfsoc_rxd_brk_en;
  736. if (termios->c_iflag & IGNPAR)
  737. port->ignore_status_mask |=
  738. uint_en->sirfsoc_rx_oflow_en;
  739. }
  740. if ((termios->c_cflag & CREAD) == 0)
  741. port->ignore_status_mask |= SIRFUART_DUMMY_READ;
  742. /* Hardware Flow Control Settings */
  743. if (UART_ENABLE_MS(port, termios->c_cflag)) {
  744. if (!sirfport->ms_enabled)
  745. sirfsoc_uart_enable_ms(port);
  746. } else {
  747. if (sirfport->ms_enabled)
  748. sirfsoc_uart_disable_ms(port);
  749. }
  750. baud_rate = uart_get_baud_rate(port, termios, old, 0, 4000000);
  751. if (ioclk_rate == 150000000) {
  752. for (ic = 0; ic < SIRF_BAUD_RATE_SUPPORT_NR; ic++)
  753. if (baud_rate == baudrate_to_regv[ic].baud_rate)
  754. clk_div_reg = baudrate_to_regv[ic].reg_val;
  755. }
  756. set_baud = baud_rate;
  757. if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
  758. if (unlikely(clk_div_reg == 0))
  759. clk_div_reg = sirfsoc_uart_calc_sample_div(baud_rate,
  760. ioclk_rate, &set_baud);
  761. wr_regl(port, ureg->sirfsoc_divisor, clk_div_reg);
  762. } else {
  763. clk_div_reg = sirfsoc_usp_calc_sample_div(baud_rate,
  764. ioclk_rate, &sample_div_reg);
  765. sample_div_reg--;
  766. set_baud = ((ioclk_rate / (clk_div_reg+1) - 1) /
  767. (sample_div_reg + 1));
  768. /* setting usp mode 2 */
  769. len_val = ((1 << SIRFSOC_USP_MODE2_RXD_DELAY_OFFSET) |
  770. (1 << SIRFSOC_USP_MODE2_TXD_DELAY_OFFSET));
  771. len_val |= ((clk_div_reg & SIRFSOC_USP_MODE2_CLK_DIVISOR_MASK)
  772. << SIRFSOC_USP_MODE2_CLK_DIVISOR_OFFSET);
  773. wr_regl(port, ureg->sirfsoc_mode2, len_val);
  774. }
  775. if (tty_termios_baud_rate(termios))
  776. tty_termios_encode_baud_rate(termios, set_baud, set_baud);
  777. /* set receive timeout && data bits len */
  778. rx_time_out = SIRFSOC_UART_RX_TIMEOUT(set_baud, 20000);
  779. rx_time_out = SIRFUART_RECV_TIMEOUT_VALUE(rx_time_out);
  780. txfifo_op_reg = rd_regl(port, ureg->sirfsoc_tx_fifo_op);
  781. wr_regl(port, ureg->sirfsoc_tx_fifo_op,
  782. (txfifo_op_reg & ~SIRFUART_FIFO_START));
  783. if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
  784. config_reg |= SIRFUART_UART_RECV_TIMEOUT(rx_time_out);
  785. wr_regl(port, ureg->sirfsoc_line_ctrl, config_reg);
  786. } else {
  787. /*tx frame ctrl*/
  788. len_val = (data_bit_len - 1) << SIRFSOC_USP_TX_DATA_LEN_OFFSET;
  789. len_val |= (data_bit_len + 1 + stop_bit_len - 1) <<
  790. SIRFSOC_USP_TX_FRAME_LEN_OFFSET;
  791. len_val |= ((data_bit_len - 1) <<
  792. SIRFSOC_USP_TX_SHIFTER_LEN_OFFSET);
  793. len_val |= (((clk_div_reg & 0xc00) >> 10) <<
  794. SIRFSOC_USP_TX_CLK_DIVISOR_OFFSET);
  795. wr_regl(port, ureg->sirfsoc_tx_frame_ctrl, len_val);
  796. /*rx frame ctrl*/
  797. len_val = (data_bit_len - 1) << SIRFSOC_USP_RX_DATA_LEN_OFFSET;
  798. len_val |= (data_bit_len + 1 + stop_bit_len - 1) <<
  799. SIRFSOC_USP_RX_FRAME_LEN_OFFSET;
  800. len_val |= (data_bit_len - 1) <<
  801. SIRFSOC_USP_RX_SHIFTER_LEN_OFFSET;
  802. len_val |= (((clk_div_reg & 0xf000) >> 12) <<
  803. SIRFSOC_USP_RX_CLK_DIVISOR_OFFSET);
  804. wr_regl(port, ureg->sirfsoc_rx_frame_ctrl, len_val);
  805. /*async param*/
  806. wr_regl(port, ureg->sirfsoc_async_param_reg,
  807. (SIRFUART_USP_RECV_TIMEOUT(rx_time_out)) |
  808. (sample_div_reg & SIRFSOC_USP_ASYNC_DIV2_MASK) <<
  809. SIRFSOC_USP_ASYNC_DIV2_OFFSET);
  810. }
  811. if (sirfport->tx_dma_chan)
  812. wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl, SIRFUART_DMA_MODE);
  813. else
  814. wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl, SIRFUART_IO_MODE);
  815. if (sirfport->rx_dma_chan)
  816. wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
  817. rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) &
  818. ~SIRFUART_IO_MODE);
  819. else
  820. wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
  821. rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) |
  822. SIRFUART_IO_MODE);
  823. sirfport->rx_period_time = 20000000;
  824. /* Reset Rx/Tx FIFO Threshold level for proper baudrate */
  825. if (set_baud < 1000000)
  826. threshold_div = 1;
  827. else
  828. threshold_div = 2;
  829. wr_regl(port, ureg->sirfsoc_tx_fifo_ctrl,
  830. SIRFUART_FIFO_THD(port) / threshold_div);
  831. wr_regl(port, ureg->sirfsoc_rx_fifo_ctrl,
  832. SIRFUART_FIFO_THD(port) / threshold_div);
  833. txfifo_op_reg |= SIRFUART_FIFO_START;
  834. wr_regl(port, ureg->sirfsoc_tx_fifo_op, txfifo_op_reg);
  835. uart_update_timeout(port, termios->c_cflag, set_baud);
  836. wr_regl(port, ureg->sirfsoc_tx_rx_en, SIRFUART_TX_EN | SIRFUART_RX_EN);
  837. spin_unlock_irqrestore(&port->lock, flags);
  838. }
  839. static void sirfsoc_uart_pm(struct uart_port *port, unsigned int state,
  840. unsigned int oldstate)
  841. {
  842. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  843. if (!state)
  844. clk_prepare_enable(sirfport->clk);
  845. else
  846. clk_disable_unprepare(sirfport->clk);
  847. }
  848. static int sirfsoc_uart_startup(struct uart_port *port)
  849. {
  850. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  851. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  852. struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
  853. unsigned int index = port->line;
  854. int ret;
  855. irq_modify_status(port->irq, IRQ_NOREQUEST, IRQ_NOAUTOEN);
  856. ret = request_irq(port->irq,
  857. sirfsoc_uart_isr,
  858. 0,
  859. SIRFUART_PORT_NAME,
  860. sirfport);
  861. if (ret != 0) {
  862. dev_err(port->dev, "UART%d request IRQ line (%d) failed.\n",
  863. index, port->irq);
  864. goto irq_err;
  865. }
  866. /* initial hardware settings */
  867. wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl,
  868. rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl) |
  869. SIRFUART_IO_MODE);
  870. wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
  871. rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) |
  872. SIRFUART_IO_MODE);
  873. wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
  874. rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) &
  875. ~SIRFUART_RX_DMA_FLUSH);
  876. wr_regl(port, ureg->sirfsoc_tx_dma_io_len, 0);
  877. wr_regl(port, ureg->sirfsoc_rx_dma_io_len, 0);
  878. wr_regl(port, ureg->sirfsoc_tx_rx_en, SIRFUART_RX_EN | SIRFUART_TX_EN);
  879. if (sirfport->uart_reg->uart_type == SIRF_USP_UART)
  880. wr_regl(port, ureg->sirfsoc_mode1,
  881. SIRFSOC_USP_ENDIAN_CTRL_LSBF |
  882. SIRFSOC_USP_EN);
  883. wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_RESET);
  884. wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_RESET);
  885. wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
  886. wr_regl(port, ureg->sirfsoc_tx_fifo_ctrl, SIRFUART_FIFO_THD(port));
  887. wr_regl(port, ureg->sirfsoc_rx_fifo_ctrl, SIRFUART_FIFO_THD(port));
  888. if (sirfport->rx_dma_chan)
  889. wr_regl(port, ureg->sirfsoc_rx_fifo_level_chk,
  890. SIRFUART_RX_FIFO_CHK_SC(port->line, 0x1) |
  891. SIRFUART_RX_FIFO_CHK_LC(port->line, 0x2) |
  892. SIRFUART_RX_FIFO_CHK_HC(port->line, 0x4));
  893. if (sirfport->tx_dma_chan) {
  894. sirfport->tx_dma_state = TX_DMA_IDLE;
  895. wr_regl(port, ureg->sirfsoc_tx_fifo_level_chk,
  896. SIRFUART_TX_FIFO_CHK_SC(port->line, 0x1b) |
  897. SIRFUART_TX_FIFO_CHK_LC(port->line, 0xe) |
  898. SIRFUART_TX_FIFO_CHK_HC(port->line, 0x4));
  899. }
  900. sirfport->ms_enabled = false;
  901. if (sirfport->uart_reg->uart_type == SIRF_USP_UART &&
  902. sirfport->hw_flow_ctrl) {
  903. irq_modify_status(gpio_to_irq(sirfport->cts_gpio),
  904. IRQ_NOREQUEST, IRQ_NOAUTOEN);
  905. ret = request_irq(gpio_to_irq(sirfport->cts_gpio),
  906. sirfsoc_uart_usp_cts_handler, IRQF_TRIGGER_FALLING |
  907. IRQF_TRIGGER_RISING, "usp_cts_irq", sirfport);
  908. if (ret != 0) {
  909. dev_err(port->dev, "UART-USP:request gpio irq fail\n");
  910. goto init_rx_err;
  911. }
  912. }
  913. if (sirfport->uart_reg->uart_type == SIRF_REAL_UART &&
  914. sirfport->rx_dma_chan)
  915. wr_regl(port, ureg->sirfsoc_swh_dma_io,
  916. SIRFUART_CLEAR_RX_ADDR_EN);
  917. if (sirfport->uart_reg->uart_type == SIRF_USP_UART &&
  918. sirfport->rx_dma_chan)
  919. wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
  920. rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) |
  921. SIRFSOC_USP_FRADDR_CLR_EN);
  922. if (sirfport->rx_dma_chan && !sirfport->is_hrt_enabled) {
  923. sirfport->is_hrt_enabled = true;
  924. sirfport->rx_period_time = 20000000;
  925. sirfport->rx_last_pos = -1;
  926. sirfport->pio_fetch_cnt = 0;
  927. sirfport->rx_dma_items.xmit.tail =
  928. sirfport->rx_dma_items.xmit.head = 0;
  929. hrtimer_start(&sirfport->hrt,
  930. ns_to_ktime(sirfport->rx_period_time),
  931. HRTIMER_MODE_REL);
  932. }
  933. wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_START);
  934. if (sirfport->rx_dma_chan)
  935. sirfsoc_uart_start_next_rx_dma(port);
  936. else {
  937. if (!sirfport->is_atlas7)
  938. wr_regl(port, ureg->sirfsoc_int_en_reg,
  939. rd_regl(port, ureg->sirfsoc_int_en_reg) |
  940. SIRFUART_RX_IO_INT_EN(uint_en,
  941. sirfport->uart_reg->uart_type));
  942. else
  943. wr_regl(port, ureg->sirfsoc_int_en_reg,
  944. SIRFUART_RX_IO_INT_EN(uint_en,
  945. sirfport->uart_reg->uart_type));
  946. }
  947. enable_irq(port->irq);
  948. return 0;
  949. init_rx_err:
  950. free_irq(port->irq, sirfport);
  951. irq_err:
  952. return ret;
  953. }
  954. static void sirfsoc_uart_shutdown(struct uart_port *port)
  955. {
  956. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  957. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  958. struct circ_buf *xmit;
  959. xmit = &sirfport->rx_dma_items.xmit;
  960. if (!sirfport->is_atlas7)
  961. wr_regl(port, ureg->sirfsoc_int_en_reg, 0);
  962. else
  963. wr_regl(port, ureg->sirfsoc_int_en_clr_reg, ~0UL);
  964. free_irq(port->irq, sirfport);
  965. if (sirfport->ms_enabled)
  966. sirfsoc_uart_disable_ms(port);
  967. if (sirfport->uart_reg->uart_type == SIRF_USP_UART &&
  968. sirfport->hw_flow_ctrl) {
  969. gpio_set_value(sirfport->rts_gpio, 1);
  970. free_irq(gpio_to_irq(sirfport->cts_gpio), sirfport);
  971. }
  972. if (sirfport->tx_dma_chan)
  973. sirfport->tx_dma_state = TX_DMA_IDLE;
  974. if (sirfport->rx_dma_chan && sirfport->is_hrt_enabled) {
  975. while (((rd_regl(port, ureg->sirfsoc_rx_fifo_status) &
  976. SIRFUART_RX_FIFO_MASK) > sirfport->pio_fetch_cnt) &&
  977. !CIRC_CNT(xmit->head, xmit->tail,
  978. SIRFSOC_RX_DMA_BUF_SIZE))
  979. ;
  980. sirfport->is_hrt_enabled = false;
  981. hrtimer_cancel(&sirfport->hrt);
  982. }
  983. }
  984. static const char *sirfsoc_uart_type(struct uart_port *port)
  985. {
  986. return port->type == SIRFSOC_PORT_TYPE ? SIRFUART_PORT_NAME : NULL;
  987. }
  988. static int sirfsoc_uart_request_port(struct uart_port *port)
  989. {
  990. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  991. struct sirfsoc_uart_param *uart_param = &sirfport->uart_reg->uart_param;
  992. void *ret;
  993. ret = request_mem_region(port->mapbase,
  994. SIRFUART_MAP_SIZE, uart_param->port_name);
  995. return ret ? 0 : -EBUSY;
  996. }
  997. static void sirfsoc_uart_release_port(struct uart_port *port)
  998. {
  999. release_mem_region(port->mapbase, SIRFUART_MAP_SIZE);
  1000. }
  1001. static void sirfsoc_uart_config_port(struct uart_port *port, int flags)
  1002. {
  1003. if (flags & UART_CONFIG_TYPE) {
  1004. port->type = SIRFSOC_PORT_TYPE;
  1005. sirfsoc_uart_request_port(port);
  1006. }
  1007. }
  1008. static const struct uart_ops sirfsoc_uart_ops = {
  1009. .tx_empty = sirfsoc_uart_tx_empty,
  1010. .get_mctrl = sirfsoc_uart_get_mctrl,
  1011. .set_mctrl = sirfsoc_uart_set_mctrl,
  1012. .stop_tx = sirfsoc_uart_stop_tx,
  1013. .start_tx = sirfsoc_uart_start_tx,
  1014. .stop_rx = sirfsoc_uart_stop_rx,
  1015. .enable_ms = sirfsoc_uart_enable_ms,
  1016. .break_ctl = sirfsoc_uart_break_ctl,
  1017. .startup = sirfsoc_uart_startup,
  1018. .shutdown = sirfsoc_uart_shutdown,
  1019. .set_termios = sirfsoc_uart_set_termios,
  1020. .pm = sirfsoc_uart_pm,
  1021. .type = sirfsoc_uart_type,
  1022. .release_port = sirfsoc_uart_release_port,
  1023. .request_port = sirfsoc_uart_request_port,
  1024. .config_port = sirfsoc_uart_config_port,
  1025. };
  1026. #ifdef CONFIG_SERIAL_SIRFSOC_CONSOLE
  1027. static int __init
  1028. sirfsoc_uart_console_setup(struct console *co, char *options)
  1029. {
  1030. unsigned int baud = 115200;
  1031. unsigned int bits = 8;
  1032. unsigned int parity = 'n';
  1033. unsigned int flow = 'n';
  1034. struct sirfsoc_uart_port *sirfport;
  1035. struct sirfsoc_register *ureg;
  1036. if (co->index < 0 || co->index >= SIRFSOC_UART_NR)
  1037. co->index = 1;
  1038. sirfport = sirf_ports[co->index];
  1039. if (!sirfport)
  1040. return -ENODEV;
  1041. ureg = &sirfport->uart_reg->uart_reg;
  1042. if (!sirfport->port.mapbase)
  1043. return -ENODEV;
  1044. /* enable usp in mode1 register */
  1045. if (sirfport->uart_reg->uart_type == SIRF_USP_UART)
  1046. wr_regl(&sirfport->port, ureg->sirfsoc_mode1, SIRFSOC_USP_EN |
  1047. SIRFSOC_USP_ENDIAN_CTRL_LSBF);
  1048. if (options)
  1049. uart_parse_options(options, &baud, &parity, &bits, &flow);
  1050. sirfport->port.cons = co;
  1051. /* default console tx/rx transfer using io mode */
  1052. sirfport->rx_dma_chan = NULL;
  1053. sirfport->tx_dma_chan = NULL;
  1054. return uart_set_options(&sirfport->port, co, baud, parity, bits, flow);
  1055. }
  1056. static void sirfsoc_uart_console_putchar(struct uart_port *port, int ch)
  1057. {
  1058. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  1059. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  1060. struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
  1061. while (rd_regl(port, ureg->sirfsoc_tx_fifo_status) &
  1062. ufifo_st->ff_full(port))
  1063. cpu_relax();
  1064. wr_regl(port, ureg->sirfsoc_tx_fifo_data, ch);
  1065. }
  1066. static void sirfsoc_uart_console_write(struct console *co, const char *s,
  1067. unsigned int count)
  1068. {
  1069. struct sirfsoc_uart_port *sirfport = sirf_ports[co->index];
  1070. uart_console_write(&sirfport->port, s, count,
  1071. sirfsoc_uart_console_putchar);
  1072. }
  1073. static struct console sirfsoc_uart_console = {
  1074. .name = SIRFSOC_UART_NAME,
  1075. .device = uart_console_device,
  1076. .flags = CON_PRINTBUFFER,
  1077. .index = -1,
  1078. .write = sirfsoc_uart_console_write,
  1079. .setup = sirfsoc_uart_console_setup,
  1080. .data = &sirfsoc_uart_drv,
  1081. };
  1082. static int __init sirfsoc_uart_console_init(void)
  1083. {
  1084. register_console(&sirfsoc_uart_console);
  1085. return 0;
  1086. }
  1087. console_initcall(sirfsoc_uart_console_init);
  1088. #endif
  1089. static struct uart_driver sirfsoc_uart_drv = {
  1090. .owner = THIS_MODULE,
  1091. .driver_name = SIRFUART_PORT_NAME,
  1092. .nr = SIRFSOC_UART_NR,
  1093. .dev_name = SIRFSOC_UART_NAME,
  1094. .major = SIRFSOC_UART_MAJOR,
  1095. .minor = SIRFSOC_UART_MINOR,
  1096. #ifdef CONFIG_SERIAL_SIRFSOC_CONSOLE
  1097. .cons = &sirfsoc_uart_console,
  1098. #else
  1099. .cons = NULL,
  1100. #endif
  1101. };
  1102. static enum hrtimer_restart
  1103. sirfsoc_uart_rx_dma_hrtimer_callback(struct hrtimer *hrt)
  1104. {
  1105. struct sirfsoc_uart_port *sirfport;
  1106. struct uart_port *port;
  1107. int count, inserted;
  1108. struct dma_tx_state tx_state;
  1109. struct tty_struct *tty;
  1110. struct sirfsoc_register *ureg;
  1111. struct circ_buf *xmit;
  1112. struct sirfsoc_fifo_status *ufifo_st;
  1113. int max_pio_cnt;
  1114. sirfport = container_of(hrt, struct sirfsoc_uart_port, hrt);
  1115. port = &sirfport->port;
  1116. inserted = 0;
  1117. tty = port->state->port.tty;
  1118. ureg = &sirfport->uart_reg->uart_reg;
  1119. xmit = &sirfport->rx_dma_items.xmit;
  1120. ufifo_st = &sirfport->uart_reg->fifo_status;
  1121. dmaengine_tx_status(sirfport->rx_dma_chan,
  1122. sirfport->rx_dma_items.cookie, &tx_state);
  1123. if (SIRFSOC_RX_DMA_BUF_SIZE - tx_state.residue !=
  1124. sirfport->rx_last_pos) {
  1125. xmit->head = SIRFSOC_RX_DMA_BUF_SIZE - tx_state.residue;
  1126. sirfport->rx_last_pos = xmit->head;
  1127. sirfport->pio_fetch_cnt = 0;
  1128. }
  1129. count = CIRC_CNT_TO_END(xmit->head, xmit->tail,
  1130. SIRFSOC_RX_DMA_BUF_SIZE);
  1131. while (count > 0) {
  1132. inserted = tty_insert_flip_string(tty->port,
  1133. (const unsigned char *)&xmit->buf[xmit->tail], count);
  1134. if (!inserted)
  1135. goto next_hrt;
  1136. port->icount.rx += inserted;
  1137. xmit->tail = (xmit->tail + inserted) &
  1138. (SIRFSOC_RX_DMA_BUF_SIZE - 1);
  1139. count = CIRC_CNT_TO_END(xmit->head, xmit->tail,
  1140. SIRFSOC_RX_DMA_BUF_SIZE);
  1141. tty_flip_buffer_push(tty->port);
  1142. }
  1143. /*
  1144. * if RX DMA buffer data have all push into tty buffer, and there is
  1145. * only little data(less than a dma transfer unit) left in rxfifo,
  1146. * fetch it out in pio mode and switch back to dma immediately
  1147. */
  1148. if (!inserted && !count &&
  1149. ((rd_regl(port, ureg->sirfsoc_rx_fifo_status) &
  1150. SIRFUART_RX_FIFO_MASK) > sirfport->pio_fetch_cnt)) {
  1151. dmaengine_pause(sirfport->rx_dma_chan);
  1152. /* switch to pio mode */
  1153. wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
  1154. rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) |
  1155. SIRFUART_IO_MODE);
  1156. /*
  1157. * UART controller SWH_DMA_IO register have CLEAR_RX_ADDR_EN
  1158. * When found changing I/O to DMA mode, it clears
  1159. * two low bits of read point;
  1160. * USP have similar FRADDR_CLR_EN bit in USP_RX_DMA_IO_CTRL.
  1161. * Fetch data out from rxfifo into DMA buffer in PIO mode,
  1162. * while switch back to DMA mode, the data fetched will override
  1163. * by DMA, as hardware have a strange behaviour:
  1164. * after switch back to DMA mode, check rxfifo status it will
  1165. * be the number PIO fetched, so record the fetched data count
  1166. * to avoid the repeated fetch
  1167. */
  1168. max_pio_cnt = 3;
  1169. while (!(rd_regl(port, ureg->sirfsoc_rx_fifo_status) &
  1170. ufifo_st->ff_empty(port)) && max_pio_cnt--) {
  1171. xmit->buf[xmit->head] =
  1172. rd_regl(port, ureg->sirfsoc_rx_fifo_data);
  1173. xmit->head = (xmit->head + 1) &
  1174. (SIRFSOC_RX_DMA_BUF_SIZE - 1);
  1175. sirfport->pio_fetch_cnt++;
  1176. }
  1177. /* switch back to dma mode */
  1178. wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
  1179. rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) &
  1180. ~SIRFUART_IO_MODE);
  1181. dmaengine_resume(sirfport->rx_dma_chan);
  1182. }
  1183. next_hrt:
  1184. hrtimer_forward_now(hrt, ns_to_ktime(sirfport->rx_period_time));
  1185. return HRTIMER_RESTART;
  1186. }
  1187. static const struct of_device_id sirfsoc_uart_ids[] = {
  1188. { .compatible = "sirf,prima2-uart", .data = &sirfsoc_uart,},
  1189. { .compatible = "sirf,atlas7-uart", .data = &sirfsoc_uart},
  1190. { .compatible = "sirf,prima2-usp-uart", .data = &sirfsoc_usp},
  1191. { .compatible = "sirf,atlas7-usp-uart", .data = &sirfsoc_usp},
  1192. {}
  1193. };
  1194. MODULE_DEVICE_TABLE(of, sirfsoc_uart_ids);
  1195. static int sirfsoc_uart_probe(struct platform_device *pdev)
  1196. {
  1197. struct device_node *np = pdev->dev.of_node;
  1198. struct sirfsoc_uart_port *sirfport;
  1199. struct uart_port *port;
  1200. struct resource *res;
  1201. int ret;
  1202. struct dma_slave_config slv_cfg = {
  1203. .src_maxburst = 1,
  1204. };
  1205. struct dma_slave_config tx_slv_cfg = {
  1206. .dst_maxburst = 2,
  1207. };
  1208. const struct of_device_id *match;
  1209. match = of_match_node(sirfsoc_uart_ids, np);
  1210. sirfport = devm_kzalloc(&pdev->dev, sizeof(*sirfport), GFP_KERNEL);
  1211. if (!sirfport) {
  1212. ret = -ENOMEM;
  1213. goto err;
  1214. }
  1215. sirfport->port.line = of_alias_get_id(np, "serial");
  1216. if (sirfport->port.line >= ARRAY_SIZE(sirf_ports)) {
  1217. dev_err(&pdev->dev, "serial%d out of range\n",
  1218. sirfport->port.line);
  1219. return -EINVAL;
  1220. }
  1221. sirf_ports[sirfport->port.line] = sirfport;
  1222. sirfport->port.iotype = UPIO_MEM;
  1223. sirfport->port.flags = UPF_BOOT_AUTOCONF;
  1224. port = &sirfport->port;
  1225. port->dev = &pdev->dev;
  1226. port->private_data = sirfport;
  1227. sirfport->uart_reg = (struct sirfsoc_uart_register *)match->data;
  1228. sirfport->hw_flow_ctrl =
  1229. of_property_read_bool(np, "uart-has-rtscts") ||
  1230. of_property_read_bool(np, "sirf,uart-has-rtscts") /* deprecated */;
  1231. if (of_device_is_compatible(np, "sirf,prima2-uart") ||
  1232. of_device_is_compatible(np, "sirf,atlas7-uart"))
  1233. sirfport->uart_reg->uart_type = SIRF_REAL_UART;
  1234. if (of_device_is_compatible(np, "sirf,prima2-usp-uart") ||
  1235. of_device_is_compatible(np, "sirf,atlas7-usp-uart")) {
  1236. sirfport->uart_reg->uart_type = SIRF_USP_UART;
  1237. if (!sirfport->hw_flow_ctrl)
  1238. goto usp_no_flow_control;
  1239. if (of_find_property(np, "cts-gpios", NULL))
  1240. sirfport->cts_gpio =
  1241. of_get_named_gpio(np, "cts-gpios", 0);
  1242. else
  1243. sirfport->cts_gpio = -1;
  1244. if (of_find_property(np, "rts-gpios", NULL))
  1245. sirfport->rts_gpio =
  1246. of_get_named_gpio(np, "rts-gpios", 0);
  1247. else
  1248. sirfport->rts_gpio = -1;
  1249. if ((!gpio_is_valid(sirfport->cts_gpio) ||
  1250. !gpio_is_valid(sirfport->rts_gpio))) {
  1251. ret = -EINVAL;
  1252. dev_err(&pdev->dev,
  1253. "Usp flow control must have cts and rts gpio");
  1254. goto err;
  1255. }
  1256. ret = devm_gpio_request(&pdev->dev, sirfport->cts_gpio,
  1257. "usp-cts-gpio");
  1258. if (ret) {
  1259. dev_err(&pdev->dev, "Unable request cts gpio");
  1260. goto err;
  1261. }
  1262. gpio_direction_input(sirfport->cts_gpio);
  1263. ret = devm_gpio_request(&pdev->dev, sirfport->rts_gpio,
  1264. "usp-rts-gpio");
  1265. if (ret) {
  1266. dev_err(&pdev->dev, "Unable request rts gpio");
  1267. goto err;
  1268. }
  1269. gpio_direction_output(sirfport->rts_gpio, 1);
  1270. }
  1271. usp_no_flow_control:
  1272. if (of_device_is_compatible(np, "sirf,atlas7-uart") ||
  1273. of_device_is_compatible(np, "sirf,atlas7-usp-uart"))
  1274. sirfport->is_atlas7 = true;
  1275. if (of_property_read_u32(np, "fifosize", &port->fifosize)) {
  1276. dev_err(&pdev->dev,
  1277. "Unable to find fifosize in uart node.\n");
  1278. ret = -EFAULT;
  1279. goto err;
  1280. }
  1281. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1282. if (res == NULL) {
  1283. dev_err(&pdev->dev, "Insufficient resources.\n");
  1284. ret = -EFAULT;
  1285. goto err;
  1286. }
  1287. port->mapbase = res->start;
  1288. port->membase = devm_ioremap(&pdev->dev,
  1289. res->start, resource_size(res));
  1290. if (!port->membase) {
  1291. dev_err(&pdev->dev, "Cannot remap resource.\n");
  1292. ret = -ENOMEM;
  1293. goto err;
  1294. }
  1295. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1296. if (res == NULL) {
  1297. dev_err(&pdev->dev, "Insufficient resources.\n");
  1298. ret = -EFAULT;
  1299. goto err;
  1300. }
  1301. port->irq = res->start;
  1302. sirfport->clk = devm_clk_get(&pdev->dev, NULL);
  1303. if (IS_ERR(sirfport->clk)) {
  1304. ret = PTR_ERR(sirfport->clk);
  1305. goto err;
  1306. }
  1307. port->uartclk = clk_get_rate(sirfport->clk);
  1308. port->ops = &sirfsoc_uart_ops;
  1309. spin_lock_init(&port->lock);
  1310. platform_set_drvdata(pdev, sirfport);
  1311. ret = uart_add_one_port(&sirfsoc_uart_drv, port);
  1312. if (ret != 0) {
  1313. dev_err(&pdev->dev, "Cannot add UART port(%d).\n", pdev->id);
  1314. goto err;
  1315. }
  1316. sirfport->rx_dma_chan = dma_request_slave_channel(port->dev, "rx");
  1317. sirfport->rx_dma_items.xmit.buf =
  1318. dma_alloc_coherent(port->dev, SIRFSOC_RX_DMA_BUF_SIZE,
  1319. &sirfport->rx_dma_items.dma_addr, GFP_KERNEL);
  1320. if (!sirfport->rx_dma_items.xmit.buf) {
  1321. dev_err(port->dev, "Uart alloc bufa failed\n");
  1322. ret = -ENOMEM;
  1323. goto alloc_coherent_err;
  1324. }
  1325. sirfport->rx_dma_items.xmit.head =
  1326. sirfport->rx_dma_items.xmit.tail = 0;
  1327. if (sirfport->rx_dma_chan)
  1328. dmaengine_slave_config(sirfport->rx_dma_chan, &slv_cfg);
  1329. sirfport->tx_dma_chan = dma_request_slave_channel(port->dev, "tx");
  1330. if (sirfport->tx_dma_chan)
  1331. dmaengine_slave_config(sirfport->tx_dma_chan, &tx_slv_cfg);
  1332. if (sirfport->rx_dma_chan) {
  1333. hrtimer_init(&sirfport->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
  1334. sirfport->hrt.function = sirfsoc_uart_rx_dma_hrtimer_callback;
  1335. sirfport->is_hrt_enabled = false;
  1336. }
  1337. return 0;
  1338. alloc_coherent_err:
  1339. dma_free_coherent(port->dev, SIRFSOC_RX_DMA_BUF_SIZE,
  1340. sirfport->rx_dma_items.xmit.buf,
  1341. sirfport->rx_dma_items.dma_addr);
  1342. dma_release_channel(sirfport->rx_dma_chan);
  1343. err:
  1344. return ret;
  1345. }
  1346. static int sirfsoc_uart_remove(struct platform_device *pdev)
  1347. {
  1348. struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev);
  1349. struct uart_port *port = &sirfport->port;
  1350. uart_remove_one_port(&sirfsoc_uart_drv, port);
  1351. if (sirfport->rx_dma_chan) {
  1352. dmaengine_terminate_all(sirfport->rx_dma_chan);
  1353. dma_release_channel(sirfport->rx_dma_chan);
  1354. dma_free_coherent(port->dev, SIRFSOC_RX_DMA_BUF_SIZE,
  1355. sirfport->rx_dma_items.xmit.buf,
  1356. sirfport->rx_dma_items.dma_addr);
  1357. }
  1358. if (sirfport->tx_dma_chan) {
  1359. dmaengine_terminate_all(sirfport->tx_dma_chan);
  1360. dma_release_channel(sirfport->tx_dma_chan);
  1361. }
  1362. return 0;
  1363. }
  1364. #ifdef CONFIG_PM_SLEEP
  1365. static int
  1366. sirfsoc_uart_suspend(struct device *pdev)
  1367. {
  1368. struct sirfsoc_uart_port *sirfport = dev_get_drvdata(pdev);
  1369. struct uart_port *port = &sirfport->port;
  1370. uart_suspend_port(&sirfsoc_uart_drv, port);
  1371. return 0;
  1372. }
  1373. static int sirfsoc_uart_resume(struct device *pdev)
  1374. {
  1375. struct sirfsoc_uart_port *sirfport = dev_get_drvdata(pdev);
  1376. struct uart_port *port = &sirfport->port;
  1377. uart_resume_port(&sirfsoc_uart_drv, port);
  1378. return 0;
  1379. }
  1380. #endif
  1381. static const struct dev_pm_ops sirfsoc_uart_pm_ops = {
  1382. SET_SYSTEM_SLEEP_PM_OPS(sirfsoc_uart_suspend, sirfsoc_uart_resume)
  1383. };
  1384. static struct platform_driver sirfsoc_uart_driver = {
  1385. .probe = sirfsoc_uart_probe,
  1386. .remove = sirfsoc_uart_remove,
  1387. .driver = {
  1388. .name = SIRFUART_PORT_NAME,
  1389. .of_match_table = sirfsoc_uart_ids,
  1390. .pm = &sirfsoc_uart_pm_ops,
  1391. },
  1392. };
  1393. static int __init sirfsoc_uart_init(void)
  1394. {
  1395. int ret = 0;
  1396. ret = uart_register_driver(&sirfsoc_uart_drv);
  1397. if (ret)
  1398. goto out;
  1399. ret = platform_driver_register(&sirfsoc_uart_driver);
  1400. if (ret)
  1401. uart_unregister_driver(&sirfsoc_uart_drv);
  1402. out:
  1403. return ret;
  1404. }
  1405. module_init(sirfsoc_uart_init);
  1406. static void __exit sirfsoc_uart_exit(void)
  1407. {
  1408. platform_driver_unregister(&sirfsoc_uart_driver);
  1409. uart_unregister_driver(&sirfsoc_uart_drv);
  1410. }
  1411. module_exit(sirfsoc_uart_exit);
  1412. MODULE_LICENSE("GPL v2");
  1413. MODULE_AUTHOR("Bin Shi <Bin.Shi@csr.com>, Rong Wang<Rong.Wang@csr.com>");
  1414. MODULE_DESCRIPTION("CSR SiRFprimaII Uart Driver");