rp2.c 23 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Driver for Comtrol RocketPort EXPRESS/INFINITY cards
  4. *
  5. * Copyright (C) 2012 Kevin Cernekee <cernekee@gmail.com>
  6. *
  7. * Inspired by, and loosely based on:
  8. *
  9. * ar933x_uart.c
  10. * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
  11. *
  12. * rocketport_infinity_express-linux-1.20.tar.gz
  13. * Copyright (C) 2004-2011 Comtrol, Inc.
  14. */
  15. #include <linux/bitops.h>
  16. #include <linux/compiler.h>
  17. #include <linux/completion.h>
  18. #include <linux/console.h>
  19. #include <linux/delay.h>
  20. #include <linux/firmware.h>
  21. #include <linux/init.h>
  22. #include <linux/io.h>
  23. #include <linux/ioport.h>
  24. #include <linux/irq.h>
  25. #include <linux/kernel.h>
  26. #include <linux/log2.h>
  27. #include <linux/module.h>
  28. #include <linux/pci.h>
  29. #include <linux/serial.h>
  30. #include <linux/serial_core.h>
  31. #include <linux/slab.h>
  32. #include <linux/sysrq.h>
  33. #include <linux/tty.h>
  34. #include <linux/tty_flip.h>
  35. #include <linux/types.h>
  36. #define DRV_NAME "rp2"
  37. #define RP2_FW_NAME "rp2.fw"
  38. #define RP2_UCODE_BYTES 0x3f
  39. #define PORTS_PER_ASIC 16
  40. #define ALL_PORTS_MASK (BIT(PORTS_PER_ASIC) - 1)
  41. #define UART_CLOCK 44236800
  42. #define DEFAULT_BAUD_DIV (UART_CLOCK / (9600 * 16))
  43. #define FIFO_SIZE 512
  44. /* BAR0 registers */
  45. #define RP2_FPGA_CTL0 0x110
  46. #define RP2_FPGA_CTL1 0x11c
  47. #define RP2_IRQ_MASK 0x1ec
  48. #define RP2_IRQ_MASK_EN_m BIT(0)
  49. #define RP2_IRQ_STATUS 0x1f0
  50. /* BAR1 registers */
  51. #define RP2_ASIC_SPACING 0x1000
  52. #define RP2_ASIC_OFFSET(i) ((i) << ilog2(RP2_ASIC_SPACING))
  53. #define RP2_PORT_BASE 0x000
  54. #define RP2_PORT_SPACING 0x040
  55. #define RP2_UCODE_BASE 0x400
  56. #define RP2_UCODE_SPACING 0x80
  57. #define RP2_CLK_PRESCALER 0xc00
  58. #define RP2_CH_IRQ_STAT 0xc04
  59. #define RP2_CH_IRQ_MASK 0xc08
  60. #define RP2_ASIC_IRQ 0xd00
  61. #define RP2_ASIC_IRQ_EN_m BIT(20)
  62. #define RP2_GLOBAL_CMD 0xd0c
  63. #define RP2_ASIC_CFG 0xd04
  64. /* port registers */
  65. #define RP2_DATA_DWORD 0x000
  66. #define RP2_DATA_BYTE 0x008
  67. #define RP2_DATA_BYTE_ERR_PARITY_m BIT(8)
  68. #define RP2_DATA_BYTE_ERR_OVERRUN_m BIT(9)
  69. #define RP2_DATA_BYTE_ERR_FRAMING_m BIT(10)
  70. #define RP2_DATA_BYTE_BREAK_m BIT(11)
  71. /* This lets uart_insert_char() drop bytes received on a !CREAD port */
  72. #define RP2_DUMMY_READ BIT(16)
  73. #define RP2_DATA_BYTE_EXCEPTION_MASK (RP2_DATA_BYTE_ERR_PARITY_m | \
  74. RP2_DATA_BYTE_ERR_OVERRUN_m | \
  75. RP2_DATA_BYTE_ERR_FRAMING_m | \
  76. RP2_DATA_BYTE_BREAK_m)
  77. #define RP2_RX_FIFO_COUNT 0x00c
  78. #define RP2_TX_FIFO_COUNT 0x00e
  79. #define RP2_CHAN_STAT 0x010
  80. #define RP2_CHAN_STAT_RXDATA_m BIT(0)
  81. #define RP2_CHAN_STAT_DCD_m BIT(3)
  82. #define RP2_CHAN_STAT_DSR_m BIT(4)
  83. #define RP2_CHAN_STAT_CTS_m BIT(5)
  84. #define RP2_CHAN_STAT_RI_m BIT(6)
  85. #define RP2_CHAN_STAT_OVERRUN_m BIT(13)
  86. #define RP2_CHAN_STAT_DSR_CHANGED_m BIT(16)
  87. #define RP2_CHAN_STAT_CTS_CHANGED_m BIT(17)
  88. #define RP2_CHAN_STAT_CD_CHANGED_m BIT(18)
  89. #define RP2_CHAN_STAT_RI_CHANGED_m BIT(22)
  90. #define RP2_CHAN_STAT_TXEMPTY_m BIT(25)
  91. #define RP2_CHAN_STAT_MS_CHANGED_MASK (RP2_CHAN_STAT_DSR_CHANGED_m | \
  92. RP2_CHAN_STAT_CTS_CHANGED_m | \
  93. RP2_CHAN_STAT_CD_CHANGED_m | \
  94. RP2_CHAN_STAT_RI_CHANGED_m)
  95. #define RP2_TXRX_CTL 0x014
  96. #define RP2_TXRX_CTL_MSRIRQ_m BIT(0)
  97. #define RP2_TXRX_CTL_RXIRQ_m BIT(2)
  98. #define RP2_TXRX_CTL_RX_TRIG_s 3
  99. #define RP2_TXRX_CTL_RX_TRIG_m (0x3 << RP2_TXRX_CTL_RX_TRIG_s)
  100. #define RP2_TXRX_CTL_RX_TRIG_1 (0x1 << RP2_TXRX_CTL_RX_TRIG_s)
  101. #define RP2_TXRX_CTL_RX_TRIG_256 (0x2 << RP2_TXRX_CTL_RX_TRIG_s)
  102. #define RP2_TXRX_CTL_RX_TRIG_448 (0x3 << RP2_TXRX_CTL_RX_TRIG_s)
  103. #define RP2_TXRX_CTL_RX_EN_m BIT(5)
  104. #define RP2_TXRX_CTL_RTSFLOW_m BIT(6)
  105. #define RP2_TXRX_CTL_DTRFLOW_m BIT(7)
  106. #define RP2_TXRX_CTL_TX_TRIG_s 16
  107. #define RP2_TXRX_CTL_TX_TRIG_m (0x3 << RP2_TXRX_CTL_RX_TRIG_s)
  108. #define RP2_TXRX_CTL_DSRFLOW_m BIT(18)
  109. #define RP2_TXRX_CTL_TXIRQ_m BIT(19)
  110. #define RP2_TXRX_CTL_CTSFLOW_m BIT(23)
  111. #define RP2_TXRX_CTL_TX_EN_m BIT(24)
  112. #define RP2_TXRX_CTL_RTS_m BIT(25)
  113. #define RP2_TXRX_CTL_DTR_m BIT(26)
  114. #define RP2_TXRX_CTL_LOOP_m BIT(27)
  115. #define RP2_TXRX_CTL_BREAK_m BIT(28)
  116. #define RP2_TXRX_CTL_CMSPAR_m BIT(29)
  117. #define RP2_TXRX_CTL_nPARODD_m BIT(30)
  118. #define RP2_TXRX_CTL_PARENB_m BIT(31)
  119. #define RP2_UART_CTL 0x018
  120. #define RP2_UART_CTL_MODE_s 0
  121. #define RP2_UART_CTL_MODE_m (0x7 << RP2_UART_CTL_MODE_s)
  122. #define RP2_UART_CTL_MODE_rs232 (0x1 << RP2_UART_CTL_MODE_s)
  123. #define RP2_UART_CTL_FLUSH_RX_m BIT(3)
  124. #define RP2_UART_CTL_FLUSH_TX_m BIT(4)
  125. #define RP2_UART_CTL_RESET_CH_m BIT(5)
  126. #define RP2_UART_CTL_XMIT_EN_m BIT(6)
  127. #define RP2_UART_CTL_DATABITS_s 8
  128. #define RP2_UART_CTL_DATABITS_m (0x3 << RP2_UART_CTL_DATABITS_s)
  129. #define RP2_UART_CTL_DATABITS_8 (0x3 << RP2_UART_CTL_DATABITS_s)
  130. #define RP2_UART_CTL_DATABITS_7 (0x2 << RP2_UART_CTL_DATABITS_s)
  131. #define RP2_UART_CTL_DATABITS_6 (0x1 << RP2_UART_CTL_DATABITS_s)
  132. #define RP2_UART_CTL_DATABITS_5 (0x0 << RP2_UART_CTL_DATABITS_s)
  133. #define RP2_UART_CTL_STOPBITS_m BIT(10)
  134. #define RP2_BAUD 0x01c
  135. /* ucode registers */
  136. #define RP2_TX_SWFLOW 0x02
  137. #define RP2_TX_SWFLOW_ena 0x81
  138. #define RP2_TX_SWFLOW_dis 0x9d
  139. #define RP2_RX_SWFLOW 0x0c
  140. #define RP2_RX_SWFLOW_ena 0x81
  141. #define RP2_RX_SWFLOW_dis 0x8d
  142. #define RP2_RX_FIFO 0x37
  143. #define RP2_RX_FIFO_ena 0x08
  144. #define RP2_RX_FIFO_dis 0x81
  145. static struct uart_driver rp2_uart_driver = {
  146. .owner = THIS_MODULE,
  147. .driver_name = DRV_NAME,
  148. .dev_name = "ttyRP",
  149. .nr = CONFIG_SERIAL_RP2_NR_UARTS,
  150. };
  151. struct rp2_card;
  152. struct rp2_uart_port {
  153. struct uart_port port;
  154. int idx;
  155. int ignore_rx;
  156. struct rp2_card *card;
  157. void __iomem *asic_base;
  158. void __iomem *base;
  159. void __iomem *ucode;
  160. };
  161. struct rp2_card {
  162. struct pci_dev *pdev;
  163. struct rp2_uart_port *ports;
  164. int n_ports;
  165. int initialized_ports;
  166. int minor_start;
  167. int smpte;
  168. void __iomem *bar0;
  169. void __iomem *bar1;
  170. spinlock_t card_lock;
  171. };
  172. #define RP_ID(prod) PCI_VDEVICE(RP, (prod))
  173. #define RP_CAP(ports, smpte) (((ports) << 8) | ((smpte) << 0))
  174. static inline void rp2_decode_cap(const struct pci_device_id *id,
  175. int *ports, int *smpte)
  176. {
  177. *ports = id->driver_data >> 8;
  178. *smpte = id->driver_data & 0xff;
  179. }
  180. static DEFINE_SPINLOCK(rp2_minor_lock);
  181. static int rp2_minor_next;
  182. static int rp2_alloc_ports(int n_ports)
  183. {
  184. int ret = -ENOSPC;
  185. spin_lock(&rp2_minor_lock);
  186. if (rp2_minor_next + n_ports <= CONFIG_SERIAL_RP2_NR_UARTS) {
  187. /* sorry, no support for hot unplugging individual cards */
  188. ret = rp2_minor_next;
  189. rp2_minor_next += n_ports;
  190. }
  191. spin_unlock(&rp2_minor_lock);
  192. return ret;
  193. }
  194. static inline struct rp2_uart_port *port_to_up(struct uart_port *port)
  195. {
  196. return container_of(port, struct rp2_uart_port, port);
  197. }
  198. static void rp2_rmw(struct rp2_uart_port *up, int reg,
  199. u32 clr_bits, u32 set_bits)
  200. {
  201. u32 tmp = readl(up->base + reg);
  202. tmp &= ~clr_bits;
  203. tmp |= set_bits;
  204. writel(tmp, up->base + reg);
  205. }
  206. static void rp2_rmw_clr(struct rp2_uart_port *up, int reg, u32 val)
  207. {
  208. rp2_rmw(up, reg, val, 0);
  209. }
  210. static void rp2_rmw_set(struct rp2_uart_port *up, int reg, u32 val)
  211. {
  212. rp2_rmw(up, reg, 0, val);
  213. }
  214. static void rp2_mask_ch_irq(struct rp2_uart_port *up, int ch_num,
  215. int is_enabled)
  216. {
  217. unsigned long flags, irq_mask;
  218. spin_lock_irqsave(&up->card->card_lock, flags);
  219. irq_mask = readl(up->asic_base + RP2_CH_IRQ_MASK);
  220. if (is_enabled)
  221. irq_mask &= ~BIT(ch_num);
  222. else
  223. irq_mask |= BIT(ch_num);
  224. writel(irq_mask, up->asic_base + RP2_CH_IRQ_MASK);
  225. spin_unlock_irqrestore(&up->card->card_lock, flags);
  226. }
  227. static unsigned int rp2_uart_tx_empty(struct uart_port *port)
  228. {
  229. struct rp2_uart_port *up = port_to_up(port);
  230. unsigned long tx_fifo_bytes, flags;
  231. /*
  232. * This should probably check the transmitter, not the FIFO.
  233. * But the TXEMPTY bit doesn't seem to work unless the TX IRQ is
  234. * enabled.
  235. */
  236. spin_lock_irqsave(&up->port.lock, flags);
  237. tx_fifo_bytes = readw(up->base + RP2_TX_FIFO_COUNT);
  238. spin_unlock_irqrestore(&up->port.lock, flags);
  239. return tx_fifo_bytes ? 0 : TIOCSER_TEMT;
  240. }
  241. static unsigned int rp2_uart_get_mctrl(struct uart_port *port)
  242. {
  243. struct rp2_uart_port *up = port_to_up(port);
  244. u32 status;
  245. status = readl(up->base + RP2_CHAN_STAT);
  246. return ((status & RP2_CHAN_STAT_DCD_m) ? TIOCM_CAR : 0) |
  247. ((status & RP2_CHAN_STAT_DSR_m) ? TIOCM_DSR : 0) |
  248. ((status & RP2_CHAN_STAT_CTS_m) ? TIOCM_CTS : 0) |
  249. ((status & RP2_CHAN_STAT_RI_m) ? TIOCM_RI : 0);
  250. }
  251. static void rp2_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
  252. {
  253. rp2_rmw(port_to_up(port), RP2_TXRX_CTL,
  254. RP2_TXRX_CTL_DTR_m | RP2_TXRX_CTL_RTS_m | RP2_TXRX_CTL_LOOP_m,
  255. ((mctrl & TIOCM_DTR) ? RP2_TXRX_CTL_DTR_m : 0) |
  256. ((mctrl & TIOCM_RTS) ? RP2_TXRX_CTL_RTS_m : 0) |
  257. ((mctrl & TIOCM_LOOP) ? RP2_TXRX_CTL_LOOP_m : 0));
  258. }
  259. static void rp2_uart_start_tx(struct uart_port *port)
  260. {
  261. rp2_rmw_set(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_TXIRQ_m);
  262. }
  263. static void rp2_uart_stop_tx(struct uart_port *port)
  264. {
  265. rp2_rmw_clr(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_TXIRQ_m);
  266. }
  267. static void rp2_uart_stop_rx(struct uart_port *port)
  268. {
  269. rp2_rmw_clr(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_RXIRQ_m);
  270. }
  271. static void rp2_uart_break_ctl(struct uart_port *port, int break_state)
  272. {
  273. unsigned long flags;
  274. spin_lock_irqsave(&port->lock, flags);
  275. rp2_rmw(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_BREAK_m,
  276. break_state ? RP2_TXRX_CTL_BREAK_m : 0);
  277. spin_unlock_irqrestore(&port->lock, flags);
  278. }
  279. static void rp2_uart_enable_ms(struct uart_port *port)
  280. {
  281. rp2_rmw_set(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_MSRIRQ_m);
  282. }
  283. static void __rp2_uart_set_termios(struct rp2_uart_port *up,
  284. unsigned long cfl,
  285. unsigned long ifl,
  286. unsigned int baud_div)
  287. {
  288. /* baud rate divisor (calculated elsewhere). 0 = divide-by-1 */
  289. writew(baud_div - 1, up->base + RP2_BAUD);
  290. /* data bits and stop bits */
  291. rp2_rmw(up, RP2_UART_CTL,
  292. RP2_UART_CTL_STOPBITS_m | RP2_UART_CTL_DATABITS_m,
  293. ((cfl & CSTOPB) ? RP2_UART_CTL_STOPBITS_m : 0) |
  294. (((cfl & CSIZE) == CS8) ? RP2_UART_CTL_DATABITS_8 : 0) |
  295. (((cfl & CSIZE) == CS7) ? RP2_UART_CTL_DATABITS_7 : 0) |
  296. (((cfl & CSIZE) == CS6) ? RP2_UART_CTL_DATABITS_6 : 0) |
  297. (((cfl & CSIZE) == CS5) ? RP2_UART_CTL_DATABITS_5 : 0));
  298. /* parity and hardware flow control */
  299. rp2_rmw(up, RP2_TXRX_CTL,
  300. RP2_TXRX_CTL_PARENB_m | RP2_TXRX_CTL_nPARODD_m |
  301. RP2_TXRX_CTL_CMSPAR_m | RP2_TXRX_CTL_DTRFLOW_m |
  302. RP2_TXRX_CTL_DSRFLOW_m | RP2_TXRX_CTL_RTSFLOW_m |
  303. RP2_TXRX_CTL_CTSFLOW_m,
  304. ((cfl & PARENB) ? RP2_TXRX_CTL_PARENB_m : 0) |
  305. ((cfl & PARODD) ? 0 : RP2_TXRX_CTL_nPARODD_m) |
  306. ((cfl & CMSPAR) ? RP2_TXRX_CTL_CMSPAR_m : 0) |
  307. ((cfl & CRTSCTS) ? (RP2_TXRX_CTL_RTSFLOW_m |
  308. RP2_TXRX_CTL_CTSFLOW_m) : 0));
  309. /* XON/XOFF software flow control */
  310. writeb((ifl & IXON) ? RP2_TX_SWFLOW_ena : RP2_TX_SWFLOW_dis,
  311. up->ucode + RP2_TX_SWFLOW);
  312. writeb((ifl & IXOFF) ? RP2_RX_SWFLOW_ena : RP2_RX_SWFLOW_dis,
  313. up->ucode + RP2_RX_SWFLOW);
  314. }
  315. static void rp2_uart_set_termios(struct uart_port *port,
  316. struct ktermios *new,
  317. struct ktermios *old)
  318. {
  319. struct rp2_uart_port *up = port_to_up(port);
  320. unsigned long flags;
  321. unsigned int baud, baud_div;
  322. baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
  323. baud_div = uart_get_divisor(port, baud);
  324. if (tty_termios_baud_rate(new))
  325. tty_termios_encode_baud_rate(new, baud, baud);
  326. spin_lock_irqsave(&port->lock, flags);
  327. /* ignore all characters if CREAD is not set */
  328. port->ignore_status_mask = (new->c_cflag & CREAD) ? 0 : RP2_DUMMY_READ;
  329. __rp2_uart_set_termios(up, new->c_cflag, new->c_iflag, baud_div);
  330. uart_update_timeout(port, new->c_cflag, baud);
  331. spin_unlock_irqrestore(&port->lock, flags);
  332. }
  333. static void rp2_rx_chars(struct rp2_uart_port *up)
  334. {
  335. u16 bytes = readw(up->base + RP2_RX_FIFO_COUNT);
  336. struct tty_port *port = &up->port.state->port;
  337. for (; bytes != 0; bytes--) {
  338. u32 byte = readw(up->base + RP2_DATA_BYTE) | RP2_DUMMY_READ;
  339. char ch = byte & 0xff;
  340. if (likely(!(byte & RP2_DATA_BYTE_EXCEPTION_MASK))) {
  341. if (!uart_handle_sysrq_char(&up->port, ch))
  342. uart_insert_char(&up->port, byte, 0, ch,
  343. TTY_NORMAL);
  344. } else {
  345. char flag = TTY_NORMAL;
  346. if (byte & RP2_DATA_BYTE_BREAK_m)
  347. flag = TTY_BREAK;
  348. else if (byte & RP2_DATA_BYTE_ERR_FRAMING_m)
  349. flag = TTY_FRAME;
  350. else if (byte & RP2_DATA_BYTE_ERR_PARITY_m)
  351. flag = TTY_PARITY;
  352. uart_insert_char(&up->port, byte,
  353. RP2_DATA_BYTE_ERR_OVERRUN_m, ch, flag);
  354. }
  355. up->port.icount.rx++;
  356. }
  357. spin_unlock(&up->port.lock);
  358. tty_flip_buffer_push(port);
  359. spin_lock(&up->port.lock);
  360. }
  361. static void rp2_tx_chars(struct rp2_uart_port *up)
  362. {
  363. u16 max_tx = FIFO_SIZE - readw(up->base + RP2_TX_FIFO_COUNT);
  364. struct circ_buf *xmit = &up->port.state->xmit;
  365. if (uart_tx_stopped(&up->port)) {
  366. rp2_uart_stop_tx(&up->port);
  367. return;
  368. }
  369. for (; max_tx != 0; max_tx--) {
  370. if (up->port.x_char) {
  371. writeb(up->port.x_char, up->base + RP2_DATA_BYTE);
  372. up->port.x_char = 0;
  373. up->port.icount.tx++;
  374. continue;
  375. }
  376. if (uart_circ_empty(xmit)) {
  377. rp2_uart_stop_tx(&up->port);
  378. break;
  379. }
  380. writeb(xmit->buf[xmit->tail], up->base + RP2_DATA_BYTE);
  381. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  382. up->port.icount.tx++;
  383. }
  384. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  385. uart_write_wakeup(&up->port);
  386. }
  387. static void rp2_ch_interrupt(struct rp2_uart_port *up)
  388. {
  389. u32 status;
  390. spin_lock(&up->port.lock);
  391. /*
  392. * The IRQ status bits are clear-on-write. Other status bits in
  393. * this register aren't, so it's harmless to write to them.
  394. */
  395. status = readl(up->base + RP2_CHAN_STAT);
  396. writel(status, up->base + RP2_CHAN_STAT);
  397. if (status & RP2_CHAN_STAT_RXDATA_m)
  398. rp2_rx_chars(up);
  399. if (status & RP2_CHAN_STAT_TXEMPTY_m)
  400. rp2_tx_chars(up);
  401. if (status & RP2_CHAN_STAT_MS_CHANGED_MASK)
  402. wake_up_interruptible(&up->port.state->port.delta_msr_wait);
  403. spin_unlock(&up->port.lock);
  404. }
  405. static int rp2_asic_interrupt(struct rp2_card *card, unsigned int asic_id)
  406. {
  407. void __iomem *base = card->bar1 + RP2_ASIC_OFFSET(asic_id);
  408. int ch, handled = 0;
  409. unsigned long status = readl(base + RP2_CH_IRQ_STAT) &
  410. ~readl(base + RP2_CH_IRQ_MASK);
  411. for_each_set_bit(ch, &status, PORTS_PER_ASIC) {
  412. rp2_ch_interrupt(&card->ports[ch]);
  413. handled++;
  414. }
  415. return handled;
  416. }
  417. static irqreturn_t rp2_uart_interrupt(int irq, void *dev_id)
  418. {
  419. struct rp2_card *card = dev_id;
  420. int handled;
  421. handled = rp2_asic_interrupt(card, 0);
  422. if (card->n_ports >= PORTS_PER_ASIC)
  423. handled += rp2_asic_interrupt(card, 1);
  424. return handled ? IRQ_HANDLED : IRQ_NONE;
  425. }
  426. static inline void rp2_flush_fifos(struct rp2_uart_port *up)
  427. {
  428. rp2_rmw_set(up, RP2_UART_CTL,
  429. RP2_UART_CTL_FLUSH_RX_m | RP2_UART_CTL_FLUSH_TX_m);
  430. readl(up->base + RP2_UART_CTL);
  431. udelay(10);
  432. rp2_rmw_clr(up, RP2_UART_CTL,
  433. RP2_UART_CTL_FLUSH_RX_m | RP2_UART_CTL_FLUSH_TX_m);
  434. }
  435. static int rp2_uart_startup(struct uart_port *port)
  436. {
  437. struct rp2_uart_port *up = port_to_up(port);
  438. rp2_flush_fifos(up);
  439. rp2_rmw(up, RP2_TXRX_CTL, RP2_TXRX_CTL_MSRIRQ_m, RP2_TXRX_CTL_RXIRQ_m);
  440. rp2_rmw(up, RP2_TXRX_CTL, RP2_TXRX_CTL_RX_TRIG_m,
  441. RP2_TXRX_CTL_RX_TRIG_1);
  442. rp2_rmw(up, RP2_CHAN_STAT, 0, 0);
  443. rp2_mask_ch_irq(up, up->idx, 1);
  444. return 0;
  445. }
  446. static void rp2_uart_shutdown(struct uart_port *port)
  447. {
  448. struct rp2_uart_port *up = port_to_up(port);
  449. unsigned long flags;
  450. rp2_uart_break_ctl(port, 0);
  451. spin_lock_irqsave(&port->lock, flags);
  452. rp2_mask_ch_irq(up, up->idx, 0);
  453. rp2_rmw(up, RP2_CHAN_STAT, 0, 0);
  454. spin_unlock_irqrestore(&port->lock, flags);
  455. }
  456. static const char *rp2_uart_type(struct uart_port *port)
  457. {
  458. return (port->type == PORT_RP2) ? "RocketPort 2 UART" : NULL;
  459. }
  460. static void rp2_uart_release_port(struct uart_port *port)
  461. {
  462. /* Nothing to release ... */
  463. }
  464. static int rp2_uart_request_port(struct uart_port *port)
  465. {
  466. /* UARTs always present */
  467. return 0;
  468. }
  469. static void rp2_uart_config_port(struct uart_port *port, int flags)
  470. {
  471. if (flags & UART_CONFIG_TYPE)
  472. port->type = PORT_RP2;
  473. }
  474. static int rp2_uart_verify_port(struct uart_port *port,
  475. struct serial_struct *ser)
  476. {
  477. if (ser->type != PORT_UNKNOWN && ser->type != PORT_RP2)
  478. return -EINVAL;
  479. return 0;
  480. }
  481. static const struct uart_ops rp2_uart_ops = {
  482. .tx_empty = rp2_uart_tx_empty,
  483. .set_mctrl = rp2_uart_set_mctrl,
  484. .get_mctrl = rp2_uart_get_mctrl,
  485. .stop_tx = rp2_uart_stop_tx,
  486. .start_tx = rp2_uart_start_tx,
  487. .stop_rx = rp2_uart_stop_rx,
  488. .enable_ms = rp2_uart_enable_ms,
  489. .break_ctl = rp2_uart_break_ctl,
  490. .startup = rp2_uart_startup,
  491. .shutdown = rp2_uart_shutdown,
  492. .set_termios = rp2_uart_set_termios,
  493. .type = rp2_uart_type,
  494. .release_port = rp2_uart_release_port,
  495. .request_port = rp2_uart_request_port,
  496. .config_port = rp2_uart_config_port,
  497. .verify_port = rp2_uart_verify_port,
  498. };
  499. static void rp2_reset_asic(struct rp2_card *card, unsigned int asic_id)
  500. {
  501. void __iomem *base = card->bar1 + RP2_ASIC_OFFSET(asic_id);
  502. u32 clk_cfg;
  503. writew(1, base + RP2_GLOBAL_CMD);
  504. readw(base + RP2_GLOBAL_CMD);
  505. msleep(100);
  506. writel(0, base + RP2_CLK_PRESCALER);
  507. /* TDM clock configuration */
  508. clk_cfg = readw(base + RP2_ASIC_CFG);
  509. clk_cfg = (clk_cfg & ~BIT(8)) | BIT(9);
  510. writew(clk_cfg, base + RP2_ASIC_CFG);
  511. /* IRQ routing */
  512. writel(ALL_PORTS_MASK, base + RP2_CH_IRQ_MASK);
  513. writel(RP2_ASIC_IRQ_EN_m, base + RP2_ASIC_IRQ);
  514. }
  515. static void rp2_init_card(struct rp2_card *card)
  516. {
  517. writel(4, card->bar0 + RP2_FPGA_CTL0);
  518. writel(0, card->bar0 + RP2_FPGA_CTL1);
  519. rp2_reset_asic(card, 0);
  520. if (card->n_ports >= PORTS_PER_ASIC)
  521. rp2_reset_asic(card, 1);
  522. writel(RP2_IRQ_MASK_EN_m, card->bar0 + RP2_IRQ_MASK);
  523. }
  524. static void rp2_init_port(struct rp2_uart_port *up, const struct firmware *fw)
  525. {
  526. int i;
  527. writel(RP2_UART_CTL_RESET_CH_m, up->base + RP2_UART_CTL);
  528. readl(up->base + RP2_UART_CTL);
  529. udelay(1);
  530. writel(0, up->base + RP2_TXRX_CTL);
  531. writel(0, up->base + RP2_UART_CTL);
  532. readl(up->base + RP2_UART_CTL);
  533. udelay(1);
  534. rp2_flush_fifos(up);
  535. for (i = 0; i < min_t(int, fw->size, RP2_UCODE_BYTES); i++)
  536. writeb(fw->data[i], up->ucode + i);
  537. __rp2_uart_set_termios(up, CS8 | CREAD | CLOCAL, 0, DEFAULT_BAUD_DIV);
  538. rp2_uart_set_mctrl(&up->port, 0);
  539. writeb(RP2_RX_FIFO_ena, up->ucode + RP2_RX_FIFO);
  540. rp2_rmw(up, RP2_UART_CTL, RP2_UART_CTL_MODE_m,
  541. RP2_UART_CTL_XMIT_EN_m | RP2_UART_CTL_MODE_rs232);
  542. rp2_rmw_set(up, RP2_TXRX_CTL,
  543. RP2_TXRX_CTL_TX_EN_m | RP2_TXRX_CTL_RX_EN_m);
  544. }
  545. static void rp2_remove_ports(struct rp2_card *card)
  546. {
  547. int i;
  548. for (i = 0; i < card->initialized_ports; i++)
  549. uart_remove_one_port(&rp2_uart_driver, &card->ports[i].port);
  550. card->initialized_ports = 0;
  551. }
  552. static int rp2_load_firmware(struct rp2_card *card, const struct firmware *fw)
  553. {
  554. resource_size_t phys_base;
  555. int i, rc = 0;
  556. phys_base = pci_resource_start(card->pdev, 1);
  557. for (i = 0; i < card->n_ports; i++) {
  558. struct rp2_uart_port *rp = &card->ports[i];
  559. struct uart_port *p;
  560. int j = (unsigned)i % PORTS_PER_ASIC;
  561. rp->asic_base = card->bar1;
  562. rp->base = card->bar1 + RP2_PORT_BASE + j*RP2_PORT_SPACING;
  563. rp->ucode = card->bar1 + RP2_UCODE_BASE + j*RP2_UCODE_SPACING;
  564. rp->card = card;
  565. rp->idx = j;
  566. p = &rp->port;
  567. p->line = card->minor_start + i;
  568. p->dev = &card->pdev->dev;
  569. p->type = PORT_RP2;
  570. p->iotype = UPIO_MEM32;
  571. p->uartclk = UART_CLOCK;
  572. p->regshift = 2;
  573. p->fifosize = FIFO_SIZE;
  574. p->ops = &rp2_uart_ops;
  575. p->irq = card->pdev->irq;
  576. p->membase = rp->base;
  577. p->mapbase = phys_base + RP2_PORT_BASE + j*RP2_PORT_SPACING;
  578. if (i >= PORTS_PER_ASIC) {
  579. rp->asic_base += RP2_ASIC_SPACING;
  580. rp->base += RP2_ASIC_SPACING;
  581. rp->ucode += RP2_ASIC_SPACING;
  582. p->mapbase += RP2_ASIC_SPACING;
  583. }
  584. rp2_init_port(rp, fw);
  585. rc = uart_add_one_port(&rp2_uart_driver, p);
  586. if (rc) {
  587. dev_err(&card->pdev->dev,
  588. "error registering port %d: %d\n", i, rc);
  589. rp2_remove_ports(card);
  590. break;
  591. }
  592. card->initialized_ports++;
  593. }
  594. return rc;
  595. }
  596. static int rp2_probe(struct pci_dev *pdev,
  597. const struct pci_device_id *id)
  598. {
  599. const struct firmware *fw;
  600. struct rp2_card *card;
  601. struct rp2_uart_port *ports;
  602. void __iomem * const *bars;
  603. int rc;
  604. card = devm_kzalloc(&pdev->dev, sizeof(*card), GFP_KERNEL);
  605. if (!card)
  606. return -ENOMEM;
  607. pci_set_drvdata(pdev, card);
  608. spin_lock_init(&card->card_lock);
  609. rc = pcim_enable_device(pdev);
  610. if (rc)
  611. return rc;
  612. rc = pcim_iomap_regions_request_all(pdev, 0x03, DRV_NAME);
  613. if (rc)
  614. return rc;
  615. bars = pcim_iomap_table(pdev);
  616. card->bar0 = bars[0];
  617. card->bar1 = bars[1];
  618. card->pdev = pdev;
  619. rp2_decode_cap(id, &card->n_ports, &card->smpte);
  620. dev_info(&pdev->dev, "found new card with %d ports\n", card->n_ports);
  621. card->minor_start = rp2_alloc_ports(card->n_ports);
  622. if (card->minor_start < 0) {
  623. dev_err(&pdev->dev,
  624. "too many ports (try increasing CONFIG_SERIAL_RP2_NR_UARTS)\n");
  625. return -EINVAL;
  626. }
  627. rp2_init_card(card);
  628. ports = devm_kcalloc(&pdev->dev, card->n_ports, sizeof(*ports),
  629. GFP_KERNEL);
  630. if (!ports)
  631. return -ENOMEM;
  632. card->ports = ports;
  633. rc = request_firmware(&fw, RP2_FW_NAME, &pdev->dev);
  634. if (rc < 0) {
  635. dev_err(&pdev->dev, "cannot find '%s' firmware image\n",
  636. RP2_FW_NAME);
  637. return rc;
  638. }
  639. rc = rp2_load_firmware(card, fw);
  640. release_firmware(fw);
  641. if (rc < 0)
  642. return rc;
  643. rc = devm_request_irq(&pdev->dev, pdev->irq, rp2_uart_interrupt,
  644. IRQF_SHARED, DRV_NAME, card);
  645. if (rc)
  646. return rc;
  647. return 0;
  648. }
  649. static void rp2_remove(struct pci_dev *pdev)
  650. {
  651. struct rp2_card *card = pci_get_drvdata(pdev);
  652. rp2_remove_ports(card);
  653. }
  654. static const struct pci_device_id rp2_pci_tbl[] = {
  655. /* RocketPort INFINITY cards */
  656. { RP_ID(0x0040), RP_CAP(8, 0) }, /* INF Octa, RJ45, selectable */
  657. { RP_ID(0x0041), RP_CAP(32, 0) }, /* INF 32, ext interface */
  658. { RP_ID(0x0042), RP_CAP(8, 0) }, /* INF Octa, ext interface */
  659. { RP_ID(0x0043), RP_CAP(16, 0) }, /* INF 16, ext interface */
  660. { RP_ID(0x0044), RP_CAP(4, 0) }, /* INF Quad, DB, selectable */
  661. { RP_ID(0x0045), RP_CAP(8, 0) }, /* INF Octa, DB, selectable */
  662. { RP_ID(0x0046), RP_CAP(4, 0) }, /* INF Quad, ext interface */
  663. { RP_ID(0x0047), RP_CAP(4, 0) }, /* INF Quad, RJ45 */
  664. { RP_ID(0x004a), RP_CAP(4, 0) }, /* INF Plus, Quad */
  665. { RP_ID(0x004b), RP_CAP(8, 0) }, /* INF Plus, Octa */
  666. { RP_ID(0x004c), RP_CAP(8, 0) }, /* INF III, Octa */
  667. { RP_ID(0x004d), RP_CAP(4, 0) }, /* INF III, Quad */
  668. { RP_ID(0x004e), RP_CAP(2, 0) }, /* INF Plus, 2, RS232 */
  669. { RP_ID(0x004f), RP_CAP(2, 1) }, /* INF Plus, 2, SMPTE */
  670. { RP_ID(0x0050), RP_CAP(4, 0) }, /* INF Plus, Quad, RJ45 */
  671. { RP_ID(0x0051), RP_CAP(8, 0) }, /* INF Plus, Octa, RJ45 */
  672. { RP_ID(0x0052), RP_CAP(8, 1) }, /* INF Octa, SMPTE */
  673. /* RocketPort EXPRESS cards */
  674. { RP_ID(0x0060), RP_CAP(8, 0) }, /* EXP Octa, RJ45, selectable */
  675. { RP_ID(0x0061), RP_CAP(32, 0) }, /* EXP 32, ext interface */
  676. { RP_ID(0x0062), RP_CAP(8, 0) }, /* EXP Octa, ext interface */
  677. { RP_ID(0x0063), RP_CAP(16, 0) }, /* EXP 16, ext interface */
  678. { RP_ID(0x0064), RP_CAP(4, 0) }, /* EXP Quad, DB, selectable */
  679. { RP_ID(0x0065), RP_CAP(8, 0) }, /* EXP Octa, DB, selectable */
  680. { RP_ID(0x0066), RP_CAP(4, 0) }, /* EXP Quad, ext interface */
  681. { RP_ID(0x0067), RP_CAP(4, 0) }, /* EXP Quad, RJ45 */
  682. { RP_ID(0x0068), RP_CAP(8, 0) }, /* EXP Octa, RJ11 */
  683. { RP_ID(0x0072), RP_CAP(8, 1) }, /* EXP Octa, SMPTE */
  684. { }
  685. };
  686. MODULE_DEVICE_TABLE(pci, rp2_pci_tbl);
  687. static struct pci_driver rp2_pci_driver = {
  688. .name = DRV_NAME,
  689. .id_table = rp2_pci_tbl,
  690. .probe = rp2_probe,
  691. .remove = rp2_remove,
  692. };
  693. static int __init rp2_uart_init(void)
  694. {
  695. int rc;
  696. rc = uart_register_driver(&rp2_uart_driver);
  697. if (rc)
  698. return rc;
  699. rc = pci_register_driver(&rp2_pci_driver);
  700. if (rc) {
  701. uart_unregister_driver(&rp2_uart_driver);
  702. return rc;
  703. }
  704. return 0;
  705. }
  706. static void __exit rp2_uart_exit(void)
  707. {
  708. pci_unregister_driver(&rp2_pci_driver);
  709. uart_unregister_driver(&rp2_uart_driver);
  710. }
  711. module_init(rp2_uart_init);
  712. module_exit(rp2_uart_exit);
  713. MODULE_DESCRIPTION("Comtrol RocketPort EXPRESS/INFINITY driver");
  714. MODULE_AUTHOR("Kevin Cernekee <cernekee@gmail.com>");
  715. MODULE_LICENSE("GPL v2");
  716. MODULE_FIRMWARE(RP2_FW_NAME);