omap-serial.c 50 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Driver for OMAP-UART controller.
  4. * Based on drivers/serial/8250.c
  5. *
  6. * Copyright (C) 2010 Texas Instruments.
  7. *
  8. * Authors:
  9. * Govindraj R <govindraj.raja@ti.com>
  10. * Thara Gopinath <thara@ti.com>
  11. *
  12. * Note: This driver is made separate from 8250 driver as we cannot
  13. * over load 8250 driver with omap platform specific configuration for
  14. * features like DMA, it makes easier to implement features like DMA and
  15. * hardware flow control and software flow control configuration with
  16. * this driver as required for the omap-platform.
  17. */
  18. #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  19. #define SUPPORT_SYSRQ
  20. #endif
  21. #include <linux/module.h>
  22. #include <linux/init.h>
  23. #include <linux/console.h>
  24. #include <linux/serial_reg.h>
  25. #include <linux/delay.h>
  26. #include <linux/slab.h>
  27. #include <linux/tty.h>
  28. #include <linux/tty_flip.h>
  29. #include <linux/platform_device.h>
  30. #include <linux/io.h>
  31. #include <linux/clk.h>
  32. #include <linux/serial_core.h>
  33. #include <linux/irq.h>
  34. #include <linux/pm_runtime.h>
  35. #include <linux/pm_wakeirq.h>
  36. #include <linux/of.h>
  37. #include <linux/of_irq.h>
  38. #include <linux/gpio.h>
  39. #include <linux/of_gpio.h>
  40. #include <linux/platform_data/serial-omap.h>
  41. #include <dt-bindings/gpio/gpio.h>
  42. #define OMAP_MAX_HSUART_PORTS 10
  43. #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
  44. #define OMAP_UART_REV_42 0x0402
  45. #define OMAP_UART_REV_46 0x0406
  46. #define OMAP_UART_REV_52 0x0502
  47. #define OMAP_UART_REV_63 0x0603
  48. #define OMAP_UART_TX_WAKEUP_EN BIT(7)
  49. /* Feature flags */
  50. #define OMAP_UART_WER_HAS_TX_WAKEUP BIT(0)
  51. #define UART_ERRATA_i202_MDR1_ACCESS BIT(0)
  52. #define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1)
  53. #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz */
  54. /* SCR register bitmasks */
  55. #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
  56. #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
  57. #define OMAP_UART_SCR_TX_EMPTY (1 << 3)
  58. /* FCR register bitmasks */
  59. #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
  60. #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4)
  61. /* MVR register bitmasks */
  62. #define OMAP_UART_MVR_SCHEME_SHIFT 30
  63. #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
  64. #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
  65. #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
  66. #define OMAP_UART_MVR_MAJ_MASK 0x700
  67. #define OMAP_UART_MVR_MAJ_SHIFT 8
  68. #define OMAP_UART_MVR_MIN_MASK 0x3f
  69. #define OMAP_UART_DMA_CH_FREE -1
  70. #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
  71. #define OMAP_MODE13X_SPEED 230400
  72. /* WER = 0x7F
  73. * Enable module level wakeup in WER reg
  74. */
  75. #define OMAP_UART_WER_MOD_WKUP 0x7F
  76. /* Enable XON/XOFF flow control on output */
  77. #define OMAP_UART_SW_TX 0x08
  78. /* Enable XON/XOFF flow control on input */
  79. #define OMAP_UART_SW_RX 0x02
  80. #define OMAP_UART_SW_CLR 0xF0
  81. #define OMAP_UART_TCR_TRIG 0x0F
  82. struct uart_omap_dma {
  83. u8 uart_dma_tx;
  84. u8 uart_dma_rx;
  85. int rx_dma_channel;
  86. int tx_dma_channel;
  87. dma_addr_t rx_buf_dma_phys;
  88. dma_addr_t tx_buf_dma_phys;
  89. unsigned int uart_base;
  90. /*
  91. * Buffer for rx dma. It is not required for tx because the buffer
  92. * comes from port structure.
  93. */
  94. unsigned char *rx_buf;
  95. unsigned int prev_rx_dma_pos;
  96. int tx_buf_size;
  97. int tx_dma_used;
  98. int rx_dma_used;
  99. spinlock_t tx_lock;
  100. spinlock_t rx_lock;
  101. /* timer to poll activity on rx dma */
  102. struct timer_list rx_timer;
  103. unsigned int rx_buf_size;
  104. unsigned int rx_poll_rate;
  105. unsigned int rx_timeout;
  106. };
  107. struct uart_omap_port {
  108. struct uart_port port;
  109. struct uart_omap_dma uart_dma;
  110. struct device *dev;
  111. int wakeirq;
  112. unsigned char ier;
  113. unsigned char lcr;
  114. unsigned char mcr;
  115. unsigned char fcr;
  116. unsigned char efr;
  117. unsigned char dll;
  118. unsigned char dlh;
  119. unsigned char mdr1;
  120. unsigned char scr;
  121. unsigned char wer;
  122. int use_dma;
  123. /*
  124. * Some bits in registers are cleared on a read, so they must
  125. * be saved whenever the register is read, but the bits will not
  126. * be immediately processed.
  127. */
  128. unsigned int lsr_break_flag;
  129. unsigned char msr_saved_flags;
  130. char name[20];
  131. unsigned long port_activity;
  132. int context_loss_cnt;
  133. u32 errata;
  134. u32 features;
  135. int rts_gpio;
  136. struct pm_qos_request pm_qos_request;
  137. u32 latency;
  138. u32 calc_latency;
  139. struct work_struct qos_work;
  140. bool is_suspending;
  141. };
  142. #define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
  143. static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
  144. /* Forward declaration of functions */
  145. static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
  146. static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
  147. {
  148. offset <<= up->port.regshift;
  149. return readw(up->port.membase + offset);
  150. }
  151. static inline void serial_out(struct uart_omap_port *up, int offset, int value)
  152. {
  153. offset <<= up->port.regshift;
  154. writew(value, up->port.membase + offset);
  155. }
  156. static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
  157. {
  158. serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
  159. serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
  160. UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
  161. serial_out(up, UART_FCR, 0);
  162. }
  163. #ifdef CONFIG_PM
  164. static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
  165. {
  166. struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
  167. if (!pdata || !pdata->get_context_loss_count)
  168. return -EINVAL;
  169. return pdata->get_context_loss_count(up->dev);
  170. }
  171. /* REVISIT: Remove this when omap3 boots in device tree only mode */
  172. static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
  173. {
  174. struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
  175. if (!pdata || !pdata->enable_wakeup)
  176. return;
  177. pdata->enable_wakeup(up->dev, enable);
  178. }
  179. #endif /* CONFIG_PM */
  180. /*
  181. * Calculate the absolute difference between the desired and actual baud
  182. * rate for the given mode.
  183. */
  184. static inline int calculate_baud_abs_diff(struct uart_port *port,
  185. unsigned int baud, unsigned int mode)
  186. {
  187. unsigned int n = port->uartclk / (mode * baud);
  188. int abs_diff;
  189. if (n == 0)
  190. n = 1;
  191. abs_diff = baud - (port->uartclk / (mode * n));
  192. if (abs_diff < 0)
  193. abs_diff = -abs_diff;
  194. return abs_diff;
  195. }
  196. /*
  197. * serial_omap_baud_is_mode16 - check if baud rate is MODE16X
  198. * @port: uart port info
  199. * @baud: baudrate for which mode needs to be determined
  200. *
  201. * Returns true if baud rate is MODE16X and false if MODE13X
  202. * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values,
  203. * and Error Rates" determines modes not for all common baud rates.
  204. * E.g. for 1000000 baud rate mode must be 16x, but according to that
  205. * table it's determined as 13x.
  206. */
  207. static bool
  208. serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud)
  209. {
  210. int abs_diff_13 = calculate_baud_abs_diff(port, baud, 13);
  211. int abs_diff_16 = calculate_baud_abs_diff(port, baud, 16);
  212. return (abs_diff_13 >= abs_diff_16);
  213. }
  214. /*
  215. * serial_omap_get_divisor - calculate divisor value
  216. * @port: uart port info
  217. * @baud: baudrate for which divisor needs to be calculated.
  218. */
  219. static unsigned int
  220. serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
  221. {
  222. unsigned int mode;
  223. if (!serial_omap_baud_is_mode16(port, baud))
  224. mode = 13;
  225. else
  226. mode = 16;
  227. return port->uartclk/(mode * baud);
  228. }
  229. static void serial_omap_enable_ms(struct uart_port *port)
  230. {
  231. struct uart_omap_port *up = to_uart_omap_port(port);
  232. dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
  233. pm_runtime_get_sync(up->dev);
  234. up->ier |= UART_IER_MSI;
  235. serial_out(up, UART_IER, up->ier);
  236. pm_runtime_mark_last_busy(up->dev);
  237. pm_runtime_put_autosuspend(up->dev);
  238. }
  239. static void serial_omap_stop_tx(struct uart_port *port)
  240. {
  241. struct uart_omap_port *up = to_uart_omap_port(port);
  242. int res;
  243. pm_runtime_get_sync(up->dev);
  244. /* Handle RS-485 */
  245. if (port->rs485.flags & SER_RS485_ENABLED) {
  246. if (up->scr & OMAP_UART_SCR_TX_EMPTY) {
  247. /* THR interrupt is fired when both TX FIFO and TX
  248. * shift register are empty. This means there's nothing
  249. * left to transmit now, so make sure the THR interrupt
  250. * is fired when TX FIFO is below the trigger level,
  251. * disable THR interrupts and toggle the RS-485 GPIO
  252. * data direction pin if needed.
  253. */
  254. up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
  255. serial_out(up, UART_OMAP_SCR, up->scr);
  256. res = (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) ?
  257. 1 : 0;
  258. if (gpio_get_value(up->rts_gpio) != res) {
  259. if (port->rs485.delay_rts_after_send > 0)
  260. mdelay(
  261. port->rs485.delay_rts_after_send);
  262. gpio_set_value(up->rts_gpio, res);
  263. }
  264. } else {
  265. /* We're asked to stop, but there's still stuff in the
  266. * UART FIFO, so make sure the THR interrupt is fired
  267. * when both TX FIFO and TX shift register are empty.
  268. * The next THR interrupt (if no transmission is started
  269. * in the meantime) will indicate the end of a
  270. * transmission. Therefore we _don't_ disable THR
  271. * interrupts in this situation.
  272. */
  273. up->scr |= OMAP_UART_SCR_TX_EMPTY;
  274. serial_out(up, UART_OMAP_SCR, up->scr);
  275. return;
  276. }
  277. }
  278. if (up->ier & UART_IER_THRI) {
  279. up->ier &= ~UART_IER_THRI;
  280. serial_out(up, UART_IER, up->ier);
  281. }
  282. if ((port->rs485.flags & SER_RS485_ENABLED) &&
  283. !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
  284. /*
  285. * Empty the RX FIFO, we are not interested in anything
  286. * received during the half-duplex transmission.
  287. */
  288. serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_RCVR);
  289. /* Re-enable RX interrupts */
  290. up->ier |= UART_IER_RLSI | UART_IER_RDI;
  291. up->port.read_status_mask |= UART_LSR_DR;
  292. serial_out(up, UART_IER, up->ier);
  293. }
  294. pm_runtime_mark_last_busy(up->dev);
  295. pm_runtime_put_autosuspend(up->dev);
  296. }
  297. static void serial_omap_stop_rx(struct uart_port *port)
  298. {
  299. struct uart_omap_port *up = to_uart_omap_port(port);
  300. pm_runtime_get_sync(up->dev);
  301. up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
  302. up->port.read_status_mask &= ~UART_LSR_DR;
  303. serial_out(up, UART_IER, up->ier);
  304. pm_runtime_mark_last_busy(up->dev);
  305. pm_runtime_put_autosuspend(up->dev);
  306. }
  307. static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
  308. {
  309. struct circ_buf *xmit = &up->port.state->xmit;
  310. int count;
  311. if (up->port.x_char) {
  312. serial_out(up, UART_TX, up->port.x_char);
  313. up->port.icount.tx++;
  314. up->port.x_char = 0;
  315. return;
  316. }
  317. if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
  318. serial_omap_stop_tx(&up->port);
  319. return;
  320. }
  321. count = up->port.fifosize / 4;
  322. do {
  323. serial_out(up, UART_TX, xmit->buf[xmit->tail]);
  324. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  325. up->port.icount.tx++;
  326. if (uart_circ_empty(xmit))
  327. break;
  328. } while (--count > 0);
  329. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  330. uart_write_wakeup(&up->port);
  331. if (uart_circ_empty(xmit))
  332. serial_omap_stop_tx(&up->port);
  333. }
  334. static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
  335. {
  336. if (!(up->ier & UART_IER_THRI)) {
  337. up->ier |= UART_IER_THRI;
  338. serial_out(up, UART_IER, up->ier);
  339. }
  340. }
  341. static void serial_omap_start_tx(struct uart_port *port)
  342. {
  343. struct uart_omap_port *up = to_uart_omap_port(port);
  344. int res;
  345. pm_runtime_get_sync(up->dev);
  346. /* Handle RS-485 */
  347. if (port->rs485.flags & SER_RS485_ENABLED) {
  348. /* Fire THR interrupts when FIFO is below trigger level */
  349. up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
  350. serial_out(up, UART_OMAP_SCR, up->scr);
  351. /* if rts not already enabled */
  352. res = (port->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0;
  353. if (gpio_get_value(up->rts_gpio) != res) {
  354. gpio_set_value(up->rts_gpio, res);
  355. if (port->rs485.delay_rts_before_send > 0)
  356. mdelay(port->rs485.delay_rts_before_send);
  357. }
  358. }
  359. if ((port->rs485.flags & SER_RS485_ENABLED) &&
  360. !(port->rs485.flags & SER_RS485_RX_DURING_TX))
  361. serial_omap_stop_rx(port);
  362. serial_omap_enable_ier_thri(up);
  363. pm_runtime_mark_last_busy(up->dev);
  364. pm_runtime_put_autosuspend(up->dev);
  365. }
  366. static void serial_omap_throttle(struct uart_port *port)
  367. {
  368. struct uart_omap_port *up = to_uart_omap_port(port);
  369. unsigned long flags;
  370. pm_runtime_get_sync(up->dev);
  371. spin_lock_irqsave(&up->port.lock, flags);
  372. up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
  373. serial_out(up, UART_IER, up->ier);
  374. spin_unlock_irqrestore(&up->port.lock, flags);
  375. pm_runtime_mark_last_busy(up->dev);
  376. pm_runtime_put_autosuspend(up->dev);
  377. }
  378. static void serial_omap_unthrottle(struct uart_port *port)
  379. {
  380. struct uart_omap_port *up = to_uart_omap_port(port);
  381. unsigned long flags;
  382. pm_runtime_get_sync(up->dev);
  383. spin_lock_irqsave(&up->port.lock, flags);
  384. up->ier |= UART_IER_RLSI | UART_IER_RDI;
  385. serial_out(up, UART_IER, up->ier);
  386. spin_unlock_irqrestore(&up->port.lock, flags);
  387. pm_runtime_mark_last_busy(up->dev);
  388. pm_runtime_put_autosuspend(up->dev);
  389. }
  390. static unsigned int check_modem_status(struct uart_omap_port *up)
  391. {
  392. unsigned int status;
  393. status = serial_in(up, UART_MSR);
  394. status |= up->msr_saved_flags;
  395. up->msr_saved_flags = 0;
  396. if ((status & UART_MSR_ANY_DELTA) == 0)
  397. return status;
  398. if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
  399. up->port.state != NULL) {
  400. if (status & UART_MSR_TERI)
  401. up->port.icount.rng++;
  402. if (status & UART_MSR_DDSR)
  403. up->port.icount.dsr++;
  404. if (status & UART_MSR_DDCD)
  405. uart_handle_dcd_change
  406. (&up->port, status & UART_MSR_DCD);
  407. if (status & UART_MSR_DCTS)
  408. uart_handle_cts_change
  409. (&up->port, status & UART_MSR_CTS);
  410. wake_up_interruptible(&up->port.state->port.delta_msr_wait);
  411. }
  412. return status;
  413. }
  414. static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
  415. {
  416. unsigned int flag;
  417. unsigned char ch = 0;
  418. if (likely(lsr & UART_LSR_DR))
  419. ch = serial_in(up, UART_RX);
  420. up->port.icount.rx++;
  421. flag = TTY_NORMAL;
  422. if (lsr & UART_LSR_BI) {
  423. flag = TTY_BREAK;
  424. lsr &= ~(UART_LSR_FE | UART_LSR_PE);
  425. up->port.icount.brk++;
  426. /*
  427. * We do the SysRQ and SAK checking
  428. * here because otherwise the break
  429. * may get masked by ignore_status_mask
  430. * or read_status_mask.
  431. */
  432. if (uart_handle_break(&up->port))
  433. return;
  434. }
  435. if (lsr & UART_LSR_PE) {
  436. flag = TTY_PARITY;
  437. up->port.icount.parity++;
  438. }
  439. if (lsr & UART_LSR_FE) {
  440. flag = TTY_FRAME;
  441. up->port.icount.frame++;
  442. }
  443. if (lsr & UART_LSR_OE)
  444. up->port.icount.overrun++;
  445. #ifdef CONFIG_SERIAL_OMAP_CONSOLE
  446. if (up->port.line == up->port.cons->index) {
  447. /* Recover the break flag from console xmit */
  448. lsr |= up->lsr_break_flag;
  449. }
  450. #endif
  451. uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
  452. }
  453. static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
  454. {
  455. unsigned char ch = 0;
  456. unsigned int flag;
  457. if (!(lsr & UART_LSR_DR))
  458. return;
  459. ch = serial_in(up, UART_RX);
  460. flag = TTY_NORMAL;
  461. up->port.icount.rx++;
  462. if (uart_handle_sysrq_char(&up->port, ch))
  463. return;
  464. uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
  465. }
  466. /**
  467. * serial_omap_irq() - This handles the interrupt from one port
  468. * @irq: uart port irq number
  469. * @dev_id: uart port info
  470. */
  471. static irqreturn_t serial_omap_irq(int irq, void *dev_id)
  472. {
  473. struct uart_omap_port *up = dev_id;
  474. unsigned int iir, lsr;
  475. unsigned int type;
  476. irqreturn_t ret = IRQ_NONE;
  477. int max_count = 256;
  478. spin_lock(&up->port.lock);
  479. pm_runtime_get_sync(up->dev);
  480. do {
  481. iir = serial_in(up, UART_IIR);
  482. if (iir & UART_IIR_NO_INT)
  483. break;
  484. ret = IRQ_HANDLED;
  485. lsr = serial_in(up, UART_LSR);
  486. /* extract IRQ type from IIR register */
  487. type = iir & 0x3e;
  488. switch (type) {
  489. case UART_IIR_MSI:
  490. check_modem_status(up);
  491. break;
  492. case UART_IIR_THRI:
  493. transmit_chars(up, lsr);
  494. break;
  495. case UART_IIR_RX_TIMEOUT:
  496. /* FALLTHROUGH */
  497. case UART_IIR_RDI:
  498. serial_omap_rdi(up, lsr);
  499. break;
  500. case UART_IIR_RLSI:
  501. serial_omap_rlsi(up, lsr);
  502. break;
  503. case UART_IIR_CTS_RTS_DSR:
  504. /* simply try again */
  505. break;
  506. case UART_IIR_XOFF:
  507. /* FALLTHROUGH */
  508. default:
  509. break;
  510. }
  511. } while (max_count--);
  512. spin_unlock(&up->port.lock);
  513. tty_flip_buffer_push(&up->port.state->port);
  514. pm_runtime_mark_last_busy(up->dev);
  515. pm_runtime_put_autosuspend(up->dev);
  516. up->port_activity = jiffies;
  517. return ret;
  518. }
  519. static unsigned int serial_omap_tx_empty(struct uart_port *port)
  520. {
  521. struct uart_omap_port *up = to_uart_omap_port(port);
  522. unsigned long flags = 0;
  523. unsigned int ret = 0;
  524. pm_runtime_get_sync(up->dev);
  525. dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
  526. spin_lock_irqsave(&up->port.lock, flags);
  527. ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
  528. spin_unlock_irqrestore(&up->port.lock, flags);
  529. pm_runtime_mark_last_busy(up->dev);
  530. pm_runtime_put_autosuspend(up->dev);
  531. return ret;
  532. }
  533. static unsigned int serial_omap_get_mctrl(struct uart_port *port)
  534. {
  535. struct uart_omap_port *up = to_uart_omap_port(port);
  536. unsigned int status;
  537. unsigned int ret = 0;
  538. pm_runtime_get_sync(up->dev);
  539. status = check_modem_status(up);
  540. pm_runtime_mark_last_busy(up->dev);
  541. pm_runtime_put_autosuspend(up->dev);
  542. dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
  543. if (status & UART_MSR_DCD)
  544. ret |= TIOCM_CAR;
  545. if (status & UART_MSR_RI)
  546. ret |= TIOCM_RNG;
  547. if (status & UART_MSR_DSR)
  548. ret |= TIOCM_DSR;
  549. if (status & UART_MSR_CTS)
  550. ret |= TIOCM_CTS;
  551. return ret;
  552. }
  553. static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
  554. {
  555. struct uart_omap_port *up = to_uart_omap_port(port);
  556. unsigned char mcr = 0, old_mcr, lcr;
  557. dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
  558. if (mctrl & TIOCM_RTS)
  559. mcr |= UART_MCR_RTS;
  560. if (mctrl & TIOCM_DTR)
  561. mcr |= UART_MCR_DTR;
  562. if (mctrl & TIOCM_OUT1)
  563. mcr |= UART_MCR_OUT1;
  564. if (mctrl & TIOCM_OUT2)
  565. mcr |= UART_MCR_OUT2;
  566. if (mctrl & TIOCM_LOOP)
  567. mcr |= UART_MCR_LOOP;
  568. pm_runtime_get_sync(up->dev);
  569. old_mcr = serial_in(up, UART_MCR);
  570. old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
  571. UART_MCR_DTR | UART_MCR_RTS);
  572. up->mcr = old_mcr | mcr;
  573. serial_out(up, UART_MCR, up->mcr);
  574. /* Turn off autoRTS if RTS is lowered; restore autoRTS if RTS raised */
  575. lcr = serial_in(up, UART_LCR);
  576. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  577. if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
  578. up->efr |= UART_EFR_RTS;
  579. else
  580. up->efr &= ~UART_EFR_RTS;
  581. serial_out(up, UART_EFR, up->efr);
  582. serial_out(up, UART_LCR, lcr);
  583. pm_runtime_mark_last_busy(up->dev);
  584. pm_runtime_put_autosuspend(up->dev);
  585. }
  586. static void serial_omap_break_ctl(struct uart_port *port, int break_state)
  587. {
  588. struct uart_omap_port *up = to_uart_omap_port(port);
  589. unsigned long flags = 0;
  590. dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
  591. pm_runtime_get_sync(up->dev);
  592. spin_lock_irqsave(&up->port.lock, flags);
  593. if (break_state == -1)
  594. up->lcr |= UART_LCR_SBC;
  595. else
  596. up->lcr &= ~UART_LCR_SBC;
  597. serial_out(up, UART_LCR, up->lcr);
  598. spin_unlock_irqrestore(&up->port.lock, flags);
  599. pm_runtime_mark_last_busy(up->dev);
  600. pm_runtime_put_autosuspend(up->dev);
  601. }
  602. static int serial_omap_startup(struct uart_port *port)
  603. {
  604. struct uart_omap_port *up = to_uart_omap_port(port);
  605. unsigned long flags = 0;
  606. int retval;
  607. /*
  608. * Allocate the IRQ
  609. */
  610. retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
  611. up->name, up);
  612. if (retval)
  613. return retval;
  614. /* Optional wake-up IRQ */
  615. if (up->wakeirq) {
  616. retval = dev_pm_set_dedicated_wake_irq(up->dev, up->wakeirq);
  617. if (retval) {
  618. free_irq(up->port.irq, up);
  619. return retval;
  620. }
  621. }
  622. dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
  623. pm_runtime_get_sync(up->dev);
  624. /*
  625. * Clear the FIFO buffers and disable them.
  626. * (they will be reenabled in set_termios())
  627. */
  628. serial_omap_clear_fifos(up);
  629. /*
  630. * Clear the interrupt registers.
  631. */
  632. (void) serial_in(up, UART_LSR);
  633. if (serial_in(up, UART_LSR) & UART_LSR_DR)
  634. (void) serial_in(up, UART_RX);
  635. (void) serial_in(up, UART_IIR);
  636. (void) serial_in(up, UART_MSR);
  637. /*
  638. * Now, initialize the UART
  639. */
  640. serial_out(up, UART_LCR, UART_LCR_WLEN8);
  641. spin_lock_irqsave(&up->port.lock, flags);
  642. /*
  643. * Most PC uarts need OUT2 raised to enable interrupts.
  644. */
  645. up->port.mctrl |= TIOCM_OUT2;
  646. serial_omap_set_mctrl(&up->port, up->port.mctrl);
  647. spin_unlock_irqrestore(&up->port.lock, flags);
  648. up->msr_saved_flags = 0;
  649. /*
  650. * Finally, enable interrupts. Note: Modem status interrupts
  651. * are set via set_termios(), which will be occurring imminently
  652. * anyway, so we don't enable them here.
  653. */
  654. up->ier = UART_IER_RLSI | UART_IER_RDI;
  655. serial_out(up, UART_IER, up->ier);
  656. /* Enable module level wake up */
  657. up->wer = OMAP_UART_WER_MOD_WKUP;
  658. if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP)
  659. up->wer |= OMAP_UART_TX_WAKEUP_EN;
  660. serial_out(up, UART_OMAP_WER, up->wer);
  661. pm_runtime_mark_last_busy(up->dev);
  662. pm_runtime_put_autosuspend(up->dev);
  663. up->port_activity = jiffies;
  664. return 0;
  665. }
  666. static void serial_omap_shutdown(struct uart_port *port)
  667. {
  668. struct uart_omap_port *up = to_uart_omap_port(port);
  669. unsigned long flags = 0;
  670. dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
  671. pm_runtime_get_sync(up->dev);
  672. /*
  673. * Disable interrupts from this port
  674. */
  675. up->ier = 0;
  676. serial_out(up, UART_IER, 0);
  677. spin_lock_irqsave(&up->port.lock, flags);
  678. up->port.mctrl &= ~TIOCM_OUT2;
  679. serial_omap_set_mctrl(&up->port, up->port.mctrl);
  680. spin_unlock_irqrestore(&up->port.lock, flags);
  681. /*
  682. * Disable break condition and FIFOs
  683. */
  684. serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
  685. serial_omap_clear_fifos(up);
  686. /*
  687. * Read data port to reset things, and then free the irq
  688. */
  689. if (serial_in(up, UART_LSR) & UART_LSR_DR)
  690. (void) serial_in(up, UART_RX);
  691. pm_runtime_mark_last_busy(up->dev);
  692. pm_runtime_put_autosuspend(up->dev);
  693. free_irq(up->port.irq, up);
  694. dev_pm_clear_wake_irq(up->dev);
  695. }
  696. static void serial_omap_uart_qos_work(struct work_struct *work)
  697. {
  698. struct uart_omap_port *up = container_of(work, struct uart_omap_port,
  699. qos_work);
  700. pm_qos_update_request(&up->pm_qos_request, up->latency);
  701. }
  702. static void
  703. serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
  704. struct ktermios *old)
  705. {
  706. struct uart_omap_port *up = to_uart_omap_port(port);
  707. unsigned char cval = 0;
  708. unsigned long flags = 0;
  709. unsigned int baud, quot;
  710. switch (termios->c_cflag & CSIZE) {
  711. case CS5:
  712. cval = UART_LCR_WLEN5;
  713. break;
  714. case CS6:
  715. cval = UART_LCR_WLEN6;
  716. break;
  717. case CS7:
  718. cval = UART_LCR_WLEN7;
  719. break;
  720. default:
  721. case CS8:
  722. cval = UART_LCR_WLEN8;
  723. break;
  724. }
  725. if (termios->c_cflag & CSTOPB)
  726. cval |= UART_LCR_STOP;
  727. if (termios->c_cflag & PARENB)
  728. cval |= UART_LCR_PARITY;
  729. if (!(termios->c_cflag & PARODD))
  730. cval |= UART_LCR_EPAR;
  731. if (termios->c_cflag & CMSPAR)
  732. cval |= UART_LCR_SPAR;
  733. /*
  734. * Ask the core to calculate the divisor for us.
  735. */
  736. baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
  737. quot = serial_omap_get_divisor(port, baud);
  738. /* calculate wakeup latency constraint */
  739. up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
  740. up->latency = up->calc_latency;
  741. schedule_work(&up->qos_work);
  742. up->dll = quot & 0xff;
  743. up->dlh = quot >> 8;
  744. up->mdr1 = UART_OMAP_MDR1_DISABLE;
  745. up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
  746. UART_FCR_ENABLE_FIFO;
  747. /*
  748. * Ok, we're now changing the port state. Do it with
  749. * interrupts disabled.
  750. */
  751. pm_runtime_get_sync(up->dev);
  752. spin_lock_irqsave(&up->port.lock, flags);
  753. /*
  754. * Update the per-port timeout.
  755. */
  756. uart_update_timeout(port, termios->c_cflag, baud);
  757. up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
  758. if (termios->c_iflag & INPCK)
  759. up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
  760. if (termios->c_iflag & (BRKINT | PARMRK))
  761. up->port.read_status_mask |= UART_LSR_BI;
  762. /*
  763. * Characters to ignore
  764. */
  765. up->port.ignore_status_mask = 0;
  766. if (termios->c_iflag & IGNPAR)
  767. up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
  768. if (termios->c_iflag & IGNBRK) {
  769. up->port.ignore_status_mask |= UART_LSR_BI;
  770. /*
  771. * If we're ignoring parity and break indicators,
  772. * ignore overruns too (for real raw support).
  773. */
  774. if (termios->c_iflag & IGNPAR)
  775. up->port.ignore_status_mask |= UART_LSR_OE;
  776. }
  777. /*
  778. * ignore all characters if CREAD is not set
  779. */
  780. if ((termios->c_cflag & CREAD) == 0)
  781. up->port.ignore_status_mask |= UART_LSR_DR;
  782. /*
  783. * Modem status interrupts
  784. */
  785. up->ier &= ~UART_IER_MSI;
  786. if (UART_ENABLE_MS(&up->port, termios->c_cflag))
  787. up->ier |= UART_IER_MSI;
  788. serial_out(up, UART_IER, up->ier);
  789. serial_out(up, UART_LCR, cval); /* reset DLAB */
  790. up->lcr = cval;
  791. up->scr = 0;
  792. /* FIFOs and DMA Settings */
  793. /* FCR can be changed only when the
  794. * baud clock is not running
  795. * DLL_REG and DLH_REG set to 0.
  796. */
  797. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
  798. serial_out(up, UART_DLL, 0);
  799. serial_out(up, UART_DLM, 0);
  800. serial_out(up, UART_LCR, 0);
  801. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  802. up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
  803. up->efr &= ~UART_EFR_SCD;
  804. serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
  805. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
  806. up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
  807. serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
  808. /* FIFO ENABLE, DMA MODE */
  809. up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
  810. /*
  811. * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
  812. * sets Enables the granularity of 1 for TRIGGER RX
  813. * level. Along with setting RX FIFO trigger level
  814. * to 1 (as noted below, 16 characters) and TLR[3:0]
  815. * to zero this will result RX FIFO threshold level
  816. * to 1 character, instead of 16 as noted in comment
  817. * below.
  818. */
  819. /* Set receive FIFO threshold to 16 characters and
  820. * transmit FIFO threshold to 32 spaces
  821. */
  822. up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
  823. up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
  824. up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
  825. UART_FCR_ENABLE_FIFO;
  826. serial_out(up, UART_FCR, up->fcr);
  827. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  828. serial_out(up, UART_OMAP_SCR, up->scr);
  829. /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
  830. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
  831. serial_out(up, UART_MCR, up->mcr);
  832. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  833. serial_out(up, UART_EFR, up->efr);
  834. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
  835. /* Protocol, Baud Rate, and Interrupt Settings */
  836. if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
  837. serial_omap_mdr1_errataset(up, up->mdr1);
  838. else
  839. serial_out(up, UART_OMAP_MDR1, up->mdr1);
  840. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  841. serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
  842. serial_out(up, UART_LCR, 0);
  843. serial_out(up, UART_IER, 0);
  844. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  845. serial_out(up, UART_DLL, up->dll); /* LS of divisor */
  846. serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
  847. serial_out(up, UART_LCR, 0);
  848. serial_out(up, UART_IER, up->ier);
  849. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  850. serial_out(up, UART_EFR, up->efr);
  851. serial_out(up, UART_LCR, cval);
  852. if (!serial_omap_baud_is_mode16(port, baud))
  853. up->mdr1 = UART_OMAP_MDR1_13X_MODE;
  854. else
  855. up->mdr1 = UART_OMAP_MDR1_16X_MODE;
  856. if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
  857. serial_omap_mdr1_errataset(up, up->mdr1);
  858. else
  859. serial_out(up, UART_OMAP_MDR1, up->mdr1);
  860. /* Configure flow control */
  861. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  862. /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
  863. serial_out(up, UART_XON1, termios->c_cc[VSTART]);
  864. serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
  865. /* Enable access to TCR/TLR */
  866. serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
  867. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
  868. serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
  869. serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
  870. up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
  871. if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
  872. /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
  873. up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
  874. up->efr |= UART_EFR_CTS;
  875. } else {
  876. /* Disable AUTORTS and AUTOCTS */
  877. up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
  878. }
  879. if (up->port.flags & UPF_SOFT_FLOW) {
  880. /* clear SW control mode bits */
  881. up->efr &= OMAP_UART_SW_CLR;
  882. /*
  883. * IXON Flag:
  884. * Enable XON/XOFF flow control on input.
  885. * Receiver compares XON1, XOFF1.
  886. */
  887. if (termios->c_iflag & IXON)
  888. up->efr |= OMAP_UART_SW_RX;
  889. /*
  890. * IXOFF Flag:
  891. * Enable XON/XOFF flow control on output.
  892. * Transmit XON1, XOFF1
  893. */
  894. if (termios->c_iflag & IXOFF) {
  895. up->port.status |= UPSTAT_AUTOXOFF;
  896. up->efr |= OMAP_UART_SW_TX;
  897. }
  898. /*
  899. * IXANY Flag:
  900. * Enable any character to restart output.
  901. * Operation resumes after receiving any
  902. * character after recognition of the XOFF character
  903. */
  904. if (termios->c_iflag & IXANY)
  905. up->mcr |= UART_MCR_XONANY;
  906. else
  907. up->mcr &= ~UART_MCR_XONANY;
  908. }
  909. serial_out(up, UART_MCR, up->mcr);
  910. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  911. serial_out(up, UART_EFR, up->efr);
  912. serial_out(up, UART_LCR, up->lcr);
  913. serial_omap_set_mctrl(&up->port, up->port.mctrl);
  914. spin_unlock_irqrestore(&up->port.lock, flags);
  915. pm_runtime_mark_last_busy(up->dev);
  916. pm_runtime_put_autosuspend(up->dev);
  917. dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
  918. }
  919. static void
  920. serial_omap_pm(struct uart_port *port, unsigned int state,
  921. unsigned int oldstate)
  922. {
  923. struct uart_omap_port *up = to_uart_omap_port(port);
  924. unsigned char efr;
  925. dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
  926. pm_runtime_get_sync(up->dev);
  927. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  928. efr = serial_in(up, UART_EFR);
  929. serial_out(up, UART_EFR, efr | UART_EFR_ECB);
  930. serial_out(up, UART_LCR, 0);
  931. serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
  932. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  933. serial_out(up, UART_EFR, efr);
  934. serial_out(up, UART_LCR, 0);
  935. pm_runtime_mark_last_busy(up->dev);
  936. pm_runtime_put_autosuspend(up->dev);
  937. }
  938. static void serial_omap_release_port(struct uart_port *port)
  939. {
  940. dev_dbg(port->dev, "serial_omap_release_port+\n");
  941. }
  942. static int serial_omap_request_port(struct uart_port *port)
  943. {
  944. dev_dbg(port->dev, "serial_omap_request_port+\n");
  945. return 0;
  946. }
  947. static void serial_omap_config_port(struct uart_port *port, int flags)
  948. {
  949. struct uart_omap_port *up = to_uart_omap_port(port);
  950. dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
  951. up->port.line);
  952. up->port.type = PORT_OMAP;
  953. up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
  954. }
  955. static int
  956. serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
  957. {
  958. /* we don't want the core code to modify any port params */
  959. dev_dbg(port->dev, "serial_omap_verify_port+\n");
  960. return -EINVAL;
  961. }
  962. static const char *
  963. serial_omap_type(struct uart_port *port)
  964. {
  965. struct uart_omap_port *up = to_uart_omap_port(port);
  966. dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
  967. return up->name;
  968. }
  969. #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
  970. static void __maybe_unused wait_for_xmitr(struct uart_omap_port *up)
  971. {
  972. unsigned int status, tmout = 10000;
  973. /* Wait up to 10ms for the character(s) to be sent. */
  974. do {
  975. status = serial_in(up, UART_LSR);
  976. if (status & UART_LSR_BI)
  977. up->lsr_break_flag = UART_LSR_BI;
  978. if (--tmout == 0)
  979. break;
  980. udelay(1);
  981. } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
  982. /* Wait up to 1s for flow control if necessary */
  983. if (up->port.flags & UPF_CONS_FLOW) {
  984. tmout = 1000000;
  985. for (tmout = 1000000; tmout; tmout--) {
  986. unsigned int msr = serial_in(up, UART_MSR);
  987. up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
  988. if (msr & UART_MSR_CTS)
  989. break;
  990. udelay(1);
  991. }
  992. }
  993. }
  994. #ifdef CONFIG_CONSOLE_POLL
  995. static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
  996. {
  997. struct uart_omap_port *up = to_uart_omap_port(port);
  998. pm_runtime_get_sync(up->dev);
  999. wait_for_xmitr(up);
  1000. serial_out(up, UART_TX, ch);
  1001. pm_runtime_mark_last_busy(up->dev);
  1002. pm_runtime_put_autosuspend(up->dev);
  1003. }
  1004. static int serial_omap_poll_get_char(struct uart_port *port)
  1005. {
  1006. struct uart_omap_port *up = to_uart_omap_port(port);
  1007. unsigned int status;
  1008. pm_runtime_get_sync(up->dev);
  1009. status = serial_in(up, UART_LSR);
  1010. if (!(status & UART_LSR_DR)) {
  1011. status = NO_POLL_CHAR;
  1012. goto out;
  1013. }
  1014. status = serial_in(up, UART_RX);
  1015. out:
  1016. pm_runtime_mark_last_busy(up->dev);
  1017. pm_runtime_put_autosuspend(up->dev);
  1018. return status;
  1019. }
  1020. #endif /* CONFIG_CONSOLE_POLL */
  1021. #ifdef CONFIG_SERIAL_OMAP_CONSOLE
  1022. #ifdef CONFIG_SERIAL_EARLYCON
  1023. static unsigned int omap_serial_early_in(struct uart_port *port, int offset)
  1024. {
  1025. offset <<= port->regshift;
  1026. return readw(port->membase + offset);
  1027. }
  1028. static void omap_serial_early_out(struct uart_port *port, int offset,
  1029. int value)
  1030. {
  1031. offset <<= port->regshift;
  1032. writew(value, port->membase + offset);
  1033. }
  1034. static void omap_serial_early_putc(struct uart_port *port, int c)
  1035. {
  1036. unsigned int status;
  1037. for (;;) {
  1038. status = omap_serial_early_in(port, UART_LSR);
  1039. if ((status & BOTH_EMPTY) == BOTH_EMPTY)
  1040. break;
  1041. cpu_relax();
  1042. }
  1043. omap_serial_early_out(port, UART_TX, c);
  1044. }
  1045. static void early_omap_serial_write(struct console *console, const char *s,
  1046. unsigned int count)
  1047. {
  1048. struct earlycon_device *device = console->data;
  1049. struct uart_port *port = &device->port;
  1050. uart_console_write(port, s, count, omap_serial_early_putc);
  1051. }
  1052. static int __init early_omap_serial_setup(struct earlycon_device *device,
  1053. const char *options)
  1054. {
  1055. struct uart_port *port = &device->port;
  1056. if (!(device->port.membase || device->port.iobase))
  1057. return -ENODEV;
  1058. port->regshift = 2;
  1059. device->con->write = early_omap_serial_write;
  1060. return 0;
  1061. }
  1062. OF_EARLYCON_DECLARE(omapserial, "ti,omap2-uart", early_omap_serial_setup);
  1063. OF_EARLYCON_DECLARE(omapserial, "ti,omap3-uart", early_omap_serial_setup);
  1064. OF_EARLYCON_DECLARE(omapserial, "ti,omap4-uart", early_omap_serial_setup);
  1065. #endif /* CONFIG_SERIAL_EARLYCON */
  1066. static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
  1067. static struct uart_driver serial_omap_reg;
  1068. static void serial_omap_console_putchar(struct uart_port *port, int ch)
  1069. {
  1070. struct uart_omap_port *up = to_uart_omap_port(port);
  1071. wait_for_xmitr(up);
  1072. serial_out(up, UART_TX, ch);
  1073. }
  1074. static void
  1075. serial_omap_console_write(struct console *co, const char *s,
  1076. unsigned int count)
  1077. {
  1078. struct uart_omap_port *up = serial_omap_console_ports[co->index];
  1079. unsigned long flags;
  1080. unsigned int ier;
  1081. int locked = 1;
  1082. pm_runtime_get_sync(up->dev);
  1083. local_irq_save(flags);
  1084. if (up->port.sysrq)
  1085. locked = 0;
  1086. else if (oops_in_progress)
  1087. locked = spin_trylock(&up->port.lock);
  1088. else
  1089. spin_lock(&up->port.lock);
  1090. /*
  1091. * First save the IER then disable the interrupts
  1092. */
  1093. ier = serial_in(up, UART_IER);
  1094. serial_out(up, UART_IER, 0);
  1095. uart_console_write(&up->port, s, count, serial_omap_console_putchar);
  1096. /*
  1097. * Finally, wait for transmitter to become empty
  1098. * and restore the IER
  1099. */
  1100. wait_for_xmitr(up);
  1101. serial_out(up, UART_IER, ier);
  1102. /*
  1103. * The receive handling will happen properly because the
  1104. * receive ready bit will still be set; it is not cleared
  1105. * on read. However, modem control will not, we must
  1106. * call it if we have saved something in the saved flags
  1107. * while processing with interrupts off.
  1108. */
  1109. if (up->msr_saved_flags)
  1110. check_modem_status(up);
  1111. pm_runtime_mark_last_busy(up->dev);
  1112. pm_runtime_put_autosuspend(up->dev);
  1113. if (locked)
  1114. spin_unlock(&up->port.lock);
  1115. local_irq_restore(flags);
  1116. }
  1117. static int __init
  1118. serial_omap_console_setup(struct console *co, char *options)
  1119. {
  1120. struct uart_omap_port *up;
  1121. int baud = 115200;
  1122. int bits = 8;
  1123. int parity = 'n';
  1124. int flow = 'n';
  1125. if (serial_omap_console_ports[co->index] == NULL)
  1126. return -ENODEV;
  1127. up = serial_omap_console_ports[co->index];
  1128. if (options)
  1129. uart_parse_options(options, &baud, &parity, &bits, &flow);
  1130. return uart_set_options(&up->port, co, baud, parity, bits, flow);
  1131. }
  1132. static struct console serial_omap_console = {
  1133. .name = OMAP_SERIAL_NAME,
  1134. .write = serial_omap_console_write,
  1135. .device = uart_console_device,
  1136. .setup = serial_omap_console_setup,
  1137. .flags = CON_PRINTBUFFER,
  1138. .index = -1,
  1139. .data = &serial_omap_reg,
  1140. };
  1141. static void serial_omap_add_console_port(struct uart_omap_port *up)
  1142. {
  1143. serial_omap_console_ports[up->port.line] = up;
  1144. }
  1145. #define OMAP_CONSOLE (&serial_omap_console)
  1146. #else
  1147. #define OMAP_CONSOLE NULL
  1148. static inline void serial_omap_add_console_port(struct uart_omap_port *up)
  1149. {}
  1150. #endif
  1151. /* Enable or disable the rs485 support */
  1152. static int
  1153. serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485)
  1154. {
  1155. struct uart_omap_port *up = to_uart_omap_port(port);
  1156. unsigned int mode;
  1157. int val;
  1158. pm_runtime_get_sync(up->dev);
  1159. /* Disable interrupts from this port */
  1160. mode = up->ier;
  1161. up->ier = 0;
  1162. serial_out(up, UART_IER, 0);
  1163. /* Clamp the delays to [0, 100ms] */
  1164. rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
  1165. rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U);
  1166. /* store new config */
  1167. port->rs485 = *rs485;
  1168. /*
  1169. * Just as a precaution, only allow rs485
  1170. * to be enabled if the gpio pin is valid
  1171. */
  1172. if (gpio_is_valid(up->rts_gpio)) {
  1173. /* enable / disable rts */
  1174. val = (port->rs485.flags & SER_RS485_ENABLED) ?
  1175. SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;
  1176. val = (port->rs485.flags & val) ? 1 : 0;
  1177. gpio_set_value(up->rts_gpio, val);
  1178. } else
  1179. port->rs485.flags &= ~SER_RS485_ENABLED;
  1180. /* Enable interrupts */
  1181. up->ier = mode;
  1182. serial_out(up, UART_IER, up->ier);
  1183. /* If RS-485 is disabled, make sure the THR interrupt is fired when
  1184. * TX FIFO is below the trigger level.
  1185. */
  1186. if (!(port->rs485.flags & SER_RS485_ENABLED) &&
  1187. (up->scr & OMAP_UART_SCR_TX_EMPTY)) {
  1188. up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
  1189. serial_out(up, UART_OMAP_SCR, up->scr);
  1190. }
  1191. pm_runtime_mark_last_busy(up->dev);
  1192. pm_runtime_put_autosuspend(up->dev);
  1193. return 0;
  1194. }
  1195. static const struct uart_ops serial_omap_pops = {
  1196. .tx_empty = serial_omap_tx_empty,
  1197. .set_mctrl = serial_omap_set_mctrl,
  1198. .get_mctrl = serial_omap_get_mctrl,
  1199. .stop_tx = serial_omap_stop_tx,
  1200. .start_tx = serial_omap_start_tx,
  1201. .throttle = serial_omap_throttle,
  1202. .unthrottle = serial_omap_unthrottle,
  1203. .stop_rx = serial_omap_stop_rx,
  1204. .enable_ms = serial_omap_enable_ms,
  1205. .break_ctl = serial_omap_break_ctl,
  1206. .startup = serial_omap_startup,
  1207. .shutdown = serial_omap_shutdown,
  1208. .set_termios = serial_omap_set_termios,
  1209. .pm = serial_omap_pm,
  1210. .type = serial_omap_type,
  1211. .release_port = serial_omap_release_port,
  1212. .request_port = serial_omap_request_port,
  1213. .config_port = serial_omap_config_port,
  1214. .verify_port = serial_omap_verify_port,
  1215. #ifdef CONFIG_CONSOLE_POLL
  1216. .poll_put_char = serial_omap_poll_put_char,
  1217. .poll_get_char = serial_omap_poll_get_char,
  1218. #endif
  1219. };
  1220. static struct uart_driver serial_omap_reg = {
  1221. .owner = THIS_MODULE,
  1222. .driver_name = "OMAP-SERIAL",
  1223. .dev_name = OMAP_SERIAL_NAME,
  1224. .nr = OMAP_MAX_HSUART_PORTS,
  1225. .cons = OMAP_CONSOLE,
  1226. };
  1227. #ifdef CONFIG_PM_SLEEP
  1228. static int serial_omap_prepare(struct device *dev)
  1229. {
  1230. struct uart_omap_port *up = dev_get_drvdata(dev);
  1231. up->is_suspending = true;
  1232. return 0;
  1233. }
  1234. static void serial_omap_complete(struct device *dev)
  1235. {
  1236. struct uart_omap_port *up = dev_get_drvdata(dev);
  1237. up->is_suspending = false;
  1238. }
  1239. static int serial_omap_suspend(struct device *dev)
  1240. {
  1241. struct uart_omap_port *up = dev_get_drvdata(dev);
  1242. uart_suspend_port(&serial_omap_reg, &up->port);
  1243. flush_work(&up->qos_work);
  1244. if (device_may_wakeup(dev))
  1245. serial_omap_enable_wakeup(up, true);
  1246. else
  1247. serial_omap_enable_wakeup(up, false);
  1248. return 0;
  1249. }
  1250. static int serial_omap_resume(struct device *dev)
  1251. {
  1252. struct uart_omap_port *up = dev_get_drvdata(dev);
  1253. if (device_may_wakeup(dev))
  1254. serial_omap_enable_wakeup(up, false);
  1255. uart_resume_port(&serial_omap_reg, &up->port);
  1256. return 0;
  1257. }
  1258. #else
  1259. #define serial_omap_prepare NULL
  1260. #define serial_omap_complete NULL
  1261. #endif /* CONFIG_PM_SLEEP */
  1262. static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
  1263. {
  1264. u32 mvr, scheme;
  1265. u16 revision, major, minor;
  1266. mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift));
  1267. /* Check revision register scheme */
  1268. scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
  1269. switch (scheme) {
  1270. case 0: /* Legacy Scheme: OMAP2/3 */
  1271. /* MINOR_REV[0:4], MAJOR_REV[4:7] */
  1272. major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
  1273. OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
  1274. minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
  1275. break;
  1276. case 1:
  1277. /* New Scheme: OMAP4+ */
  1278. /* MINOR_REV[0:5], MAJOR_REV[8:10] */
  1279. major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
  1280. OMAP_UART_MVR_MAJ_SHIFT;
  1281. minor = (mvr & OMAP_UART_MVR_MIN_MASK);
  1282. break;
  1283. default:
  1284. dev_warn(up->dev,
  1285. "Unknown %s revision, defaulting to highest\n",
  1286. up->name);
  1287. /* highest possible revision */
  1288. major = 0xff;
  1289. minor = 0xff;
  1290. }
  1291. /* normalize revision for the driver */
  1292. revision = UART_BUILD_REVISION(major, minor);
  1293. switch (revision) {
  1294. case OMAP_UART_REV_46:
  1295. up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
  1296. UART_ERRATA_i291_DMA_FORCEIDLE);
  1297. break;
  1298. case OMAP_UART_REV_52:
  1299. up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
  1300. UART_ERRATA_i291_DMA_FORCEIDLE);
  1301. up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
  1302. break;
  1303. case OMAP_UART_REV_63:
  1304. up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
  1305. up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
  1306. break;
  1307. default:
  1308. break;
  1309. }
  1310. }
  1311. static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
  1312. {
  1313. struct omap_uart_port_info *omap_up_info;
  1314. omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
  1315. if (!omap_up_info)
  1316. return NULL; /* out of memory */
  1317. of_property_read_u32(dev->of_node, "clock-frequency",
  1318. &omap_up_info->uartclk);
  1319. omap_up_info->flags = UPF_BOOT_AUTOCONF;
  1320. return omap_up_info;
  1321. }
  1322. static int serial_omap_probe_rs485(struct uart_omap_port *up,
  1323. struct device_node *np)
  1324. {
  1325. struct serial_rs485 *rs485conf = &up->port.rs485;
  1326. int ret;
  1327. rs485conf->flags = 0;
  1328. up->rts_gpio = -EINVAL;
  1329. if (!np)
  1330. return 0;
  1331. uart_get_rs485_mode(up->dev, rs485conf);
  1332. if (of_property_read_bool(np, "rs485-rts-active-high")) {
  1333. rs485conf->flags |= SER_RS485_RTS_ON_SEND;
  1334. rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
  1335. } else {
  1336. rs485conf->flags &= ~SER_RS485_RTS_ON_SEND;
  1337. rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
  1338. }
  1339. /* check for tx enable gpio */
  1340. up->rts_gpio = of_get_named_gpio(np, "rts-gpio", 0);
  1341. if (gpio_is_valid(up->rts_gpio)) {
  1342. ret = devm_gpio_request(up->dev, up->rts_gpio, "omap-serial");
  1343. if (ret < 0)
  1344. return ret;
  1345. ret = rs485conf->flags & SER_RS485_RTS_AFTER_SEND ? 1 : 0;
  1346. ret = gpio_direction_output(up->rts_gpio, ret);
  1347. if (ret < 0)
  1348. return ret;
  1349. } else if (up->rts_gpio == -EPROBE_DEFER) {
  1350. return -EPROBE_DEFER;
  1351. } else {
  1352. up->rts_gpio = -EINVAL;
  1353. }
  1354. return 0;
  1355. }
  1356. static int serial_omap_probe(struct platform_device *pdev)
  1357. {
  1358. struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);
  1359. struct uart_omap_port *up;
  1360. struct resource *mem;
  1361. void __iomem *base;
  1362. int uartirq = 0;
  1363. int wakeirq = 0;
  1364. int ret;
  1365. /* The optional wakeirq may be specified in the board dts file */
  1366. if (pdev->dev.of_node) {
  1367. uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0);
  1368. if (!uartirq)
  1369. return -EPROBE_DEFER;
  1370. wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
  1371. omap_up_info = of_get_uart_port_info(&pdev->dev);
  1372. pdev->dev.platform_data = omap_up_info;
  1373. } else {
  1374. uartirq = platform_get_irq(pdev, 0);
  1375. if (uartirq < 0)
  1376. return -EPROBE_DEFER;
  1377. }
  1378. up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
  1379. if (!up)
  1380. return -ENOMEM;
  1381. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1382. base = devm_ioremap_resource(&pdev->dev, mem);
  1383. if (IS_ERR(base))
  1384. return PTR_ERR(base);
  1385. up->dev = &pdev->dev;
  1386. up->port.dev = &pdev->dev;
  1387. up->port.type = PORT_OMAP;
  1388. up->port.iotype = UPIO_MEM;
  1389. up->port.irq = uartirq;
  1390. up->port.regshift = 2;
  1391. up->port.fifosize = 64;
  1392. up->port.ops = &serial_omap_pops;
  1393. if (pdev->dev.of_node)
  1394. ret = of_alias_get_id(pdev->dev.of_node, "serial");
  1395. else
  1396. ret = pdev->id;
  1397. if (ret < 0) {
  1398. dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
  1399. ret);
  1400. goto err_port_line;
  1401. }
  1402. up->port.line = ret;
  1403. if (up->port.line >= OMAP_MAX_HSUART_PORTS) {
  1404. dev_err(&pdev->dev, "uart ID %d > MAX %d.\n", up->port.line,
  1405. OMAP_MAX_HSUART_PORTS);
  1406. ret = -ENXIO;
  1407. goto err_port_line;
  1408. }
  1409. up->wakeirq = wakeirq;
  1410. if (!up->wakeirq)
  1411. dev_info(up->port.dev, "no wakeirq for uart%d\n",
  1412. up->port.line);
  1413. ret = serial_omap_probe_rs485(up, pdev->dev.of_node);
  1414. if (ret < 0)
  1415. goto err_rs485;
  1416. sprintf(up->name, "OMAP UART%d", up->port.line);
  1417. up->port.mapbase = mem->start;
  1418. up->port.membase = base;
  1419. up->port.flags = omap_up_info->flags;
  1420. up->port.uartclk = omap_up_info->uartclk;
  1421. up->port.rs485_config = serial_omap_config_rs485;
  1422. if (!up->port.uartclk) {
  1423. up->port.uartclk = DEFAULT_CLK_SPEED;
  1424. dev_warn(&pdev->dev,
  1425. "No clock speed specified: using default: %d\n",
  1426. DEFAULT_CLK_SPEED);
  1427. }
  1428. up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
  1429. up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
  1430. pm_qos_add_request(&up->pm_qos_request,
  1431. PM_QOS_CPU_DMA_LATENCY, up->latency);
  1432. INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
  1433. platform_set_drvdata(pdev, up);
  1434. if (omap_up_info->autosuspend_timeout == 0)
  1435. omap_up_info->autosuspend_timeout = -1;
  1436. device_init_wakeup(up->dev, true);
  1437. pm_runtime_use_autosuspend(&pdev->dev);
  1438. pm_runtime_set_autosuspend_delay(&pdev->dev,
  1439. omap_up_info->autosuspend_timeout);
  1440. pm_runtime_irq_safe(&pdev->dev);
  1441. pm_runtime_enable(&pdev->dev);
  1442. pm_runtime_get_sync(&pdev->dev);
  1443. omap_serial_fill_features_erratas(up);
  1444. ui[up->port.line] = up;
  1445. serial_omap_add_console_port(up);
  1446. ret = uart_add_one_port(&serial_omap_reg, &up->port);
  1447. if (ret != 0)
  1448. goto err_add_port;
  1449. pm_runtime_mark_last_busy(up->dev);
  1450. pm_runtime_put_autosuspend(up->dev);
  1451. return 0;
  1452. err_add_port:
  1453. pm_runtime_dont_use_autosuspend(&pdev->dev);
  1454. pm_runtime_put_sync(&pdev->dev);
  1455. pm_runtime_disable(&pdev->dev);
  1456. pm_qos_remove_request(&up->pm_qos_request);
  1457. device_init_wakeup(up->dev, false);
  1458. err_rs485:
  1459. err_port_line:
  1460. return ret;
  1461. }
  1462. static int serial_omap_remove(struct platform_device *dev)
  1463. {
  1464. struct uart_omap_port *up = platform_get_drvdata(dev);
  1465. pm_runtime_get_sync(up->dev);
  1466. uart_remove_one_port(&serial_omap_reg, &up->port);
  1467. pm_runtime_dont_use_autosuspend(up->dev);
  1468. pm_runtime_put_sync(up->dev);
  1469. pm_runtime_disable(up->dev);
  1470. pm_qos_remove_request(&up->pm_qos_request);
  1471. device_init_wakeup(&dev->dev, false);
  1472. return 0;
  1473. }
  1474. /*
  1475. * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
  1476. * The access to uart register after MDR1 Access
  1477. * causes UART to corrupt data.
  1478. *
  1479. * Need a delay =
  1480. * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
  1481. * give 10 times as much
  1482. */
  1483. static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
  1484. {
  1485. u8 timeout = 255;
  1486. serial_out(up, UART_OMAP_MDR1, mdr1);
  1487. udelay(2);
  1488. serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
  1489. UART_FCR_CLEAR_RCVR);
  1490. /*
  1491. * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
  1492. * TX_FIFO_E bit is 1.
  1493. */
  1494. while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
  1495. (UART_LSR_THRE | UART_LSR_DR))) {
  1496. timeout--;
  1497. if (!timeout) {
  1498. /* Should *never* happen. we warn and carry on */
  1499. dev_crit(up->dev, "Errata i202: timedout %x\n",
  1500. serial_in(up, UART_LSR));
  1501. break;
  1502. }
  1503. udelay(1);
  1504. }
  1505. }
  1506. #ifdef CONFIG_PM
  1507. static void serial_omap_restore_context(struct uart_omap_port *up)
  1508. {
  1509. if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
  1510. serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
  1511. else
  1512. serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
  1513. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
  1514. serial_out(up, UART_EFR, UART_EFR_ECB);
  1515. serial_out(up, UART_LCR, 0x0); /* Operational mode */
  1516. serial_out(up, UART_IER, 0x0);
  1517. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
  1518. serial_out(up, UART_DLL, up->dll);
  1519. serial_out(up, UART_DLM, up->dlh);
  1520. serial_out(up, UART_LCR, 0x0); /* Operational mode */
  1521. serial_out(up, UART_IER, up->ier);
  1522. serial_out(up, UART_FCR, up->fcr);
  1523. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
  1524. serial_out(up, UART_MCR, up->mcr);
  1525. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
  1526. serial_out(up, UART_OMAP_SCR, up->scr);
  1527. serial_out(up, UART_EFR, up->efr);
  1528. serial_out(up, UART_LCR, up->lcr);
  1529. if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
  1530. serial_omap_mdr1_errataset(up, up->mdr1);
  1531. else
  1532. serial_out(up, UART_OMAP_MDR1, up->mdr1);
  1533. serial_out(up, UART_OMAP_WER, up->wer);
  1534. }
  1535. static int serial_omap_runtime_suspend(struct device *dev)
  1536. {
  1537. struct uart_omap_port *up = dev_get_drvdata(dev);
  1538. if (!up)
  1539. return -EINVAL;
  1540. /*
  1541. * When using 'no_console_suspend', the console UART must not be
  1542. * suspended. Since driver suspend is managed by runtime suspend,
  1543. * preventing runtime suspend (by returning error) will keep device
  1544. * active during suspend.
  1545. */
  1546. if (up->is_suspending && !console_suspend_enabled &&
  1547. uart_console(&up->port))
  1548. return -EBUSY;
  1549. up->context_loss_cnt = serial_omap_get_context_loss_count(up);
  1550. serial_omap_enable_wakeup(up, true);
  1551. up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
  1552. schedule_work(&up->qos_work);
  1553. return 0;
  1554. }
  1555. static int serial_omap_runtime_resume(struct device *dev)
  1556. {
  1557. struct uart_omap_port *up = dev_get_drvdata(dev);
  1558. int loss_cnt = serial_omap_get_context_loss_count(up);
  1559. serial_omap_enable_wakeup(up, false);
  1560. if (loss_cnt < 0) {
  1561. dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n",
  1562. loss_cnt);
  1563. serial_omap_restore_context(up);
  1564. } else if (up->context_loss_cnt != loss_cnt) {
  1565. serial_omap_restore_context(up);
  1566. }
  1567. up->latency = up->calc_latency;
  1568. schedule_work(&up->qos_work);
  1569. return 0;
  1570. }
  1571. #endif
  1572. static const struct dev_pm_ops serial_omap_dev_pm_ops = {
  1573. SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
  1574. SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
  1575. serial_omap_runtime_resume, NULL)
  1576. .prepare = serial_omap_prepare,
  1577. .complete = serial_omap_complete,
  1578. };
  1579. #if defined(CONFIG_OF)
  1580. static const struct of_device_id omap_serial_of_match[] = {
  1581. { .compatible = "ti,omap2-uart" },
  1582. { .compatible = "ti,omap3-uart" },
  1583. { .compatible = "ti,omap4-uart" },
  1584. {},
  1585. };
  1586. MODULE_DEVICE_TABLE(of, omap_serial_of_match);
  1587. #endif
  1588. static struct platform_driver serial_omap_driver = {
  1589. .probe = serial_omap_probe,
  1590. .remove = serial_omap_remove,
  1591. .driver = {
  1592. .name = OMAP_SERIAL_DRIVER_NAME,
  1593. .pm = &serial_omap_dev_pm_ops,
  1594. .of_match_table = of_match_ptr(omap_serial_of_match),
  1595. },
  1596. };
  1597. static int __init serial_omap_init(void)
  1598. {
  1599. int ret;
  1600. ret = uart_register_driver(&serial_omap_reg);
  1601. if (ret != 0)
  1602. return ret;
  1603. ret = platform_driver_register(&serial_omap_driver);
  1604. if (ret != 0)
  1605. uart_unregister_driver(&serial_omap_reg);
  1606. return ret;
  1607. }
  1608. static void __exit serial_omap_exit(void)
  1609. {
  1610. platform_driver_unregister(&serial_omap_driver);
  1611. uart_unregister_driver(&serial_omap_reg);
  1612. }
  1613. module_init(serial_omap_init);
  1614. module_exit(serial_omap_exit);
  1615. MODULE_DESCRIPTION("OMAP High Speed UART driver");
  1616. MODULE_LICENSE("GPL");
  1617. MODULE_AUTHOR("Texas Instruments Inc");