rocket_int.h 42 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * rocket_int.h --- internal header file for rocket.c
  4. *
  5. * Written by Theodore Ts'o, Copyright 1997.
  6. * Copyright 1997 Comtrol Corporation.
  7. *
  8. */
  9. /*
  10. * Definition of the types in rcktpt_type
  11. */
  12. #define ROCKET_TYPE_NORMAL 0
  13. #define ROCKET_TYPE_MODEM 1
  14. #define ROCKET_TYPE_MODEMII 2
  15. #define ROCKET_TYPE_MODEMIII 3
  16. #define ROCKET_TYPE_PC104 4
  17. #include <linux/mutex.h>
  18. #include <asm/io.h>
  19. #include <asm/byteorder.h>
  20. typedef unsigned char Byte_t;
  21. typedef unsigned int ByteIO_t;
  22. typedef unsigned int Word_t;
  23. typedef unsigned int WordIO_t;
  24. typedef unsigned int DWordIO_t;
  25. /*
  26. * Note! Normally the Linux I/O macros already take care of
  27. * byte-swapping the I/O instructions. However, all accesses using
  28. * sOutDW aren't really 32-bit accesses, but should be handled in byte
  29. * order. Hence the use of the cpu_to_le32() macro to byte-swap
  30. * things to no-op the byte swapping done by the big-endian outl()
  31. * instruction.
  32. */
  33. static inline void sOutB(unsigned short port, unsigned char value)
  34. {
  35. #ifdef ROCKET_DEBUG_IO
  36. printk(KERN_DEBUG "sOutB(%x, %x)...\n", port, value);
  37. #endif
  38. outb_p(value, port);
  39. }
  40. static inline void sOutW(unsigned short port, unsigned short value)
  41. {
  42. #ifdef ROCKET_DEBUG_IO
  43. printk(KERN_DEBUG "sOutW(%x, %x)...\n", port, value);
  44. #endif
  45. outw_p(value, port);
  46. }
  47. static inline void out32(unsigned short port, Byte_t *p)
  48. {
  49. u32 value = get_unaligned_le32(p);
  50. #ifdef ROCKET_DEBUG_IO
  51. printk(KERN_DEBUG "out32(%x, %lx)...\n", port, value);
  52. #endif
  53. outl_p(value, port);
  54. }
  55. static inline unsigned char sInB(unsigned short port)
  56. {
  57. return inb_p(port);
  58. }
  59. static inline unsigned short sInW(unsigned short port)
  60. {
  61. return inw_p(port);
  62. }
  63. /* This is used to move arrays of bytes so byte swapping isn't appropriate. */
  64. #define sOutStrW(port, addr, count) if (count) outsw(port, addr, count)
  65. #define sInStrW(port, addr, count) if (count) insw(port, addr, count)
  66. #define CTL_SIZE 8
  67. #define AIOP_CTL_SIZE 4
  68. #define CHAN_AIOP_SIZE 8
  69. #define MAX_PORTS_PER_AIOP 8
  70. #define MAX_AIOPS_PER_BOARD 4
  71. #define MAX_PORTS_PER_BOARD 32
  72. /* Bus type ID */
  73. #define isISA 0
  74. #define isPCI 1
  75. #define isMC 2
  76. /* Controller ID numbers */
  77. #define CTLID_NULL -1 /* no controller exists */
  78. #define CTLID_0001 0x0001 /* controller release 1 */
  79. /* AIOP ID numbers, identifies AIOP type implementing channel */
  80. #define AIOPID_NULL -1 /* no AIOP or channel exists */
  81. #define AIOPID_0001 0x0001 /* AIOP release 1 */
  82. /************************************************************************
  83. Global Register Offsets - Direct Access - Fixed values
  84. ************************************************************************/
  85. #define _CMD_REG 0x38 /* Command Register 8 Write */
  86. #define _INT_CHAN 0x39 /* Interrupt Channel Register 8 Read */
  87. #define _INT_MASK 0x3A /* Interrupt Mask Register 8 Read / Write */
  88. #define _UNUSED 0x3B /* Unused 8 */
  89. #define _INDX_ADDR 0x3C /* Index Register Address 16 Write */
  90. #define _INDX_DATA 0x3E /* Index Register Data 8/16 Read / Write */
  91. /************************************************************************
  92. Channel Register Offsets for 1st channel in AIOP - Direct Access
  93. ************************************************************************/
  94. #define _TD0 0x00 /* Transmit Data 16 Write */
  95. #define _RD0 0x00 /* Receive Data 16 Read */
  96. #define _CHN_STAT0 0x20 /* Channel Status 8/16 Read / Write */
  97. #define _FIFO_CNT0 0x10 /* Transmit/Receive FIFO Count 16 Read */
  98. #define _INT_ID0 0x30 /* Interrupt Identification 8 Read */
  99. /************************************************************************
  100. Tx Control Register Offsets - Indexed - External - Fixed
  101. ************************************************************************/
  102. #define _TX_ENBLS 0x980 /* Tx Processor Enables Register 8 Read / Write */
  103. #define _TXCMP1 0x988 /* Transmit Compare Value #1 8 Read / Write */
  104. #define _TXCMP2 0x989 /* Transmit Compare Value #2 8 Read / Write */
  105. #define _TXREP1B1 0x98A /* Tx Replace Value #1 - Byte 1 8 Read / Write */
  106. #define _TXREP1B2 0x98B /* Tx Replace Value #1 - Byte 2 8 Read / Write */
  107. #define _TXREP2 0x98C /* Transmit Replace Value #2 8 Read / Write */
  108. /************************************************************************
  109. Memory Controller Register Offsets - Indexed - External - Fixed
  110. ************************************************************************/
  111. #define _RX_FIFO 0x000 /* Rx FIFO */
  112. #define _TX_FIFO 0x800 /* Tx FIFO */
  113. #define _RXF_OUTP 0x990 /* Rx FIFO OUT pointer 16 Read / Write */
  114. #define _RXF_INP 0x992 /* Rx FIFO IN pointer 16 Read / Write */
  115. #define _TXF_OUTP 0x994 /* Tx FIFO OUT pointer 8 Read / Write */
  116. #define _TXF_INP 0x995 /* Tx FIFO IN pointer 8 Read / Write */
  117. #define _TXP_CNT 0x996 /* Tx Priority Count 8 Read / Write */
  118. #define _TXP_PNTR 0x997 /* Tx Priority Pointer 8 Read / Write */
  119. #define PRI_PEND 0x80 /* Priority data pending (bit7, Tx pri cnt) */
  120. #define TXFIFO_SIZE 255 /* size of Tx FIFO */
  121. #define RXFIFO_SIZE 1023 /* size of Rx FIFO */
  122. /************************************************************************
  123. Tx Priority Buffer - Indexed - External - Fixed
  124. ************************************************************************/
  125. #define _TXP_BUF 0x9C0 /* Tx Priority Buffer 32 Bytes Read / Write */
  126. #define TXP_SIZE 0x20 /* 32 bytes */
  127. /************************************************************************
  128. Channel Register Offsets - Indexed - Internal - Fixed
  129. ************************************************************************/
  130. #define _TX_CTRL 0xFF0 /* Transmit Control 16 Write */
  131. #define _RX_CTRL 0xFF2 /* Receive Control 8 Write */
  132. #define _BAUD 0xFF4 /* Baud Rate 16 Write */
  133. #define _CLK_PRE 0xFF6 /* Clock Prescaler 8 Write */
  134. #define STMBREAK 0x08 /* BREAK */
  135. #define STMFRAME 0x04 /* framing error */
  136. #define STMRCVROVR 0x02 /* receiver over run error */
  137. #define STMPARITY 0x01 /* parity error */
  138. #define STMERROR (STMBREAK | STMFRAME | STMPARITY)
  139. #define STMBREAKH 0x800 /* BREAK */
  140. #define STMFRAMEH 0x400 /* framing error */
  141. #define STMRCVROVRH 0x200 /* receiver over run error */
  142. #define STMPARITYH 0x100 /* parity error */
  143. #define STMERRORH (STMBREAKH | STMFRAMEH | STMPARITYH)
  144. #define CTS_ACT 0x20 /* CTS input asserted */
  145. #define DSR_ACT 0x10 /* DSR input asserted */
  146. #define CD_ACT 0x08 /* CD input asserted */
  147. #define TXFIFOMT 0x04 /* Tx FIFO is empty */
  148. #define TXSHRMT 0x02 /* Tx shift register is empty */
  149. #define RDA 0x01 /* Rx data available */
  150. #define DRAINED (TXFIFOMT | TXSHRMT) /* indicates Tx is drained */
  151. #define STATMODE 0x8000 /* status mode enable bit */
  152. #define RXFOVERFL 0x2000 /* receive FIFO overflow */
  153. #define RX2MATCH 0x1000 /* receive compare byte 2 match */
  154. #define RX1MATCH 0x0800 /* receive compare byte 1 match */
  155. #define RXBREAK 0x0400 /* received BREAK */
  156. #define RXFRAME 0x0200 /* received framing error */
  157. #define RXPARITY 0x0100 /* received parity error */
  158. #define STATERROR (RXBREAK | RXFRAME | RXPARITY)
  159. #define CTSFC_EN 0x80 /* CTS flow control enable bit */
  160. #define RTSTOG_EN 0x40 /* RTS toggle enable bit */
  161. #define TXINT_EN 0x10 /* transmit interrupt enable */
  162. #define STOP2 0x08 /* enable 2 stop bits (0 = 1 stop) */
  163. #define PARITY_EN 0x04 /* enable parity (0 = no parity) */
  164. #define EVEN_PAR 0x02 /* even parity (0 = odd parity) */
  165. #define DATA8BIT 0x01 /* 8 bit data (0 = 7 bit data) */
  166. #define SETBREAK 0x10 /* send break condition (must clear) */
  167. #define LOCALLOOP 0x08 /* local loopback set for test */
  168. #define SET_DTR 0x04 /* assert DTR */
  169. #define SET_RTS 0x02 /* assert RTS */
  170. #define TX_ENABLE 0x01 /* enable transmitter */
  171. #define RTSFC_EN 0x40 /* RTS flow control enable */
  172. #define RXPROC_EN 0x20 /* receive processor enable */
  173. #define TRIG_NO 0x00 /* Rx FIFO trigger level 0 (no trigger) */
  174. #define TRIG_1 0x08 /* trigger level 1 char */
  175. #define TRIG_1_2 0x10 /* trigger level 1/2 */
  176. #define TRIG_7_8 0x18 /* trigger level 7/8 */
  177. #define TRIG_MASK 0x18 /* trigger level mask */
  178. #define SRCINT_EN 0x04 /* special Rx condition interrupt enable */
  179. #define RXINT_EN 0x02 /* Rx interrupt enable */
  180. #define MCINT_EN 0x01 /* modem change interrupt enable */
  181. #define RXF_TRIG 0x20 /* Rx FIFO trigger level interrupt */
  182. #define TXFIFO_MT 0x10 /* Tx FIFO empty interrupt */
  183. #define SRC_INT 0x08 /* special receive condition interrupt */
  184. #define DELTA_CD 0x04 /* CD change interrupt */
  185. #define DELTA_CTS 0x02 /* CTS change interrupt */
  186. #define DELTA_DSR 0x01 /* DSR change interrupt */
  187. #define REP1W2_EN 0x10 /* replace byte 1 with 2 bytes enable */
  188. #define IGN2_EN 0x08 /* ignore byte 2 enable */
  189. #define IGN1_EN 0x04 /* ignore byte 1 enable */
  190. #define COMP2_EN 0x02 /* compare byte 2 enable */
  191. #define COMP1_EN 0x01 /* compare byte 1 enable */
  192. #define RESET_ALL 0x80 /* reset AIOP (all channels) */
  193. #define TXOVERIDE 0x40 /* Transmit software off override */
  194. #define RESETUART 0x20 /* reset channel's UART */
  195. #define RESTXFCNT 0x10 /* reset channel's Tx FIFO count register */
  196. #define RESRXFCNT 0x08 /* reset channel's Rx FIFO count register */
  197. #define INTSTAT0 0x01 /* AIOP 0 interrupt status */
  198. #define INTSTAT1 0x02 /* AIOP 1 interrupt status */
  199. #define INTSTAT2 0x04 /* AIOP 2 interrupt status */
  200. #define INTSTAT3 0x08 /* AIOP 3 interrupt status */
  201. #define INTR_EN 0x08 /* allow interrupts to host */
  202. #define INT_STROB 0x04 /* strobe and clear interrupt line (EOI) */
  203. /**************************************************************************
  204. MUDBAC remapped for PCI
  205. **************************************************************************/
  206. #define _CFG_INT_PCI 0x40
  207. #define _PCI_INT_FUNC 0x3A
  208. #define PCI_STROB 0x2000 /* bit 13 of int aiop register */
  209. #define INTR_EN_PCI 0x0010 /* allow interrupts to host */
  210. /*
  211. * Definitions for Universal PCI board registers
  212. */
  213. #define _PCI_9030_INT_CTRL 0x4c /* Offsets from BAR1 */
  214. #define _PCI_9030_GPIO_CTRL 0x54
  215. #define PCI_INT_CTRL_AIOP 0x0001
  216. #define PCI_GPIO_CTRL_8PORT 0x4000
  217. #define _PCI_9030_RING_IND 0xc0 /* Offsets from BAR1 */
  218. #define CHAN3_EN 0x08 /* enable AIOP 3 */
  219. #define CHAN2_EN 0x04 /* enable AIOP 2 */
  220. #define CHAN1_EN 0x02 /* enable AIOP 1 */
  221. #define CHAN0_EN 0x01 /* enable AIOP 0 */
  222. #define FREQ_DIS 0x00
  223. #define FREQ_274HZ 0x60
  224. #define FREQ_137HZ 0x50
  225. #define FREQ_69HZ 0x40
  226. #define FREQ_34HZ 0x30
  227. #define FREQ_17HZ 0x20
  228. #define FREQ_9HZ 0x10
  229. #define PERIODIC_ONLY 0x80 /* only PERIODIC interrupt */
  230. #define CHANINT_EN 0x0100 /* flags to enable/disable channel ints */
  231. #define RDATASIZE 72
  232. #define RREGDATASIZE 52
  233. /*
  234. * AIOP interrupt bits for ISA/PCI boards and UPCI boards.
  235. */
  236. #define AIOP_INTR_BIT_0 0x0001
  237. #define AIOP_INTR_BIT_1 0x0002
  238. #define AIOP_INTR_BIT_2 0x0004
  239. #define AIOP_INTR_BIT_3 0x0008
  240. #define AIOP_INTR_BITS ( \
  241. AIOP_INTR_BIT_0 \
  242. | AIOP_INTR_BIT_1 \
  243. | AIOP_INTR_BIT_2 \
  244. | AIOP_INTR_BIT_3)
  245. #define UPCI_AIOP_INTR_BIT_0 0x0004
  246. #define UPCI_AIOP_INTR_BIT_1 0x0020
  247. #define UPCI_AIOP_INTR_BIT_2 0x0100
  248. #define UPCI_AIOP_INTR_BIT_3 0x0800
  249. #define UPCI_AIOP_INTR_BITS ( \
  250. UPCI_AIOP_INTR_BIT_0 \
  251. | UPCI_AIOP_INTR_BIT_1 \
  252. | UPCI_AIOP_INTR_BIT_2 \
  253. | UPCI_AIOP_INTR_BIT_3)
  254. /* Controller level information structure */
  255. typedef struct {
  256. int CtlID;
  257. int CtlNum;
  258. int BusType;
  259. int boardType;
  260. int isUPCI;
  261. WordIO_t PCIIO;
  262. WordIO_t PCIIO2;
  263. ByteIO_t MBaseIO;
  264. ByteIO_t MReg1IO;
  265. ByteIO_t MReg2IO;
  266. ByteIO_t MReg3IO;
  267. Byte_t MReg2;
  268. Byte_t MReg3;
  269. int NumAiop;
  270. int AltChanRingIndicator;
  271. ByteIO_t UPCIRingInd;
  272. WordIO_t AiopIO[AIOP_CTL_SIZE];
  273. ByteIO_t AiopIntChanIO[AIOP_CTL_SIZE];
  274. int AiopID[AIOP_CTL_SIZE];
  275. int AiopNumChan[AIOP_CTL_SIZE];
  276. Word_t *AiopIntrBits;
  277. } CONTROLLER_T;
  278. typedef CONTROLLER_T CONTROLLER_t;
  279. /* Channel level information structure */
  280. typedef struct {
  281. CONTROLLER_T *CtlP;
  282. int AiopNum;
  283. int ChanID;
  284. int ChanNum;
  285. int rtsToggle;
  286. ByteIO_t Cmd;
  287. ByteIO_t IntChan;
  288. ByteIO_t IntMask;
  289. DWordIO_t IndexAddr;
  290. WordIO_t IndexData;
  291. WordIO_t TxRxData;
  292. WordIO_t ChanStat;
  293. WordIO_t TxRxCount;
  294. ByteIO_t IntID;
  295. Word_t TxFIFO;
  296. Word_t TxFIFOPtrs;
  297. Word_t RxFIFO;
  298. Word_t RxFIFOPtrs;
  299. Word_t TxPrioCnt;
  300. Word_t TxPrioPtr;
  301. Word_t TxPrioBuf;
  302. Byte_t R[RREGDATASIZE];
  303. Byte_t BaudDiv[4];
  304. Byte_t TxControl[4];
  305. Byte_t RxControl[4];
  306. Byte_t TxEnables[4];
  307. Byte_t TxCompare[4];
  308. Byte_t TxReplace1[4];
  309. Byte_t TxReplace2[4];
  310. } CHANNEL_T;
  311. typedef CHANNEL_T CHANNEL_t;
  312. typedef CHANNEL_T *CHANPTR_T;
  313. #define InterfaceModeRS232 0x00
  314. #define InterfaceModeRS422 0x08
  315. #define InterfaceModeRS485 0x10
  316. #define InterfaceModeRS232T 0x18
  317. /***************************************************************************
  318. Function: sClrBreak
  319. Purpose: Stop sending a transmit BREAK signal
  320. Call: sClrBreak(ChP)
  321. CHANNEL_T *ChP; Ptr to channel structure
  322. */
  323. #define sClrBreak(ChP) \
  324. do { \
  325. (ChP)->TxControl[3] &= ~SETBREAK; \
  326. out32((ChP)->IndexAddr,(ChP)->TxControl); \
  327. } while (0)
  328. /***************************************************************************
  329. Function: sClrDTR
  330. Purpose: Clr the DTR output
  331. Call: sClrDTR(ChP)
  332. CHANNEL_T *ChP; Ptr to channel structure
  333. */
  334. #define sClrDTR(ChP) \
  335. do { \
  336. (ChP)->TxControl[3] &= ~SET_DTR; \
  337. out32((ChP)->IndexAddr,(ChP)->TxControl); \
  338. } while (0)
  339. /***************************************************************************
  340. Function: sClrRTS
  341. Purpose: Clr the RTS output
  342. Call: sClrRTS(ChP)
  343. CHANNEL_T *ChP; Ptr to channel structure
  344. */
  345. #define sClrRTS(ChP) \
  346. do { \
  347. if ((ChP)->rtsToggle) break; \
  348. (ChP)->TxControl[3] &= ~SET_RTS; \
  349. out32((ChP)->IndexAddr,(ChP)->TxControl); \
  350. } while (0)
  351. /***************************************************************************
  352. Function: sClrTxXOFF
  353. Purpose: Clear any existing transmit software flow control off condition
  354. Call: sClrTxXOFF(ChP)
  355. CHANNEL_T *ChP; Ptr to channel structure
  356. */
  357. #define sClrTxXOFF(ChP) \
  358. do { \
  359. sOutB((ChP)->Cmd,TXOVERIDE | (Byte_t)(ChP)->ChanNum); \
  360. sOutB((ChP)->Cmd,(Byte_t)(ChP)->ChanNum); \
  361. } while (0)
  362. /***************************************************************************
  363. Function: sCtlNumToCtlPtr
  364. Purpose: Convert a controller number to controller structure pointer
  365. Call: sCtlNumToCtlPtr(CtlNum)
  366. int CtlNum; Controller number
  367. Return: CONTROLLER_T *: Ptr to controller structure
  368. */
  369. #define sCtlNumToCtlPtr(CTLNUM) &sController[CTLNUM]
  370. /***************************************************************************
  371. Function: sControllerEOI
  372. Purpose: Strobe the MUDBAC's End Of Interrupt bit.
  373. Call: sControllerEOI(CtlP)
  374. CONTROLLER_T *CtlP; Ptr to controller structure
  375. */
  376. #define sControllerEOI(CTLP) sOutB((CTLP)->MReg2IO,(CTLP)->MReg2 | INT_STROB)
  377. /***************************************************************************
  378. Function: sPCIControllerEOI
  379. Purpose: Strobe the PCI End Of Interrupt bit.
  380. For the UPCI boards, toggle the AIOP interrupt enable bit
  381. (this was taken from the Windows driver).
  382. Call: sPCIControllerEOI(CtlP)
  383. CONTROLLER_T *CtlP; Ptr to controller structure
  384. */
  385. #define sPCIControllerEOI(CTLP) \
  386. do { \
  387. if ((CTLP)->isUPCI) { \
  388. Word_t w = sInW((CTLP)->PCIIO); \
  389. sOutW((CTLP)->PCIIO, (w ^ PCI_INT_CTRL_AIOP)); \
  390. sOutW((CTLP)->PCIIO, w); \
  391. } \
  392. else { \
  393. sOutW((CTLP)->PCIIO, PCI_STROB); \
  394. } \
  395. } while (0)
  396. /***************************************************************************
  397. Function: sDisAiop
  398. Purpose: Disable I/O access to an AIOP
  399. Call: sDisAiop(CltP)
  400. CONTROLLER_T *CtlP; Ptr to controller structure
  401. int AiopNum; Number of AIOP on controller
  402. */
  403. #define sDisAiop(CTLP,AIOPNUM) \
  404. do { \
  405. (CTLP)->MReg3 &= sBitMapClrTbl[AIOPNUM]; \
  406. sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \
  407. } while (0)
  408. /***************************************************************************
  409. Function: sDisCTSFlowCtl
  410. Purpose: Disable output flow control using CTS
  411. Call: sDisCTSFlowCtl(ChP)
  412. CHANNEL_T *ChP; Ptr to channel structure
  413. */
  414. #define sDisCTSFlowCtl(ChP) \
  415. do { \
  416. (ChP)->TxControl[2] &= ~CTSFC_EN; \
  417. out32((ChP)->IndexAddr,(ChP)->TxControl); \
  418. } while (0)
  419. /***************************************************************************
  420. Function: sDisIXANY
  421. Purpose: Disable IXANY Software Flow Control
  422. Call: sDisIXANY(ChP)
  423. CHANNEL_T *ChP; Ptr to channel structure
  424. */
  425. #define sDisIXANY(ChP) \
  426. do { \
  427. (ChP)->R[0x0e] = 0x86; \
  428. out32((ChP)->IndexAddr,&(ChP)->R[0x0c]); \
  429. } while (0)
  430. /***************************************************************************
  431. Function: DisParity
  432. Purpose: Disable parity
  433. Call: sDisParity(ChP)
  434. CHANNEL_T *ChP; Ptr to channel structure
  435. Comments: Function sSetParity() can be used in place of functions sEnParity(),
  436. sDisParity(), sSetOddParity(), and sSetEvenParity().
  437. */
  438. #define sDisParity(ChP) \
  439. do { \
  440. (ChP)->TxControl[2] &= ~PARITY_EN; \
  441. out32((ChP)->IndexAddr,(ChP)->TxControl); \
  442. } while (0)
  443. /***************************************************************************
  444. Function: sDisRTSToggle
  445. Purpose: Disable RTS toggle
  446. Call: sDisRTSToggle(ChP)
  447. CHANNEL_T *ChP; Ptr to channel structure
  448. */
  449. #define sDisRTSToggle(ChP) \
  450. do { \
  451. (ChP)->TxControl[2] &= ~RTSTOG_EN; \
  452. out32((ChP)->IndexAddr,(ChP)->TxControl); \
  453. (ChP)->rtsToggle = 0; \
  454. } while (0)
  455. /***************************************************************************
  456. Function: sDisRxFIFO
  457. Purpose: Disable Rx FIFO
  458. Call: sDisRxFIFO(ChP)
  459. CHANNEL_T *ChP; Ptr to channel structure
  460. */
  461. #define sDisRxFIFO(ChP) \
  462. do { \
  463. (ChP)->R[0x32] = 0x0a; \
  464. out32((ChP)->IndexAddr,&(ChP)->R[0x30]); \
  465. } while (0)
  466. /***************************************************************************
  467. Function: sDisRxStatusMode
  468. Purpose: Disable the Rx status mode
  469. Call: sDisRxStatusMode(ChP)
  470. CHANNEL_T *ChP; Ptr to channel structure
  471. Comments: This takes the channel out of the receive status mode. All
  472. subsequent reads of receive data using sReadRxWord() will return
  473. two data bytes.
  474. */
  475. #define sDisRxStatusMode(ChP) sOutW((ChP)->ChanStat,0)
  476. /***************************************************************************
  477. Function: sDisTransmit
  478. Purpose: Disable transmit
  479. Call: sDisTransmit(ChP)
  480. CHANNEL_T *ChP; Ptr to channel structure
  481. This disables movement of Tx data from the Tx FIFO into the 1 byte
  482. Tx buffer. Therefore there could be up to a 2 byte latency
  483. between the time sDisTransmit() is called and the transmit buffer
  484. and transmit shift register going completely empty.
  485. */
  486. #define sDisTransmit(ChP) \
  487. do { \
  488. (ChP)->TxControl[3] &= ~TX_ENABLE; \
  489. out32((ChP)->IndexAddr,(ChP)->TxControl); \
  490. } while (0)
  491. /***************************************************************************
  492. Function: sDisTxSoftFlowCtl
  493. Purpose: Disable Tx Software Flow Control
  494. Call: sDisTxSoftFlowCtl(ChP)
  495. CHANNEL_T *ChP; Ptr to channel structure
  496. */
  497. #define sDisTxSoftFlowCtl(ChP) \
  498. do { \
  499. (ChP)->R[0x06] = 0x8a; \
  500. out32((ChP)->IndexAddr,&(ChP)->R[0x04]); \
  501. } while (0)
  502. /***************************************************************************
  503. Function: sEnAiop
  504. Purpose: Enable I/O access to an AIOP
  505. Call: sEnAiop(CltP)
  506. CONTROLLER_T *CtlP; Ptr to controller structure
  507. int AiopNum; Number of AIOP on controller
  508. */
  509. #define sEnAiop(CTLP,AIOPNUM) \
  510. do { \
  511. (CTLP)->MReg3 |= sBitMapSetTbl[AIOPNUM]; \
  512. sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \
  513. } while (0)
  514. /***************************************************************************
  515. Function: sEnCTSFlowCtl
  516. Purpose: Enable output flow control using CTS
  517. Call: sEnCTSFlowCtl(ChP)
  518. CHANNEL_T *ChP; Ptr to channel structure
  519. */
  520. #define sEnCTSFlowCtl(ChP) \
  521. do { \
  522. (ChP)->TxControl[2] |= CTSFC_EN; \
  523. out32((ChP)->IndexAddr,(ChP)->TxControl); \
  524. } while (0)
  525. /***************************************************************************
  526. Function: sEnIXANY
  527. Purpose: Enable IXANY Software Flow Control
  528. Call: sEnIXANY(ChP)
  529. CHANNEL_T *ChP; Ptr to channel structure
  530. */
  531. #define sEnIXANY(ChP) \
  532. do { \
  533. (ChP)->R[0x0e] = 0x21; \
  534. out32((ChP)->IndexAddr,&(ChP)->R[0x0c]); \
  535. } while (0)
  536. /***************************************************************************
  537. Function: EnParity
  538. Purpose: Enable parity
  539. Call: sEnParity(ChP)
  540. CHANNEL_T *ChP; Ptr to channel structure
  541. Comments: Function sSetParity() can be used in place of functions sEnParity(),
  542. sDisParity(), sSetOddParity(), and sSetEvenParity().
  543. Warnings: Before enabling parity odd or even parity should be chosen using
  544. functions sSetOddParity() or sSetEvenParity().
  545. */
  546. #define sEnParity(ChP) \
  547. do { \
  548. (ChP)->TxControl[2] |= PARITY_EN; \
  549. out32((ChP)->IndexAddr,(ChP)->TxControl); \
  550. } while (0)
  551. /***************************************************************************
  552. Function: sEnRTSToggle
  553. Purpose: Enable RTS toggle
  554. Call: sEnRTSToggle(ChP)
  555. CHANNEL_T *ChP; Ptr to channel structure
  556. Comments: This function will disable RTS flow control and clear the RTS
  557. line to allow operation of RTS toggle.
  558. */
  559. #define sEnRTSToggle(ChP) \
  560. do { \
  561. (ChP)->RxControl[2] &= ~RTSFC_EN; \
  562. out32((ChP)->IndexAddr,(ChP)->RxControl); \
  563. (ChP)->TxControl[2] |= RTSTOG_EN; \
  564. (ChP)->TxControl[3] &= ~SET_RTS; \
  565. out32((ChP)->IndexAddr,(ChP)->TxControl); \
  566. (ChP)->rtsToggle = 1; \
  567. } while (0)
  568. /***************************************************************************
  569. Function: sEnRxFIFO
  570. Purpose: Enable Rx FIFO
  571. Call: sEnRxFIFO(ChP)
  572. CHANNEL_T *ChP; Ptr to channel structure
  573. */
  574. #define sEnRxFIFO(ChP) \
  575. do { \
  576. (ChP)->R[0x32] = 0x08; \
  577. out32((ChP)->IndexAddr,&(ChP)->R[0x30]); \
  578. } while (0)
  579. /***************************************************************************
  580. Function: sEnRxProcessor
  581. Purpose: Enable the receive processor
  582. Call: sEnRxProcessor(ChP)
  583. CHANNEL_T *ChP; Ptr to channel structure
  584. Comments: This function is used to start the receive processor. When
  585. the channel is in the reset state the receive processor is not
  586. running. This is done to prevent the receive processor from
  587. executing invalid microcode instructions prior to the
  588. downloading of the microcode.
  589. Warnings: This function must be called after valid microcode has been
  590. downloaded to the AIOP, and it must not be called before the
  591. microcode has been downloaded.
  592. */
  593. #define sEnRxProcessor(ChP) \
  594. do { \
  595. (ChP)->RxControl[2] |= RXPROC_EN; \
  596. out32((ChP)->IndexAddr,(ChP)->RxControl); \
  597. } while (0)
  598. /***************************************************************************
  599. Function: sEnRxStatusMode
  600. Purpose: Enable the Rx status mode
  601. Call: sEnRxStatusMode(ChP)
  602. CHANNEL_T *ChP; Ptr to channel structure
  603. Comments: This places the channel in the receive status mode. All subsequent
  604. reads of receive data using sReadRxWord() will return a data byte
  605. in the low word and a status byte in the high word.
  606. */
  607. #define sEnRxStatusMode(ChP) sOutW((ChP)->ChanStat,STATMODE)
  608. /***************************************************************************
  609. Function: sEnTransmit
  610. Purpose: Enable transmit
  611. Call: sEnTransmit(ChP)
  612. CHANNEL_T *ChP; Ptr to channel structure
  613. */
  614. #define sEnTransmit(ChP) \
  615. do { \
  616. (ChP)->TxControl[3] |= TX_ENABLE; \
  617. out32((ChP)->IndexAddr,(ChP)->TxControl); \
  618. } while (0)
  619. /***************************************************************************
  620. Function: sEnTxSoftFlowCtl
  621. Purpose: Enable Tx Software Flow Control
  622. Call: sEnTxSoftFlowCtl(ChP)
  623. CHANNEL_T *ChP; Ptr to channel structure
  624. */
  625. #define sEnTxSoftFlowCtl(ChP) \
  626. do { \
  627. (ChP)->R[0x06] = 0xc5; \
  628. out32((ChP)->IndexAddr,&(ChP)->R[0x04]); \
  629. } while (0)
  630. /***************************************************************************
  631. Function: sGetAiopIntStatus
  632. Purpose: Get the AIOP interrupt status
  633. Call: sGetAiopIntStatus(CtlP,AiopNum)
  634. CONTROLLER_T *CtlP; Ptr to controller structure
  635. int AiopNum; AIOP number
  636. Return: Byte_t: The AIOP interrupt status. Bits 0 through 7
  637. represent channels 0 through 7 respectively. If a
  638. bit is set that channel is interrupting.
  639. */
  640. #define sGetAiopIntStatus(CTLP,AIOPNUM) sInB((CTLP)->AiopIntChanIO[AIOPNUM])
  641. /***************************************************************************
  642. Function: sGetAiopNumChan
  643. Purpose: Get the number of channels supported by an AIOP
  644. Call: sGetAiopNumChan(CtlP,AiopNum)
  645. CONTROLLER_T *CtlP; Ptr to controller structure
  646. int AiopNum; AIOP number
  647. Return: int: The number of channels supported by the AIOP
  648. */
  649. #define sGetAiopNumChan(CTLP,AIOPNUM) (CTLP)->AiopNumChan[AIOPNUM]
  650. /***************************************************************************
  651. Function: sGetChanIntID
  652. Purpose: Get a channel's interrupt identification byte
  653. Call: sGetChanIntID(ChP)
  654. CHANNEL_T *ChP; Ptr to channel structure
  655. Return: Byte_t: The channel interrupt ID. Can be any
  656. combination of the following flags:
  657. RXF_TRIG: Rx FIFO trigger level interrupt
  658. TXFIFO_MT: Tx FIFO empty interrupt
  659. SRC_INT: Special receive condition interrupt
  660. DELTA_CD: CD change interrupt
  661. DELTA_CTS: CTS change interrupt
  662. DELTA_DSR: DSR change interrupt
  663. */
  664. #define sGetChanIntID(ChP) (sInB((ChP)->IntID) & (RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR))
  665. /***************************************************************************
  666. Function: sGetChanNum
  667. Purpose: Get the number of a channel within an AIOP
  668. Call: sGetChanNum(ChP)
  669. CHANNEL_T *ChP; Ptr to channel structure
  670. Return: int: Channel number within AIOP, or NULLCHAN if channel does
  671. not exist.
  672. */
  673. #define sGetChanNum(ChP) (ChP)->ChanNum
  674. /***************************************************************************
  675. Function: sGetChanStatus
  676. Purpose: Get the channel status
  677. Call: sGetChanStatus(ChP)
  678. CHANNEL_T *ChP; Ptr to channel structure
  679. Return: Word_t: The channel status. Can be any combination of
  680. the following flags:
  681. LOW BYTE FLAGS
  682. CTS_ACT: CTS input asserted
  683. DSR_ACT: DSR input asserted
  684. CD_ACT: CD input asserted
  685. TXFIFOMT: Tx FIFO is empty
  686. TXSHRMT: Tx shift register is empty
  687. RDA: Rx data available
  688. HIGH BYTE FLAGS
  689. STATMODE: status mode enable bit
  690. RXFOVERFL: receive FIFO overflow
  691. RX2MATCH: receive compare byte 2 match
  692. RX1MATCH: receive compare byte 1 match
  693. RXBREAK: received BREAK
  694. RXFRAME: received framing error
  695. RXPARITY: received parity error
  696. Warnings: This function will clear the high byte flags in the Channel
  697. Status Register.
  698. */
  699. #define sGetChanStatus(ChP) sInW((ChP)->ChanStat)
  700. /***************************************************************************
  701. Function: sGetChanStatusLo
  702. Purpose: Get the low byte only of the channel status
  703. Call: sGetChanStatusLo(ChP)
  704. CHANNEL_T *ChP; Ptr to channel structure
  705. Return: Byte_t: The channel status low byte. Can be any combination
  706. of the following flags:
  707. CTS_ACT: CTS input asserted
  708. DSR_ACT: DSR input asserted
  709. CD_ACT: CD input asserted
  710. TXFIFOMT: Tx FIFO is empty
  711. TXSHRMT: Tx shift register is empty
  712. RDA: Rx data available
  713. */
  714. #define sGetChanStatusLo(ChP) sInB((ByteIO_t)(ChP)->ChanStat)
  715. /**********************************************************************
  716. * Get RI status of channel
  717. * Defined as a function in rocket.c -aes
  718. */
  719. #if 0
  720. #define sGetChanRI(ChP) ((ChP)->CtlP->AltChanRingIndicator ? \
  721. (sInB((ByteIO_t)((ChP)->ChanStat+8)) & DSR_ACT) : \
  722. (((ChP)->CtlP->boardType == ROCKET_TYPE_PC104) ? \
  723. (!(sInB((ChP)->CtlP->AiopIO[3]) & sBitMapSetTbl[(ChP)->ChanNum])) : \
  724. 0))
  725. #endif
  726. /***************************************************************************
  727. Function: sGetControllerIntStatus
  728. Purpose: Get the controller interrupt status
  729. Call: sGetControllerIntStatus(CtlP)
  730. CONTROLLER_T *CtlP; Ptr to controller structure
  731. Return: Byte_t: The controller interrupt status in the lower 4
  732. bits. Bits 0 through 3 represent AIOP's 0
  733. through 3 respectively. If a bit is set that
  734. AIOP is interrupting. Bits 4 through 7 will
  735. always be cleared.
  736. */
  737. #define sGetControllerIntStatus(CTLP) (sInB((CTLP)->MReg1IO) & 0x0f)
  738. /***************************************************************************
  739. Function: sPCIGetControllerIntStatus
  740. Purpose: Get the controller interrupt status
  741. Call: sPCIGetControllerIntStatus(CtlP)
  742. CONTROLLER_T *CtlP; Ptr to controller structure
  743. Return: unsigned char: The controller interrupt status in the lower 4
  744. bits and bit 4. Bits 0 through 3 represent AIOP's 0
  745. through 3 respectively. Bit 4 is set if the int
  746. was generated from periodic. If a bit is set the
  747. AIOP is interrupting.
  748. */
  749. #define sPCIGetControllerIntStatus(CTLP) \
  750. ((CTLP)->isUPCI ? \
  751. (sInW((CTLP)->PCIIO2) & UPCI_AIOP_INTR_BITS) : \
  752. ((sInW((CTLP)->PCIIO) >> 8) & AIOP_INTR_BITS))
  753. /***************************************************************************
  754. Function: sGetRxCnt
  755. Purpose: Get the number of data bytes in the Rx FIFO
  756. Call: sGetRxCnt(ChP)
  757. CHANNEL_T *ChP; Ptr to channel structure
  758. Return: int: The number of data bytes in the Rx FIFO.
  759. Comments: Byte read of count register is required to obtain Rx count.
  760. */
  761. #define sGetRxCnt(ChP) sInW((ChP)->TxRxCount)
  762. /***************************************************************************
  763. Function: sGetTxCnt
  764. Purpose: Get the number of data bytes in the Tx FIFO
  765. Call: sGetTxCnt(ChP)
  766. CHANNEL_T *ChP; Ptr to channel structure
  767. Return: Byte_t: The number of data bytes in the Tx FIFO.
  768. Comments: Byte read of count register is required to obtain Tx count.
  769. */
  770. #define sGetTxCnt(ChP) sInB((ByteIO_t)(ChP)->TxRxCount)
  771. /*****************************************************************************
  772. Function: sGetTxRxDataIO
  773. Purpose: Get the I/O address of a channel's TxRx Data register
  774. Call: sGetTxRxDataIO(ChP)
  775. CHANNEL_T *ChP; Ptr to channel structure
  776. Return: WordIO_t: I/O address of a channel's TxRx Data register
  777. */
  778. #define sGetTxRxDataIO(ChP) (ChP)->TxRxData
  779. /***************************************************************************
  780. Function: sInitChanDefaults
  781. Purpose: Initialize a channel structure to it's default state.
  782. Call: sInitChanDefaults(ChP)
  783. CHANNEL_T *ChP; Ptr to the channel structure
  784. Comments: This function must be called once for every channel structure
  785. that exists before any other SSCI calls can be made.
  786. */
  787. #define sInitChanDefaults(ChP) \
  788. do { \
  789. (ChP)->CtlP = NULLCTLPTR; \
  790. (ChP)->AiopNum = NULLAIOP; \
  791. (ChP)->ChanID = AIOPID_NULL; \
  792. (ChP)->ChanNum = NULLCHAN; \
  793. } while (0)
  794. /***************************************************************************
  795. Function: sResetAiopByNum
  796. Purpose: Reset the AIOP by number
  797. Call: sResetAiopByNum(CTLP,AIOPNUM)
  798. CONTROLLER_T CTLP; Ptr to controller structure
  799. AIOPNUM; AIOP index
  800. */
  801. #define sResetAiopByNum(CTLP,AIOPNUM) \
  802. do { \
  803. sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,RESET_ALL); \
  804. sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,0x0); \
  805. } while (0)
  806. /***************************************************************************
  807. Function: sSendBreak
  808. Purpose: Send a transmit BREAK signal
  809. Call: sSendBreak(ChP)
  810. CHANNEL_T *ChP; Ptr to channel structure
  811. */
  812. #define sSendBreak(ChP) \
  813. do { \
  814. (ChP)->TxControl[3] |= SETBREAK; \
  815. out32((ChP)->IndexAddr,(ChP)->TxControl); \
  816. } while (0)
  817. /***************************************************************************
  818. Function: sSetBaud
  819. Purpose: Set baud rate
  820. Call: sSetBaud(ChP,Divisor)
  821. CHANNEL_T *ChP; Ptr to channel structure
  822. Word_t Divisor; 16 bit baud rate divisor for channel
  823. */
  824. #define sSetBaud(ChP,DIVISOR) \
  825. do { \
  826. (ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \
  827. (ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \
  828. out32((ChP)->IndexAddr,(ChP)->BaudDiv); \
  829. } while (0)
  830. /***************************************************************************
  831. Function: sSetData7
  832. Purpose: Set data bits to 7
  833. Call: sSetData7(ChP)
  834. CHANNEL_T *ChP; Ptr to channel structure
  835. */
  836. #define sSetData7(ChP) \
  837. do { \
  838. (ChP)->TxControl[2] &= ~DATA8BIT; \
  839. out32((ChP)->IndexAddr,(ChP)->TxControl); \
  840. } while (0)
  841. /***************************************************************************
  842. Function: sSetData8
  843. Purpose: Set data bits to 8
  844. Call: sSetData8(ChP)
  845. CHANNEL_T *ChP; Ptr to channel structure
  846. */
  847. #define sSetData8(ChP) \
  848. do { \
  849. (ChP)->TxControl[2] |= DATA8BIT; \
  850. out32((ChP)->IndexAddr,(ChP)->TxControl); \
  851. } while (0)
  852. /***************************************************************************
  853. Function: sSetDTR
  854. Purpose: Set the DTR output
  855. Call: sSetDTR(ChP)
  856. CHANNEL_T *ChP; Ptr to channel structure
  857. */
  858. #define sSetDTR(ChP) \
  859. do { \
  860. (ChP)->TxControl[3] |= SET_DTR; \
  861. out32((ChP)->IndexAddr,(ChP)->TxControl); \
  862. } while (0)
  863. /***************************************************************************
  864. Function: sSetEvenParity
  865. Purpose: Set even parity
  866. Call: sSetEvenParity(ChP)
  867. CHANNEL_T *ChP; Ptr to channel structure
  868. Comments: Function sSetParity() can be used in place of functions sEnParity(),
  869. sDisParity(), sSetOddParity(), and sSetEvenParity().
  870. Warnings: This function has no effect unless parity is enabled with function
  871. sEnParity().
  872. */
  873. #define sSetEvenParity(ChP) \
  874. do { \
  875. (ChP)->TxControl[2] |= EVEN_PAR; \
  876. out32((ChP)->IndexAddr,(ChP)->TxControl); \
  877. } while (0)
  878. /***************************************************************************
  879. Function: sSetOddParity
  880. Purpose: Set odd parity
  881. Call: sSetOddParity(ChP)
  882. CHANNEL_T *ChP; Ptr to channel structure
  883. Comments: Function sSetParity() can be used in place of functions sEnParity(),
  884. sDisParity(), sSetOddParity(), and sSetEvenParity().
  885. Warnings: This function has no effect unless parity is enabled with function
  886. sEnParity().
  887. */
  888. #define sSetOddParity(ChP) \
  889. do { \
  890. (ChP)->TxControl[2] &= ~EVEN_PAR; \
  891. out32((ChP)->IndexAddr,(ChP)->TxControl); \
  892. } while (0)
  893. /***************************************************************************
  894. Function: sSetRTS
  895. Purpose: Set the RTS output
  896. Call: sSetRTS(ChP)
  897. CHANNEL_T *ChP; Ptr to channel structure
  898. */
  899. #define sSetRTS(ChP) \
  900. do { \
  901. if ((ChP)->rtsToggle) break; \
  902. (ChP)->TxControl[3] |= SET_RTS; \
  903. out32((ChP)->IndexAddr,(ChP)->TxControl); \
  904. } while (0)
  905. /***************************************************************************
  906. Function: sSetRxTrigger
  907. Purpose: Set the Rx FIFO trigger level
  908. Call: sSetRxProcessor(ChP,Level)
  909. CHANNEL_T *ChP; Ptr to channel structure
  910. Byte_t Level; Number of characters in Rx FIFO at which the
  911. interrupt will be generated. Can be any of the following flags:
  912. TRIG_NO: no trigger
  913. TRIG_1: 1 character in FIFO
  914. TRIG_1_2: FIFO 1/2 full
  915. TRIG_7_8: FIFO 7/8 full
  916. Comments: An interrupt will be generated when the trigger level is reached
  917. only if function sEnInterrupt() has been called with flag
  918. RXINT_EN set. The RXF_TRIG flag in the Interrupt Idenfification
  919. register will be set whenever the trigger level is reached
  920. regardless of the setting of RXINT_EN.
  921. */
  922. #define sSetRxTrigger(ChP,LEVEL) \
  923. do { \
  924. (ChP)->RxControl[2] &= ~TRIG_MASK; \
  925. (ChP)->RxControl[2] |= LEVEL; \
  926. out32((ChP)->IndexAddr,(ChP)->RxControl); \
  927. } while (0)
  928. /***************************************************************************
  929. Function: sSetStop1
  930. Purpose: Set stop bits to 1
  931. Call: sSetStop1(ChP)
  932. CHANNEL_T *ChP; Ptr to channel structure
  933. */
  934. #define sSetStop1(ChP) \
  935. do { \
  936. (ChP)->TxControl[2] &= ~STOP2; \
  937. out32((ChP)->IndexAddr,(ChP)->TxControl); \
  938. } while (0)
  939. /***************************************************************************
  940. Function: sSetStop2
  941. Purpose: Set stop bits to 2
  942. Call: sSetStop2(ChP)
  943. CHANNEL_T *ChP; Ptr to channel structure
  944. */
  945. #define sSetStop2(ChP) \
  946. do { \
  947. (ChP)->TxControl[2] |= STOP2; \
  948. out32((ChP)->IndexAddr,(ChP)->TxControl); \
  949. } while (0)
  950. /***************************************************************************
  951. Function: sSetTxXOFFChar
  952. Purpose: Set the Tx XOFF flow control character
  953. Call: sSetTxXOFFChar(ChP,Ch)
  954. CHANNEL_T *ChP; Ptr to channel structure
  955. Byte_t Ch; The value to set the Tx XOFF character to
  956. */
  957. #define sSetTxXOFFChar(ChP,CH) \
  958. do { \
  959. (ChP)->R[0x07] = (CH); \
  960. out32((ChP)->IndexAddr,&(ChP)->R[0x04]); \
  961. } while (0)
  962. /***************************************************************************
  963. Function: sSetTxXONChar
  964. Purpose: Set the Tx XON flow control character
  965. Call: sSetTxXONChar(ChP,Ch)
  966. CHANNEL_T *ChP; Ptr to channel structure
  967. Byte_t Ch; The value to set the Tx XON character to
  968. */
  969. #define sSetTxXONChar(ChP,CH) \
  970. do { \
  971. (ChP)->R[0x0b] = (CH); \
  972. out32((ChP)->IndexAddr,&(ChP)->R[0x08]); \
  973. } while (0)
  974. /***************************************************************************
  975. Function: sStartRxProcessor
  976. Purpose: Start a channel's receive processor
  977. Call: sStartRxProcessor(ChP)
  978. CHANNEL_T *ChP; Ptr to channel structure
  979. Comments: This function is used to start a Rx processor after it was
  980. stopped with sStopRxProcessor() or sStopSWInFlowCtl(). It
  981. will restart both the Rx processor and software input flow control.
  982. */
  983. #define sStartRxProcessor(ChP) out32((ChP)->IndexAddr,&(ChP)->R[0])
  984. /***************************************************************************
  985. Function: sWriteTxByte
  986. Purpose: Write a transmit data byte to a channel.
  987. ByteIO_t io: Channel transmit register I/O address. This can
  988. be obtained with sGetTxRxDataIO().
  989. Byte_t Data; The transmit data byte.
  990. Warnings: This function writes the data byte without checking to see if
  991. sMaxTxSize is exceeded in the Tx FIFO.
  992. */
  993. #define sWriteTxByte(IO,DATA) sOutB(IO,DATA)
  994. /*
  995. * Begin Linux specific definitions for the Rocketport driver
  996. *
  997. * This code is Copyright Theodore Ts'o, 1995-1997
  998. */
  999. struct r_port {
  1000. int magic;
  1001. struct tty_port port;
  1002. int line;
  1003. int flags; /* Don't yet match the ASY_ flags!! */
  1004. unsigned int board:3;
  1005. unsigned int aiop:2;
  1006. unsigned int chan:3;
  1007. CONTROLLER_t *ctlp;
  1008. CHANNEL_t channel;
  1009. int intmask;
  1010. int xmit_fifo_room; /* room in xmit fifo */
  1011. unsigned char *xmit_buf;
  1012. int xmit_head;
  1013. int xmit_tail;
  1014. int xmit_cnt;
  1015. int cd_status;
  1016. int ignore_status_mask;
  1017. int read_status_mask;
  1018. int cps;
  1019. spinlock_t slock;
  1020. struct mutex write_mtx;
  1021. };
  1022. #define RPORT_MAGIC 0x525001
  1023. #define NUM_BOARDS 8
  1024. #define MAX_RP_PORTS (32*NUM_BOARDS)
  1025. /*
  1026. * The size of the xmit buffer is 1 page, or 4096 bytes
  1027. */
  1028. #define XMIT_BUF_SIZE 4096
  1029. /* number of characters left in xmit buffer before we ask for more */
  1030. #define WAKEUP_CHARS 256
  1031. /*
  1032. * Assigned major numbers for the Comtrol Rocketport
  1033. */
  1034. #define TTY_ROCKET_MAJOR 46
  1035. #define CUA_ROCKET_MAJOR 47
  1036. #ifdef PCI_VENDOR_ID_RP
  1037. #undef PCI_VENDOR_ID_RP
  1038. #undef PCI_DEVICE_ID_RP8OCTA
  1039. #undef PCI_DEVICE_ID_RP8INTF
  1040. #undef PCI_DEVICE_ID_RP16INTF
  1041. #undef PCI_DEVICE_ID_RP32INTF
  1042. #undef PCI_DEVICE_ID_URP8OCTA
  1043. #undef PCI_DEVICE_ID_URP8INTF
  1044. #undef PCI_DEVICE_ID_URP16INTF
  1045. #undef PCI_DEVICE_ID_CRP16INTF
  1046. #undef PCI_DEVICE_ID_URP32INTF
  1047. #endif
  1048. /* Comtrol PCI Vendor ID */
  1049. #define PCI_VENDOR_ID_RP 0x11fe
  1050. /* Comtrol Device ID's */
  1051. #define PCI_DEVICE_ID_RP32INTF 0x0001 /* Rocketport 32 port w/external I/F */
  1052. #define PCI_DEVICE_ID_RP8INTF 0x0002 /* Rocketport 8 port w/external I/F */
  1053. #define PCI_DEVICE_ID_RP16INTF 0x0003 /* Rocketport 16 port w/external I/F */
  1054. #define PCI_DEVICE_ID_RP4QUAD 0x0004 /* Rocketport 4 port w/quad cable */
  1055. #define PCI_DEVICE_ID_RP8OCTA 0x0005 /* Rocketport 8 port w/octa cable */
  1056. #define PCI_DEVICE_ID_RP8J 0x0006 /* Rocketport 8 port w/RJ11 connectors */
  1057. #define PCI_DEVICE_ID_RP4J 0x0007 /* Rocketport 4 port w/RJ11 connectors */
  1058. #define PCI_DEVICE_ID_RP8SNI 0x0008 /* Rocketport 8 port w/ DB78 SNI (Siemens) connector */
  1059. #define PCI_DEVICE_ID_RP16SNI 0x0009 /* Rocketport 16 port w/ DB78 SNI (Siemens) connector */
  1060. #define PCI_DEVICE_ID_RPP4 0x000A /* Rocketport Plus 4 port */
  1061. #define PCI_DEVICE_ID_RPP8 0x000B /* Rocketport Plus 8 port */
  1062. #define PCI_DEVICE_ID_RP6M 0x000C /* RocketModem 6 port */
  1063. #define PCI_DEVICE_ID_RP4M 0x000D /* RocketModem 4 port */
  1064. #define PCI_DEVICE_ID_RP2_232 0x000E /* Rocketport Plus 2 port RS232 */
  1065. #define PCI_DEVICE_ID_RP2_422 0x000F /* Rocketport Plus 2 port RS422 */
  1066. /* Universal PCI boards */
  1067. #define PCI_DEVICE_ID_URP32INTF 0x0801 /* Rocketport UPCI 32 port w/external I/F */
  1068. #define PCI_DEVICE_ID_URP8INTF 0x0802 /* Rocketport UPCI 8 port w/external I/F */
  1069. #define PCI_DEVICE_ID_URP16INTF 0x0803 /* Rocketport UPCI 16 port w/external I/F */
  1070. #define PCI_DEVICE_ID_URP8OCTA 0x0805 /* Rocketport UPCI 8 port w/octa cable */
  1071. #define PCI_DEVICE_ID_UPCI_RM3_8PORT 0x080C /* Rocketmodem III 8 port */
  1072. #define PCI_DEVICE_ID_UPCI_RM3_4PORT 0x080D /* Rocketmodem III 4 port */
  1073. /* Compact PCI device */
  1074. #define PCI_DEVICE_ID_CRP16INTF 0x0903 /* Rocketport Compact PCI 16 port w/external I/F */