tegra-apbmisc.c 3.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
  4. */
  5. #include <linux/kernel.h>
  6. #include <linux/of.h>
  7. #include <linux/of_address.h>
  8. #include <linux/io.h>
  9. #include <soc/tegra/fuse.h>
  10. #include <soc/tegra/common.h>
  11. #include "fuse.h"
  12. #define FUSE_SKU_INFO 0x10
  13. #define PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT 4
  14. #define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG \
  15. (0xf << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
  16. #define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT \
  17. (0x3 << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
  18. static void __iomem *apbmisc_base;
  19. static void __iomem *strapping_base;
  20. static bool long_ram_code;
  21. u32 tegra_read_chipid(void)
  22. {
  23. if (!apbmisc_base) {
  24. WARN(1, "Tegra Chip ID not yet available\n");
  25. return 0;
  26. }
  27. return readl_relaxed(apbmisc_base + 4);
  28. }
  29. u8 tegra_get_chip_id(void)
  30. {
  31. return (tegra_read_chipid() >> 8) & 0xff;
  32. }
  33. u32 tegra_read_straps(void)
  34. {
  35. if (strapping_base)
  36. return readl_relaxed(strapping_base);
  37. else
  38. return 0;
  39. }
  40. u32 tegra_read_ram_code(void)
  41. {
  42. u32 straps = tegra_read_straps();
  43. if (long_ram_code)
  44. straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG;
  45. else
  46. straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT;
  47. return straps >> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT;
  48. }
  49. static const struct of_device_id apbmisc_match[] __initconst = {
  50. { .compatible = "nvidia,tegra20-apbmisc", },
  51. { .compatible = "nvidia,tegra186-misc", },
  52. {},
  53. };
  54. void __init tegra_init_revision(void)
  55. {
  56. u32 id, chip_id, minor_rev;
  57. int rev;
  58. id = tegra_read_chipid();
  59. chip_id = (id >> 8) & 0xff;
  60. minor_rev = (id >> 16) & 0xf;
  61. switch (minor_rev) {
  62. case 1:
  63. rev = TEGRA_REVISION_A01;
  64. break;
  65. case 2:
  66. rev = TEGRA_REVISION_A02;
  67. break;
  68. case 3:
  69. if (chip_id == TEGRA20 && (tegra_fuse_read_spare(18) ||
  70. tegra_fuse_read_spare(19)))
  71. rev = TEGRA_REVISION_A03p;
  72. else
  73. rev = TEGRA_REVISION_A03;
  74. break;
  75. case 4:
  76. rev = TEGRA_REVISION_A04;
  77. break;
  78. default:
  79. rev = TEGRA_REVISION_UNKNOWN;
  80. }
  81. tegra_sku_info.revision = rev;
  82. tegra_sku_info.sku_id = tegra_fuse_read_early(FUSE_SKU_INFO);
  83. }
  84. void __init tegra_init_apbmisc(void)
  85. {
  86. struct resource apbmisc, straps;
  87. struct device_node *np;
  88. np = of_find_matching_node(NULL, apbmisc_match);
  89. if (!np) {
  90. /*
  91. * Fall back to legacy initialization for 32-bit ARM only. All
  92. * 64-bit ARM device tree files for Tegra are required to have
  93. * an APBMISC node.
  94. *
  95. * This is for backwards-compatibility with old device trees
  96. * that didn't contain an APBMISC node.
  97. */
  98. if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
  99. /* APBMISC registers (chip revision, ...) */
  100. apbmisc.start = 0x70000800;
  101. apbmisc.end = 0x70000863;
  102. apbmisc.flags = IORESOURCE_MEM;
  103. /* strapping options */
  104. if (of_machine_is_compatible("nvidia,tegra124")) {
  105. straps.start = 0x7000e864;
  106. straps.end = 0x7000e867;
  107. } else {
  108. straps.start = 0x70000008;
  109. straps.end = 0x7000000b;
  110. }
  111. straps.flags = IORESOURCE_MEM;
  112. pr_warn("Using APBMISC region %pR\n", &apbmisc);
  113. pr_warn("Using strapping options registers %pR\n",
  114. &straps);
  115. } else {
  116. /*
  117. * At this point we're not running on Tegra, so play
  118. * nice with multi-platform kernels.
  119. */
  120. return;
  121. }
  122. } else {
  123. /*
  124. * Extract information from the device tree if we've found a
  125. * matching node.
  126. */
  127. if (of_address_to_resource(np, 0, &apbmisc) < 0) {
  128. pr_err("failed to get APBMISC registers\n");
  129. return;
  130. }
  131. if (of_address_to_resource(np, 1, &straps) < 0) {
  132. pr_err("failed to get strapping options registers\n");
  133. return;
  134. }
  135. }
  136. apbmisc_base = ioremap_nocache(apbmisc.start, resource_size(&apbmisc));
  137. if (!apbmisc_base)
  138. pr_err("failed to map APBMISC registers\n");
  139. strapping_base = ioremap_nocache(straps.start, resource_size(&straps));
  140. if (!strapping_base)
  141. pr_err("failed to map strapping options registers\n");
  142. long_ram_code = of_property_read_bool(np, "nvidia,long-ram-code");
  143. }