fuse-tegra30.c 4.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
  4. */
  5. #include <linux/device.h>
  6. #include <linux/clk.h>
  7. #include <linux/err.h>
  8. #include <linux/io.h>
  9. #include <linux/kernel.h>
  10. #include <linux/of_device.h>
  11. #include <linux/of_address.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/random.h>
  14. #include <soc/tegra/fuse.h>
  15. #include "fuse.h"
  16. #define FUSE_BEGIN 0x100
  17. /* Tegra30 and later */
  18. #define FUSE_VENDOR_CODE 0x100
  19. #define FUSE_FAB_CODE 0x104
  20. #define FUSE_LOT_CODE_0 0x108
  21. #define FUSE_LOT_CODE_1 0x10c
  22. #define FUSE_WAFER_ID 0x110
  23. #define FUSE_X_COORDINATE 0x114
  24. #define FUSE_Y_COORDINATE 0x118
  25. #define FUSE_HAS_REVISION_INFO BIT(0)
  26. #if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \
  27. defined(CONFIG_ARCH_TEGRA_114_SOC) || \
  28. defined(CONFIG_ARCH_TEGRA_124_SOC) || \
  29. defined(CONFIG_ARCH_TEGRA_132_SOC) || \
  30. defined(CONFIG_ARCH_TEGRA_210_SOC) || \
  31. defined(CONFIG_ARCH_TEGRA_186_SOC) || \
  32. defined(CONFIG_ARCH_TEGRA_194_SOC) || \
  33. defined(CONFIG_ARCH_TEGRA_234_SOC)
  34. static u32 tegra30_fuse_read_early(struct tegra_fuse *fuse, unsigned int offset)
  35. {
  36. if (WARN_ON(!fuse->base))
  37. return 0;
  38. return readl_relaxed(fuse->base + FUSE_BEGIN + offset);
  39. }
  40. static u32 tegra30_fuse_read(struct tegra_fuse *fuse, unsigned int offset)
  41. {
  42. u32 value;
  43. int err;
  44. err = clk_prepare_enable(fuse->clk);
  45. if (err < 0) {
  46. dev_err(fuse->dev, "failed to enable FUSE clock: %d\n", err);
  47. return 0;
  48. }
  49. value = readl_relaxed(fuse->base + FUSE_BEGIN + offset);
  50. clk_disable_unprepare(fuse->clk);
  51. return value;
  52. }
  53. static void __init tegra30_fuse_add_randomness(void)
  54. {
  55. u32 randomness[12];
  56. randomness[0] = tegra_sku_info.sku_id;
  57. randomness[1] = tegra_read_straps();
  58. randomness[2] = tegra_read_chipid();
  59. randomness[3] = tegra_sku_info.cpu_process_id << 16;
  60. randomness[3] |= tegra_sku_info.soc_process_id;
  61. randomness[4] = tegra_sku_info.cpu_speedo_id << 16;
  62. randomness[4] |= tegra_sku_info.soc_speedo_id;
  63. randomness[5] = tegra_fuse_read_early(FUSE_VENDOR_CODE);
  64. randomness[6] = tegra_fuse_read_early(FUSE_FAB_CODE);
  65. randomness[7] = tegra_fuse_read_early(FUSE_LOT_CODE_0);
  66. randomness[8] = tegra_fuse_read_early(FUSE_LOT_CODE_1);
  67. randomness[9] = tegra_fuse_read_early(FUSE_WAFER_ID);
  68. randomness[10] = tegra_fuse_read_early(FUSE_X_COORDINATE);
  69. randomness[11] = tegra_fuse_read_early(FUSE_Y_COORDINATE);
  70. add_device_randomness(randomness, sizeof(randomness));
  71. }
  72. static void __init tegra30_fuse_init(struct tegra_fuse *fuse)
  73. {
  74. fuse->read_early = tegra30_fuse_read_early;
  75. fuse->read = tegra30_fuse_read;
  76. tegra_init_revision();
  77. if (fuse->soc->speedo_init)
  78. fuse->soc->speedo_init(&tegra_sku_info);
  79. tegra30_fuse_add_randomness();
  80. }
  81. #endif
  82. #ifdef CONFIG_ARCH_TEGRA_3x_SOC
  83. static const struct tegra_fuse_info tegra30_fuse_info = {
  84. .read = tegra30_fuse_read,
  85. .size = 0x2a4,
  86. .spare = 0x144,
  87. };
  88. const struct tegra_fuse_soc tegra30_fuse_soc = {
  89. .init = tegra30_fuse_init,
  90. .speedo_init = tegra30_init_speedo_data,
  91. .info = &tegra30_fuse_info,
  92. };
  93. #endif
  94. #ifdef CONFIG_ARCH_TEGRA_114_SOC
  95. static const struct tegra_fuse_info tegra114_fuse_info = {
  96. .read = tegra30_fuse_read,
  97. .size = 0x2a0,
  98. .spare = 0x180,
  99. };
  100. const struct tegra_fuse_soc tegra114_fuse_soc = {
  101. .init = tegra30_fuse_init,
  102. .speedo_init = tegra114_init_speedo_data,
  103. .info = &tegra114_fuse_info,
  104. };
  105. #endif
  106. #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
  107. static const struct tegra_fuse_info tegra124_fuse_info = {
  108. .read = tegra30_fuse_read,
  109. .size = 0x300,
  110. .spare = 0x200,
  111. };
  112. const struct tegra_fuse_soc tegra124_fuse_soc = {
  113. .init = tegra30_fuse_init,
  114. .speedo_init = tegra124_init_speedo_data,
  115. .info = &tegra124_fuse_info,
  116. };
  117. #endif
  118. #if defined(CONFIG_ARCH_TEGRA_210_SOC)
  119. static const struct tegra_fuse_info tegra210_fuse_info = {
  120. .read = tegra30_fuse_read,
  121. .size = 0x300,
  122. .spare = 0x280,
  123. };
  124. const struct tegra_fuse_soc tegra210_fuse_soc = {
  125. .init = tegra30_fuse_init,
  126. .speedo_init = tegra210_init_speedo_data,
  127. .info = &tegra210_fuse_info,
  128. };
  129. #endif
  130. #if defined(CONFIG_ARCH_TEGRA_186_SOC)
  131. static const struct tegra_fuse_info tegra186_fuse_info = {
  132. .read = tegra30_fuse_read,
  133. .size = 0x300,
  134. .spare = 0x280,
  135. };
  136. const struct tegra_fuse_soc tegra186_fuse_soc = {
  137. .init = tegra30_fuse_init,
  138. .info = &tegra186_fuse_info,
  139. };
  140. #endif