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exynos4-pmu.c

exynos4-pmu.c 9.6 KB
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  1. // SPDX-License-Identifier: GPL-2.0
    2. 

  2. //
    3. 

  3. // Copyright (c) 2011-2015 Samsung Electronics Co., Ltd.
    4. 

  4. //		http://www.samsung.com/
    5. 

  5. //
    6. 

  6. // EXYNOS4 - CPU PMU(Power Management Unit) support
    7. 

  7. 

  8. #include <linux/soc/samsung/exynos-regs-pmu.h>
    9. 

  9. #include <linux/soc/samsung/exynos-pmu.h>
    10. 

  10. 

  11. #include "exynos-pmu.h"
    12. 

  12. 

  13. static const struct exynos_pmu_conf exynos4210_pmu_config[] = {
    14. 

  14. 	/* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
    15. 

  15. 	{ S5P_ARM_CORE0_LOWPWR,			{ 0x0, 0x0, 0x2 } },
    16. 

  16. 	{ S5P_DIS_IRQ_CORE0,			{ 0x0, 0x0, 0x0 } },
    17. 

  17. 	{ S5P_DIS_IRQ_CENTRAL0,			{ 0x0, 0x0, 0x0 } },
    18. 

  18. 	{ S5P_ARM_CORE1_LOWPWR,			{ 0x0, 0x0, 0x2 } },
    19. 

  19. 	{ S5P_DIS_IRQ_CORE1,			{ 0x0, 0x0, 0x0 } },
    20. 

  20. 	{ S5P_DIS_IRQ_CENTRAL1,			{ 0x0, 0x0, 0x0 } },
    21. 

  21. 	{ S5P_ARM_COMMON_LOWPWR,		{ 0x0, 0x0, 0x2 } },
    22. 

  22. 	{ S5P_L2_0_LOWPWR,			{ 0x2, 0x2, 0x3 } },
    23. 

  23. 	{ S5P_L2_1_LOWPWR,			{ 0x2, 0x2, 0x3 } },
    24. 

  24. 	{ S5P_CMU_ACLKSTOP_LOWPWR,		{ 0x1, 0x0, 0x0 } },
    25. 

  25. 	{ S5P_CMU_SCLKSTOP_LOWPWR,		{ 0x1, 0x0, 0x0 } },
    26. 

  26. 	{ S5P_CMU_RESET_LOWPWR,			{ 0x1, 0x1, 0x0 } },
    27. 

  27. 	{ S5P_APLL_SYSCLK_LOWPWR,		{ 0x1, 0x0, 0x0 } },
    28. 

  28. 	{ S5P_MPLL_SYSCLK_LOWPWR,		{ 0x1, 0x0, 0x0 } },
    29. 

  29. 	{ S5P_VPLL_SYSCLK_LOWPWR,		{ 0x1, 0x0, 0x0 } },
    30. 

  30. 	{ S5P_EPLL_SYSCLK_LOWPWR,		{ 0x1, 0x1, 0x0 } },
    31. 

  31. 	{ S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR,	{ 0x1, 0x1, 0x0 } },
    32. 

  32. 	{ S5P_CMU_RESET_GPSALIVE_LOWPWR,	{ 0x1, 0x1, 0x0 } },
    33. 

  33. 	{ S5P_CMU_CLKSTOP_CAM_LOWPWR,		{ 0x1, 0x1, 0x0 } },
    34. 

  34. 	{ S5P_CMU_CLKSTOP_TV_LOWPWR,		{ 0x1, 0x1, 0x0 } },
    35. 

  35. 	{ S5P_CMU_CLKSTOP_MFC_LOWPWR,		{ 0x1, 0x1, 0x0 } },
    36. 

  36. 	{ S5P_CMU_CLKSTOP_G3D_LOWPWR,		{ 0x1, 0x1, 0x0 } },
    37. 

  37. 	{ S5P_CMU_CLKSTOP_LCD0_LOWPWR,		{ 0x1, 0x1, 0x0 } },
    38. 

  38. 	{ S5P_CMU_CLKSTOP_LCD1_LOWPWR,		{ 0x1, 0x1, 0x0 } },
    39. 

  39. 	{ S5P_CMU_CLKSTOP_MAUDIO_LOWPWR,	{ 0x1, 0x1, 0x0 } },
    40. 

  40. 	{ S5P_CMU_CLKSTOP_GPS_LOWPWR,		{ 0x1, 0x1, 0x0 } },
    41. 

  41. 	{ S5P_CMU_RESET_CAM_LOWPWR,		{ 0x1, 0x1, 0x0 } },
    42. 

  42. 	{ S5P_CMU_RESET_TV_LOWPWR,		{ 0x1, 0x1, 0x0 } },
    43. 

  43. 	{ S5P_CMU_RESET_MFC_LOWPWR,		{ 0x1, 0x1, 0x0 } },
    44. 

  44. 	{ S5P_CMU_RESET_G3D_LOWPWR,		{ 0x1, 0x1, 0x0 } },
    45. 

  45. 	{ S5P_CMU_RESET_LCD0_LOWPWR,		{ 0x1, 0x1, 0x0 } },
    46. 

  46. 	{ S5P_CMU_RESET_LCD1_LOWPWR,		{ 0x1, 0x1, 0x0 } },
    47. 

  47. 	{ S5P_CMU_RESET_MAUDIO_LOWPWR,		{ 0x1, 0x1, 0x0 } },
    48. 

  48. 	{ S5P_CMU_RESET_GPS_LOWPWR,		{ 0x1, 0x1, 0x0 } },
    49. 

  49. 	{ S5P_TOP_BUS_LOWPWR,			{ 0x3, 0x0, 0x0 } },
    50. 

  50. 	{ S5P_TOP_RETENTION_LOWPWR,		{ 0x1, 0x0, 0x1 } },
    51. 

  51. 	{ S5P_TOP_PWR_LOWPWR,			{ 0x3, 0x0, 0x3 } },
    52. 

  52. 	{ S5P_LOGIC_RESET_LOWPWR,		{ 0x1, 0x1, 0x0 } },
    53. 

  53. 	{ S5P_ONENAND_MEM_LOWPWR,		{ 0x3, 0x0, 0x0 } },
    54. 

  54. 	{ S5P_MODIMIF_MEM_LOWPWR,		{ 0x3, 0x0, 0x0 } },
    55. 

  55. 	{ S5P_G2D_ACP_MEM_LOWPWR,		{ 0x3, 0x0, 0x0 } },
    56. 

  56. 	{ S5P_USBOTG_MEM_LOWPWR,		{ 0x3, 0x0, 0x0 } },
    57. 

  57. 	{ S5P_HSMMC_MEM_LOWPWR,			{ 0x3, 0x0, 0x0 } },
    58. 

  58. 	{ S5P_CSSYS_MEM_LOWPWR,			{ 0x3, 0x0, 0x0 } },
    59. 

  59. 	{ S5P_SECSS_MEM_LOWPWR,			{ 0x3, 0x0, 0x0 } },
    60. 

  60. 	{ S5P_PCIE_MEM_LOWPWR,			{ 0x3, 0x0, 0x0 } },
    61. 

  61. 	{ S5P_SATA_MEM_LOWPWR,			{ 0x3, 0x0, 0x0 } },
    62. 

  62. 	{ S5P_PAD_RETENTION_DRAM_LOWPWR,	{ 0x1, 0x0, 0x0 } },
    63. 

  63. 	{ S5P_PAD_RETENTION_MAUDIO_LOWPWR,	{ 0x1, 0x1, 0x0 } },
    64. 

  64. 	{ S5P_PAD_RETENTION_GPIO_LOWPWR,	{ 0x1, 0x0, 0x0 } },
    65. 

  65. 	{ S5P_PAD_RETENTION_UART_LOWPWR,	{ 0x1, 0x0, 0x0 } },
    66. 

  66. 	{ S5P_PAD_RETENTION_MMCA_LOWPWR,	{ 0x1, 0x0, 0x0 } },
    67. 

  67. 	{ S5P_PAD_RETENTION_MMCB_LOWPWR,	{ 0x1, 0x0, 0x0 } },
    68. 

  68. 	{ S5P_PAD_RETENTION_EBIA_LOWPWR,	{ 0x1, 0x0, 0x0 } },
    69. 

  69. 	{ S5P_PAD_RETENTION_EBIB_LOWPWR,	{ 0x1, 0x0, 0x0 } },
    70. 

  70. 	{ S5P_PAD_RETENTION_ISOLATION_LOWPWR,	{ 0x1, 0x0, 0x0 } },
    71. 

  71. 	{ S5P_PAD_RETENTION_ALV_SEL_LOWPWR,	{ 0x1, 0x0, 0x0 } },
    72. 

  72. 	{ S5P_XUSBXTI_LOWPWR,			{ 0x1, 0x1, 0x0 } },
    73. 

  73. 	{ S5P_XXTI_LOWPWR,			{ 0x1, 0x1, 0x0 } },
    74. 

  74. 	{ S5P_EXT_REGULATOR_LOWPWR,		{ 0x1, 0x1, 0x0 } },
    75. 

  75. 	{ S5P_GPIO_MODE_LOWPWR,			{ 0x1, 0x0, 0x0 } },
    76. 

  76. 	{ S5P_GPIO_MODE_MAUDIO_LOWPWR,		{ 0x1, 0x1, 0x0 } },
    77. 

  77. 	{ S5P_CAM_LOWPWR,			{ 0x7, 0x0, 0x0 } },
    78. 

  78. 	{ S5P_TV_LOWPWR,			{ 0x7, 0x0, 0x0 } },
    79. 

  79. 	{ S5P_MFC_LOWPWR,			{ 0x7, 0x0, 0x0 } },
    80. 

  80. 	{ S5P_G3D_LOWPWR,			{ 0x7, 0x0, 0x0 } },
    81. 

  81. 	{ S5P_LCD0_LOWPWR,			{ 0x7, 0x0, 0x0 } },
    82. 

  82. 	{ S5P_LCD1_LOWPWR,			{ 0x7, 0x0, 0x0 } },
    83. 

  83. 	{ S5P_MAUDIO_LOWPWR,			{ 0x7, 0x7, 0x0 } },
    84. 

  84. 	{ S5P_GPS_LOWPWR,			{ 0x7, 0x0, 0x0 } },
    85. 

  85. 	{ S5P_GPS_ALIVE_LOWPWR,			{ 0x7, 0x0, 0x0 } },
    86. 

  86. 	{ PMU_TABLE_END,},
    87. 

  87. };
    88. 

  88. 

  89. static const struct exynos_pmu_conf exynos4412_pmu_config[] = {
    90. 

  90. 	{ S5P_ARM_CORE0_LOWPWR,			{ 0x0, 0x0, 0x2 } },
    91. 

  91. 	{ S5P_DIS_IRQ_CORE0,			{ 0x0, 0x0, 0x0 } },
    92. 

  92. 	{ S5P_DIS_IRQ_CENTRAL0,			{ 0x0, 0x0, 0x0 } },
    93. 

  93. 	{ S5P_ARM_CORE1_LOWPWR,			{ 0x0, 0x0, 0x2 } },
    94. 

  94. 	{ S5P_DIS_IRQ_CORE1,			{ 0x0, 0x0, 0x0 } },
    95. 

  95. 	{ S5P_DIS_IRQ_CENTRAL1,			{ 0x0, 0x0, 0x0 } },
    96. 

  96. 	{ S5P_ISP_ARM_LOWPWR,			{ 0x1, 0x0, 0x0 } },
    97. 

  97. 	{ S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR,	{ 0x0, 0x0, 0x0 } },
    98. 

  98. 	{ S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR,	{ 0x0, 0x0, 0x0 } },
    99. 

  99. 	{ S5P_ARM_COMMON_LOWPWR,		{ 0x0, 0x0, 0x2 } },
    100. 

  100. 	{ S5P_L2_0_LOWPWR,			{ 0x0, 0x0, 0x3 } },
    101. 

  101. 	/* XXX_OPTION register should be set other field */
    102. 

  102. 	{ S5P_ARM_L2_0_OPTION,			{ 0x10, 0x10, 0x0 } },
    103. 

  103. 	{ S5P_L2_1_LOWPWR,			{ 0x0, 0x0, 0x3 } },
    104. 

  104. 	{ S5P_ARM_L2_1_OPTION,			{ 0x10, 0x10, 0x0 } },
    105. 

  105. 	{ S5P_CMU_ACLKSTOP_LOWPWR,		{ 0x1, 0x0, 0x0 } },
    106. 

  106. 	{ S5P_CMU_SCLKSTOP_LOWPWR,		{ 0x1, 0x0, 0x0 } },
    107. 

  107. 	{ S5P_CMU_RESET_LOWPWR,			{ 0x1, 0x1, 0x0 } },
    108. 

  108. 	{ S5P_DRAM_FREQ_DOWN_LOWPWR,		{ 0x1, 0x1, 0x1 } },
    109. 

  109. 	{ S5P_DDRPHY_DLLOFF_LOWPWR,		{ 0x1, 0x1, 0x1 } },
    110. 

  110. 	{ S5P_LPDDR_PHY_DLL_LOCK_LOWPWR,	{ 0x1, 0x1, 0x1 } },
    111. 

  111. 	{ S5P_CMU_ACLKSTOP_COREBLK_LOWPWR,	{ 0x1, 0x0, 0x0 } },
    112. 

  112. 	{ S5P_CMU_SCLKSTOP_COREBLK_LOWPWR,	{ 0x1, 0x0, 0x0 } },
    113. 

  113. 	{ S5P_CMU_RESET_COREBLK_LOWPWR,		{ 0x1, 0x1, 0x0 } },
    114. 

  114. 	{ S5P_APLL_SYSCLK_LOWPWR,		{ 0x1, 0x0, 0x0 } },
    115. 

  115. 	{ S5P_MPLL_SYSCLK_LOWPWR,		{ 0x1, 0x0, 0x0 } },
    116. 

  116. 	{ S5P_VPLL_SYSCLK_LOWPWR,		{ 0x1, 0x0, 0x0 } },
    117. 

  117. 	{ S5P_EPLL_SYSCLK_LOWPWR,		{ 0x1, 0x1, 0x0 } },
    118. 

  118. 	{ S5P_MPLLUSER_SYSCLK_LOWPWR,		{ 0x1, 0x0, 0x0 } },
    119. 

  119. 	{ S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR,	{ 0x1, 0x0, 0x0 } },
    120. 

  120. 	{ S5P_CMU_RESET_GPSALIVE_LOWPWR,	{ 0x1, 0x0, 0x0 } },
    121. 

  121. 	{ S5P_CMU_CLKSTOP_CAM_LOWPWR,		{ 0x1, 0x0, 0x0 } },
    122. 

  122. 	{ S5P_CMU_CLKSTOP_TV_LOWPWR,		{ 0x1, 0x0, 0x0 } },
    123. 

  123. 	{ S5P_CMU_CLKSTOP_MFC_LOWPWR,		{ 0x1, 0x0, 0x0 } },
    124. 

  124. 	{ S5P_CMU_CLKSTOP_G3D_LOWPWR,		{ 0x1, 0x0, 0x0 } },
    125. 

  125. 	{ S5P_CMU_CLKSTOP_LCD0_LOWPWR,		{ 0x1, 0x0, 0x0 } },
    126. 

  126. 	{ S5P_CMU_CLKSTOP_ISP_LOWPWR,		{ 0x1, 0x0, 0x0 } },
    127. 

  127. 	{ S5P_CMU_CLKSTOP_MAUDIO_LOWPWR,	{ 0x1, 0x0, 0x0 } },
    128. 

  128. 	{ S5P_CMU_CLKSTOP_GPS_LOWPWR,		{ 0x1, 0x0, 0x0 } },
    129. 

  129. 	{ S5P_CMU_RESET_CAM_LOWPWR,		{ 0x1, 0x0, 0x0 } },
    130. 

  130. 	{ S5P_CMU_RESET_TV_LOWPWR,		{ 0x1, 0x0, 0x0 } },
    131. 

  131. 	{ S5P_CMU_RESET_MFC_LOWPWR,		{ 0x1, 0x0, 0x0 } },
    132. 

  132. 	{ S5P_CMU_RESET_G3D_LOWPWR,		{ 0x1, 0x0, 0x0 } },
    133. 

  133. 	{ S5P_CMU_RESET_LCD0_LOWPWR,		{ 0x1, 0x0, 0x0 } },
    134. 

  134. 	{ S5P_CMU_RESET_ISP_LOWPWR,		{ 0x1, 0x0, 0x0 } },
    135. 

  135. 	{ S5P_CMU_RESET_MAUDIO_LOWPWR,		{ 0x1, 0x1, 0x0 } },
    136. 

  136. 	{ S5P_CMU_RESET_GPS_LOWPWR,		{ 0x1, 0x0, 0x0 } },
    137. 

  137. 	{ S5P_TOP_BUS_LOWPWR,			{ 0x3, 0x0, 0x0 } },
    138. 

  138. 	{ S5P_TOP_RETENTION_LOWPWR,		{ 0x1, 0x0, 0x1 } },
    139. 

  139. 	{ S5P_TOP_PWR_LOWPWR,			{ 0x3, 0x0, 0x3 } },
    140. 

  140. 	{ S5P_TOP_BUS_COREBLK_LOWPWR,		{ 0x3, 0x0, 0x0 } },
    141. 

  141. 	{ S5P_TOP_RETENTION_COREBLK_LOWPWR,	{ 0x1, 0x0, 0x1 } },
    142. 

  142. 	{ S5P_TOP_PWR_COREBLK_LOWPWR,		{ 0x3, 0x0, 0x3 } },
    143. 

  143. 	{ S5P_LOGIC_RESET_LOWPWR,		{ 0x1, 0x1, 0x0 } },
    144. 

  144. 	{ S5P_OSCCLK_GATE_LOWPWR,		{ 0x1, 0x0, 0x1 } },
    145. 

  145. 	{ S5P_LOGIC_RESET_COREBLK_LOWPWR,	{ 0x1, 0x1, 0x0 } },
    146. 

  146. 	{ S5P_OSCCLK_GATE_COREBLK_LOWPWR,	{ 0x1, 0x0, 0x1 } },
    147. 

  147. 	{ S5P_ONENAND_MEM_LOWPWR,		{ 0x3, 0x0, 0x0 } },
    148. 

  148. 	{ S5P_ONENAND_MEM_OPTION,		{ 0x10, 0x10, 0x0 } },
    149. 

  149. 	{ S5P_HSI_MEM_LOWPWR,			{ 0x3, 0x0, 0x0 } },
    150. 

  150. 	{ S5P_HSI_MEM_OPTION,			{ 0x10, 0x10, 0x0 } },
    151. 

  151. 	{ S5P_G2D_ACP_MEM_LOWPWR,		{ 0x3, 0x0, 0x0 } },
    152. 

  152. 	{ S5P_G2D_ACP_MEM_OPTION,		{ 0x10, 0x10, 0x0 } },
    153. 

  153. 	{ S5P_USBOTG_MEM_LOWPWR,		{ 0x3, 0x0, 0x0 } },
    154. 

  154. 	{ S5P_USBOTG_MEM_OPTION,		{ 0x10, 0x10, 0x0 } },
    155. 

  155. 	{ S5P_HSMMC_MEM_LOWPWR,			{ 0x3, 0x0, 0x0 } },
    156. 

  156. 	{ S5P_HSMMC_MEM_OPTION,			{ 0x10, 0x10, 0x0 } },
    157. 

  157. 	{ S5P_CSSYS_MEM_LOWPWR,			{ 0x3, 0x0, 0x0 } },
    158. 

  158. 	{ S5P_CSSYS_MEM_OPTION,			{ 0x10, 0x10, 0x0 } },
    159. 

  159. 	{ S5P_SECSS_MEM_LOWPWR,			{ 0x3, 0x0, 0x0 } },
    160. 

  160. 	{ S5P_SECSS_MEM_OPTION,			{ 0x10, 0x10, 0x0 } },
    161. 

  161. 	{ S5P_ROTATOR_MEM_LOWPWR,		{ 0x3, 0x0, 0x0 } },
    162. 

  162. 	{ S5P_ROTATOR_MEM_OPTION,		{ 0x10, 0x10, 0x0 } },
    163. 

  163. 	{ S5P_PAD_RETENTION_DRAM_LOWPWR,	{ 0x1, 0x0, 0x0 } },
    164. 

  164. 	{ S5P_PAD_RETENTION_MAUDIO_LOWPWR,	{ 0x1, 0x1, 0x0 } },
    165. 

  165. 	{ S5P_PAD_RETENTION_GPIO_LOWPWR,	{ 0x1, 0x0, 0x0 } },
    166. 

  166. 	{ S5P_PAD_RETENTION_UART_LOWPWR,	{ 0x1, 0x0, 0x0 } },
    167. 

  167. 	{ S5P_PAD_RETENTION_MMCA_LOWPWR,	{ 0x1, 0x0, 0x0 } },
    168. 

  168. 	{ S5P_PAD_RETENTION_MMCB_LOWPWR,	{ 0x1, 0x0, 0x0 } },
    169. 

  169. 	{ S5P_PAD_RETENTION_EBIA_LOWPWR,	{ 0x1, 0x0, 0x0 } },
    170. 

  170. 	{ S5P_PAD_RETENTION_EBIB_LOWPWR,	{ 0x1, 0x0, 0x0 } },
    171. 

  171. 	{ S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } },
    172. 

  172. 	{ S5P_PAD_RETENTION_ISOLATION_LOWPWR,	{ 0x1, 0x0, 0x0 } },
    173. 

  173. 	{ S5P_PAD_ISOLATION_COREBLK_LOWPWR,	{ 0x1, 0x0, 0x0 } },
    174. 

  174. 	{ S5P_PAD_RETENTION_ALV_SEL_LOWPWR,	{ 0x1, 0x0, 0x0 } },
    175. 

  175. 	{ S5P_XUSBXTI_LOWPWR,			{ 0x1, 0x1, 0x0 } },
    176. 

  176. 	{ S5P_XXTI_LOWPWR,			{ 0x1, 0x1, 0x0 } },
    177. 

  177. 	{ S5P_EXT_REGULATOR_LOWPWR,		{ 0x1, 0x1, 0x0 } },
    178. 

  178. 	{ S5P_GPIO_MODE_LOWPWR,			{ 0x1, 0x0, 0x0 } },
    179. 

  179. 	{ S5P_GPIO_MODE_COREBLK_LOWPWR,		{ 0x1, 0x0, 0x0 } },
    180. 

  180. 	{ S5P_GPIO_MODE_MAUDIO_LOWPWR,		{ 0x1, 0x1, 0x0 } },
    181. 

  181. 	{ S5P_TOP_ASB_RESET_LOWPWR,		{ 0x1, 0x1, 0x1 } },
    182. 

  182. 	{ S5P_TOP_ASB_ISOLATION_LOWPWR,		{ 0x1, 0x0, 0x1 } },
    183. 

  183. 	{ S5P_CAM_LOWPWR,			{ 0x7, 0x0, 0x0 } },
    184. 

  184. 	{ S5P_TV_LOWPWR,			{ 0x7, 0x0, 0x0 } },
    185. 

  185. 	{ S5P_MFC_LOWPWR,			{ 0x7, 0x0, 0x0 } },
    186. 

  186. 	{ S5P_G3D_LOWPWR,			{ 0x7, 0x0, 0x0 } },
    187. 

  187. 	{ S5P_LCD0_LOWPWR,			{ 0x7, 0x0, 0x0 } },
    188. 

  188. 	{ S5P_ISP_LOWPWR,			{ 0x7, 0x0, 0x0 } },
    189. 

  189. 	{ S5P_MAUDIO_LOWPWR,			{ 0x7, 0x7, 0x0 } },
    190. 

  190. 	{ S5P_GPS_LOWPWR,			{ 0x7, 0x0, 0x0 } },
    191. 

  191. 	{ S5P_GPS_ALIVE_LOWPWR,			{ 0x7, 0x0, 0x0 } },
    192. 

  192. 	{ S5P_CMU_SYSCLK_ISP_LOWPWR,		{ 0x1, 0x0, 0x0 } },
    193. 

  193. 	{ S5P_CMU_SYSCLK_GPS_LOWPWR,		{ 0x1, 0x0, 0x0 } },
    194. 

  194. 	{ S5P_ARM_CORE2_LOWPWR,			{ 0x0, 0x0, 0x2 } },
    195. 

  195. 	{ S5P_DIS_IRQ_CORE2,			{ 0x0, 0x0, 0x0 } },
    196. 

  196. 	{ S5P_DIS_IRQ_CENTRAL2,			{ 0x0, 0x0, 0x0 } },
    197. 

  197. 	{ S5P_ARM_CORE3_LOWPWR,			{ 0x0, 0x0, 0x2 } },
    198. 

  198. 	{ S5P_DIS_IRQ_CORE3,			{ 0x0, 0x0, 0x0 } },
    199. 

  199. 	{ S5P_DIS_IRQ_CENTRAL3,			{ 0x0, 0x0, 0x0 } },
    200. 

  200. 	{ PMU_TABLE_END,},
    201. 

  201. };
    202. 

  202. 

  203. const struct exynos_pmu_data exynos4210_pmu_data = {
    204. 

  204. 	.pmu_config	= exynos4210_pmu_config,
    205. 

  205. };
    206. 

  206. 

  207. const struct exynos_pmu_data exynos4412_pmu_data = {
    208. 

  208. 	.pmu_config		= exynos4412_pmu_config,
    209. 

  209. };
    210. 

  210.