qcom_aoss.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2019, Linaro Ltd
  4. */
  5. #include <dt-bindings/power/qcom-aoss-qmp.h>
  6. #include <linux/clk-provider.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/io.h>
  9. #include <linux/mailbox_client.h>
  10. #include <linux/module.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/pm_domain.h>
  13. #include <linux/thermal.h>
  14. #include <linux/slab.h>
  15. #define QMP_DESC_MAGIC 0x0
  16. #define QMP_DESC_VERSION 0x4
  17. #define QMP_DESC_FEATURES 0x8
  18. /* AOP-side offsets */
  19. #define QMP_DESC_UCORE_LINK_STATE 0xc
  20. #define QMP_DESC_UCORE_LINK_STATE_ACK 0x10
  21. #define QMP_DESC_UCORE_CH_STATE 0x14
  22. #define QMP_DESC_UCORE_CH_STATE_ACK 0x18
  23. #define QMP_DESC_UCORE_MBOX_SIZE 0x1c
  24. #define QMP_DESC_UCORE_MBOX_OFFSET 0x20
  25. /* Linux-side offsets */
  26. #define QMP_DESC_MCORE_LINK_STATE 0x24
  27. #define QMP_DESC_MCORE_LINK_STATE_ACK 0x28
  28. #define QMP_DESC_MCORE_CH_STATE 0x2c
  29. #define QMP_DESC_MCORE_CH_STATE_ACK 0x30
  30. #define QMP_DESC_MCORE_MBOX_SIZE 0x34
  31. #define QMP_DESC_MCORE_MBOX_OFFSET 0x38
  32. #define QMP_STATE_UP GENMASK(15, 0)
  33. #define QMP_STATE_DOWN GENMASK(31, 16)
  34. #define QMP_MAGIC 0x4d41494c /* mail */
  35. #define QMP_VERSION 1
  36. /* 64 bytes is enough to store the requests and provides padding to 4 bytes */
  37. #define QMP_MSG_LEN 64
  38. #define QMP_NUM_COOLING_RESOURCES 2
  39. static bool qmp_cdev_init_state = 1;
  40. struct qmp_cooling_device {
  41. struct thermal_cooling_device *cdev;
  42. struct qmp *qmp;
  43. char *name;
  44. bool state;
  45. };
  46. /**
  47. * struct qmp - driver state for QMP implementation
  48. * @msgram: iomem referencing the message RAM used for communication
  49. * @dev: reference to QMP device
  50. * @mbox_client: mailbox client used to ring the doorbell on transmit
  51. * @mbox_chan: mailbox channel used to ring the doorbell on transmit
  52. * @offset: offset within @msgram where messages should be written
  53. * @size: maximum size of the messages to be transmitted
  54. * @event: wait_queue for synchronization with the IRQ
  55. * @tx_lock: provides synchronization between multiple callers of qmp_send()
  56. * @qdss_clk: QDSS clock hw struct
  57. * @pd_data: genpd data
  58. */
  59. struct qmp {
  60. void __iomem *msgram;
  61. struct device *dev;
  62. struct mbox_client mbox_client;
  63. struct mbox_chan *mbox_chan;
  64. size_t offset;
  65. size_t size;
  66. wait_queue_head_t event;
  67. struct mutex tx_lock;
  68. struct clk_hw qdss_clk;
  69. struct genpd_onecell_data pd_data;
  70. struct qmp_cooling_device *cooling_devs;
  71. };
  72. struct qmp_pd {
  73. struct qmp *qmp;
  74. struct generic_pm_domain pd;
  75. };
  76. #define to_qmp_pd_resource(res) container_of(res, struct qmp_pd, pd)
  77. static void qmp_kick(struct qmp *qmp)
  78. {
  79. mbox_send_message(qmp->mbox_chan, NULL);
  80. mbox_client_txdone(qmp->mbox_chan, 0);
  81. }
  82. static bool qmp_magic_valid(struct qmp *qmp)
  83. {
  84. return readl(qmp->msgram + QMP_DESC_MAGIC) == QMP_MAGIC;
  85. }
  86. static bool qmp_link_acked(struct qmp *qmp)
  87. {
  88. return readl(qmp->msgram + QMP_DESC_MCORE_LINK_STATE_ACK) == QMP_STATE_UP;
  89. }
  90. static bool qmp_mcore_channel_acked(struct qmp *qmp)
  91. {
  92. return readl(qmp->msgram + QMP_DESC_MCORE_CH_STATE_ACK) == QMP_STATE_UP;
  93. }
  94. static bool qmp_ucore_channel_up(struct qmp *qmp)
  95. {
  96. return readl(qmp->msgram + QMP_DESC_UCORE_CH_STATE) == QMP_STATE_UP;
  97. }
  98. static int qmp_open(struct qmp *qmp)
  99. {
  100. int ret;
  101. u32 val;
  102. if (!qmp_magic_valid(qmp)) {
  103. dev_err(qmp->dev, "QMP magic doesn't match\n");
  104. return -EINVAL;
  105. }
  106. val = readl(qmp->msgram + QMP_DESC_VERSION);
  107. if (val != QMP_VERSION) {
  108. dev_err(qmp->dev, "unsupported QMP version %d\n", val);
  109. return -EINVAL;
  110. }
  111. qmp->offset = readl(qmp->msgram + QMP_DESC_MCORE_MBOX_OFFSET);
  112. qmp->size = readl(qmp->msgram + QMP_DESC_MCORE_MBOX_SIZE);
  113. if (!qmp->size) {
  114. dev_err(qmp->dev, "invalid mailbox size\n");
  115. return -EINVAL;
  116. }
  117. /* Ack remote core's link state */
  118. val = readl(qmp->msgram + QMP_DESC_UCORE_LINK_STATE);
  119. writel(val, qmp->msgram + QMP_DESC_UCORE_LINK_STATE_ACK);
  120. /* Set local core's link state to up */
  121. writel(QMP_STATE_UP, qmp->msgram + QMP_DESC_MCORE_LINK_STATE);
  122. qmp_kick(qmp);
  123. ret = wait_event_timeout(qmp->event, qmp_link_acked(qmp), HZ);
  124. if (!ret) {
  125. dev_err(qmp->dev, "ucore didn't ack link\n");
  126. goto timeout_close_link;
  127. }
  128. writel(QMP_STATE_UP, qmp->msgram + QMP_DESC_MCORE_CH_STATE);
  129. qmp_kick(qmp);
  130. ret = wait_event_timeout(qmp->event, qmp_ucore_channel_up(qmp), HZ);
  131. if (!ret) {
  132. dev_err(qmp->dev, "ucore didn't open channel\n");
  133. goto timeout_close_channel;
  134. }
  135. /* Ack remote core's channel state */
  136. writel(QMP_STATE_UP, qmp->msgram + QMP_DESC_UCORE_CH_STATE_ACK);
  137. qmp_kick(qmp);
  138. ret = wait_event_timeout(qmp->event, qmp_mcore_channel_acked(qmp), HZ);
  139. if (!ret) {
  140. dev_err(qmp->dev, "ucore didn't ack channel\n");
  141. goto timeout_close_channel;
  142. }
  143. return 0;
  144. timeout_close_channel:
  145. writel(QMP_STATE_DOWN, qmp->msgram + QMP_DESC_MCORE_CH_STATE);
  146. timeout_close_link:
  147. writel(QMP_STATE_DOWN, qmp->msgram + QMP_DESC_MCORE_LINK_STATE);
  148. qmp_kick(qmp);
  149. return -ETIMEDOUT;
  150. }
  151. static void qmp_close(struct qmp *qmp)
  152. {
  153. writel(QMP_STATE_DOWN, qmp->msgram + QMP_DESC_MCORE_CH_STATE);
  154. writel(QMP_STATE_DOWN, qmp->msgram + QMP_DESC_MCORE_LINK_STATE);
  155. qmp_kick(qmp);
  156. }
  157. static irqreturn_t qmp_intr(int irq, void *data)
  158. {
  159. struct qmp *qmp = data;
  160. wake_up_interruptible_all(&qmp->event);
  161. return IRQ_HANDLED;
  162. }
  163. static bool qmp_message_empty(struct qmp *qmp)
  164. {
  165. return readl(qmp->msgram + qmp->offset) == 0;
  166. }
  167. /**
  168. * qmp_send() - send a message to the AOSS
  169. * @qmp: qmp context
  170. * @data: message to be sent
  171. * @len: length of the message
  172. *
  173. * Transmit @data to AOSS and wait for the AOSS to acknowledge the message.
  174. * @len must be a multiple of 4 and not longer than the mailbox size. Access is
  175. * synchronized by this implementation.
  176. *
  177. * Return: 0 on success, negative errno on failure
  178. */
  179. static int qmp_send(struct qmp *qmp, const void *data, size_t len)
  180. {
  181. long time_left;
  182. int ret;
  183. if (WARN_ON(len + sizeof(u32) > qmp->size))
  184. return -EINVAL;
  185. if (WARN_ON(len % sizeof(u32)))
  186. return -EINVAL;
  187. mutex_lock(&qmp->tx_lock);
  188. /* The message RAM only implements 32-bit accesses */
  189. __iowrite32_copy(qmp->msgram + qmp->offset + sizeof(u32),
  190. data, len / sizeof(u32));
  191. writel(len, qmp->msgram + qmp->offset);
  192. qmp_kick(qmp);
  193. time_left = wait_event_interruptible_timeout(qmp->event,
  194. qmp_message_empty(qmp), HZ);
  195. if (!time_left) {
  196. dev_err(qmp->dev, "ucore did not ack channel\n");
  197. ret = -ETIMEDOUT;
  198. /* Clear message from buffer */
  199. writel(0, qmp->msgram + qmp->offset);
  200. } else {
  201. ret = 0;
  202. }
  203. mutex_unlock(&qmp->tx_lock);
  204. return ret;
  205. }
  206. static int qmp_qdss_clk_prepare(struct clk_hw *hw)
  207. {
  208. static const char buf[QMP_MSG_LEN] = "{class: clock, res: qdss, val: 1}";
  209. struct qmp *qmp = container_of(hw, struct qmp, qdss_clk);
  210. return qmp_send(qmp, buf, sizeof(buf));
  211. }
  212. static void qmp_qdss_clk_unprepare(struct clk_hw *hw)
  213. {
  214. static const char buf[QMP_MSG_LEN] = "{class: clock, res: qdss, val: 0}";
  215. struct qmp *qmp = container_of(hw, struct qmp, qdss_clk);
  216. qmp_send(qmp, buf, sizeof(buf));
  217. }
  218. static const struct clk_ops qmp_qdss_clk_ops = {
  219. .prepare = qmp_qdss_clk_prepare,
  220. .unprepare = qmp_qdss_clk_unprepare,
  221. };
  222. static int qmp_qdss_clk_add(struct qmp *qmp)
  223. {
  224. static const struct clk_init_data qdss_init = {
  225. .ops = &qmp_qdss_clk_ops,
  226. .name = "qdss",
  227. };
  228. int ret;
  229. qmp->qdss_clk.init = &qdss_init;
  230. ret = clk_hw_register(qmp->dev, &qmp->qdss_clk);
  231. if (ret < 0) {
  232. dev_err(qmp->dev, "failed to register qdss clock\n");
  233. return ret;
  234. }
  235. ret = of_clk_add_hw_provider(qmp->dev->of_node, of_clk_hw_simple_get,
  236. &qmp->qdss_clk);
  237. if (ret < 0) {
  238. dev_err(qmp->dev, "unable to register of clk hw provider\n");
  239. clk_hw_unregister(&qmp->qdss_clk);
  240. }
  241. return ret;
  242. }
  243. static void qmp_qdss_clk_remove(struct qmp *qmp)
  244. {
  245. of_clk_del_provider(qmp->dev->of_node);
  246. clk_hw_unregister(&qmp->qdss_clk);
  247. }
  248. static int qmp_pd_power_toggle(struct qmp_pd *res, bool enable)
  249. {
  250. char buf[QMP_MSG_LEN] = {};
  251. snprintf(buf, sizeof(buf),
  252. "{class: image, res: load_state, name: %s, val: %s}",
  253. res->pd.name, enable ? "on" : "off");
  254. return qmp_send(res->qmp, buf, sizeof(buf));
  255. }
  256. static int qmp_pd_power_on(struct generic_pm_domain *domain)
  257. {
  258. return qmp_pd_power_toggle(to_qmp_pd_resource(domain), true);
  259. }
  260. static int qmp_pd_power_off(struct generic_pm_domain *domain)
  261. {
  262. return qmp_pd_power_toggle(to_qmp_pd_resource(domain), false);
  263. }
  264. static const char * const sdm845_resources[] = {
  265. [AOSS_QMP_LS_CDSP] = "cdsp",
  266. [AOSS_QMP_LS_LPASS] = "adsp",
  267. [AOSS_QMP_LS_MODEM] = "modem",
  268. [AOSS_QMP_LS_SLPI] = "slpi",
  269. [AOSS_QMP_LS_SPSS] = "spss",
  270. [AOSS_QMP_LS_VENUS] = "venus",
  271. };
  272. static int qmp_pd_add(struct qmp *qmp)
  273. {
  274. struct genpd_onecell_data *data = &qmp->pd_data;
  275. struct device *dev = qmp->dev;
  276. struct qmp_pd *res;
  277. size_t num = ARRAY_SIZE(sdm845_resources);
  278. int ret;
  279. int i;
  280. res = devm_kcalloc(dev, num, sizeof(*res), GFP_KERNEL);
  281. if (!res)
  282. return -ENOMEM;
  283. data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
  284. GFP_KERNEL);
  285. if (!data->domains)
  286. return -ENOMEM;
  287. for (i = 0; i < num; i++) {
  288. res[i].qmp = qmp;
  289. res[i].pd.name = sdm845_resources[i];
  290. res[i].pd.power_on = qmp_pd_power_on;
  291. res[i].pd.power_off = qmp_pd_power_off;
  292. ret = pm_genpd_init(&res[i].pd, NULL, true);
  293. if (ret < 0) {
  294. dev_err(dev, "failed to init genpd\n");
  295. goto unroll_genpds;
  296. }
  297. data->domains[i] = &res[i].pd;
  298. }
  299. data->num_domains = i;
  300. ret = of_genpd_add_provider_onecell(dev->of_node, data);
  301. if (ret < 0)
  302. goto unroll_genpds;
  303. return 0;
  304. unroll_genpds:
  305. for (i--; i >= 0; i--)
  306. pm_genpd_remove(data->domains[i]);
  307. return ret;
  308. }
  309. static void qmp_pd_remove(struct qmp *qmp)
  310. {
  311. struct genpd_onecell_data *data = &qmp->pd_data;
  312. struct device *dev = qmp->dev;
  313. int i;
  314. of_genpd_del_provider(dev->of_node);
  315. for (i = 0; i < data->num_domains; i++)
  316. pm_genpd_remove(data->domains[i]);
  317. }
  318. static int qmp_cdev_get_max_state(struct thermal_cooling_device *cdev,
  319. unsigned long *state)
  320. {
  321. *state = qmp_cdev_init_state;
  322. return 0;
  323. }
  324. static int qmp_cdev_get_cur_state(struct thermal_cooling_device *cdev,
  325. unsigned long *state)
  326. {
  327. struct qmp_cooling_device *qmp_cdev = cdev->devdata;
  328. *state = qmp_cdev->state;
  329. return 0;
  330. }
  331. static int qmp_cdev_set_cur_state(struct thermal_cooling_device *cdev,
  332. unsigned long state)
  333. {
  334. struct qmp_cooling_device *qmp_cdev = cdev->devdata;
  335. char buf[QMP_MSG_LEN] = {};
  336. bool cdev_state;
  337. int ret;
  338. /* Normalize state */
  339. cdev_state = !!state;
  340. if (qmp_cdev->state == state)
  341. return 0;
  342. snprintf(buf, sizeof(buf),
  343. "{class: volt_flr, event:zero_temp, res:%s, value:%s}",
  344. qmp_cdev->name,
  345. cdev_state ? "off" : "on");
  346. ret = qmp_send(qmp_cdev->qmp, buf, sizeof(buf));
  347. if (!ret)
  348. qmp_cdev->state = cdev_state;
  349. return ret;
  350. }
  351. static struct thermal_cooling_device_ops qmp_cooling_device_ops = {
  352. .get_max_state = qmp_cdev_get_max_state,
  353. .get_cur_state = qmp_cdev_get_cur_state,
  354. .set_cur_state = qmp_cdev_set_cur_state,
  355. };
  356. static int qmp_cooling_device_add(struct qmp *qmp,
  357. struct qmp_cooling_device *qmp_cdev,
  358. struct device_node *node)
  359. {
  360. char *cdev_name = (char *)node->name;
  361. qmp_cdev->qmp = qmp;
  362. qmp_cdev->state = qmp_cdev_init_state;
  363. qmp_cdev->name = cdev_name;
  364. qmp_cdev->cdev = devm_thermal_of_cooling_device_register
  365. (qmp->dev, node,
  366. cdev_name,
  367. qmp_cdev, &qmp_cooling_device_ops);
  368. if (IS_ERR(qmp_cdev->cdev))
  369. dev_err(qmp->dev, "unable to register %s cooling device\n",
  370. cdev_name);
  371. return PTR_ERR_OR_ZERO(qmp_cdev->cdev);
  372. }
  373. static int qmp_cooling_devices_register(struct qmp *qmp)
  374. {
  375. struct device_node *np, *child;
  376. int count = 0;
  377. int ret;
  378. np = qmp->dev->of_node;
  379. qmp->cooling_devs = devm_kcalloc(qmp->dev, QMP_NUM_COOLING_RESOURCES,
  380. sizeof(*qmp->cooling_devs),
  381. GFP_KERNEL);
  382. if (!qmp->cooling_devs)
  383. return -ENOMEM;
  384. for_each_available_child_of_node(np, child) {
  385. if (!of_find_property(child, "#cooling-cells", NULL))
  386. continue;
  387. ret = qmp_cooling_device_add(qmp, &qmp->cooling_devs[count++],
  388. child);
  389. if (ret)
  390. goto unroll;
  391. }
  392. if (!count)
  393. devm_kfree(qmp->dev, qmp->cooling_devs);
  394. return 0;
  395. unroll:
  396. while (--count >= 0)
  397. thermal_cooling_device_unregister
  398. (qmp->cooling_devs[count].cdev);
  399. devm_kfree(qmp->dev, qmp->cooling_devs);
  400. return ret;
  401. }
  402. static void qmp_cooling_devices_remove(struct qmp *qmp)
  403. {
  404. int i;
  405. for (i = 0; i < QMP_NUM_COOLING_RESOURCES; i++)
  406. thermal_cooling_device_unregister(qmp->cooling_devs[i].cdev);
  407. }
  408. static int qmp_probe(struct platform_device *pdev)
  409. {
  410. struct resource *res;
  411. struct qmp *qmp;
  412. int irq;
  413. int ret;
  414. qmp = devm_kzalloc(&pdev->dev, sizeof(*qmp), GFP_KERNEL);
  415. if (!qmp)
  416. return -ENOMEM;
  417. qmp->dev = &pdev->dev;
  418. init_waitqueue_head(&qmp->event);
  419. mutex_init(&qmp->tx_lock);
  420. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  421. qmp->msgram = devm_ioremap_resource(&pdev->dev, res);
  422. if (IS_ERR(qmp->msgram))
  423. return PTR_ERR(qmp->msgram);
  424. qmp->mbox_client.dev = &pdev->dev;
  425. qmp->mbox_client.knows_txdone = true;
  426. qmp->mbox_chan = mbox_request_channel(&qmp->mbox_client, 0);
  427. if (IS_ERR(qmp->mbox_chan)) {
  428. dev_err(&pdev->dev, "failed to acquire ipc mailbox\n");
  429. return PTR_ERR(qmp->mbox_chan);
  430. }
  431. irq = platform_get_irq(pdev, 0);
  432. ret = devm_request_irq(&pdev->dev, irq, qmp_intr, IRQF_ONESHOT,
  433. "aoss-qmp", qmp);
  434. if (ret < 0) {
  435. dev_err(&pdev->dev, "failed to request interrupt\n");
  436. goto err_free_mbox;
  437. }
  438. ret = qmp_open(qmp);
  439. if (ret < 0)
  440. goto err_free_mbox;
  441. ret = qmp_qdss_clk_add(qmp);
  442. if (ret)
  443. goto err_close_qmp;
  444. ret = qmp_pd_add(qmp);
  445. if (ret)
  446. goto err_remove_qdss_clk;
  447. ret = qmp_cooling_devices_register(qmp);
  448. if (ret)
  449. dev_err(&pdev->dev, "failed to register aoss cooling devices\n");
  450. platform_set_drvdata(pdev, qmp);
  451. return 0;
  452. err_remove_qdss_clk:
  453. qmp_qdss_clk_remove(qmp);
  454. err_close_qmp:
  455. qmp_close(qmp);
  456. err_free_mbox:
  457. mbox_free_channel(qmp->mbox_chan);
  458. return ret;
  459. }
  460. static int qmp_remove(struct platform_device *pdev)
  461. {
  462. struct qmp *qmp = platform_get_drvdata(pdev);
  463. qmp_qdss_clk_remove(qmp);
  464. qmp_pd_remove(qmp);
  465. qmp_cooling_devices_remove(qmp);
  466. qmp_close(qmp);
  467. mbox_free_channel(qmp->mbox_chan);
  468. return 0;
  469. }
  470. static const struct of_device_id qmp_dt_match[] = {
  471. { .compatible = "qcom,sc7180-aoss-qmp", },
  472. { .compatible = "qcom,sdm845-aoss-qmp", },
  473. { .compatible = "qcom,sm8150-aoss-qmp", },
  474. {}
  475. };
  476. MODULE_DEVICE_TABLE(of, qmp_dt_match);
  477. static struct platform_driver qmp_driver = {
  478. .driver = {
  479. .name = "qcom_aoss_qmp",
  480. .of_match_table = qmp_dt_match,
  481. },
  482. .probe = qmp_probe,
  483. .remove = qmp_remove,
  484. };
  485. module_platform_driver(qmp_driver);
  486. MODULE_DESCRIPTION("Qualcomm AOSS QMP driver");
  487. MODULE_LICENSE("GPL v2");