pmu.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Marvell Dove PMU support
  4. */
  5. #include <linux/io.h>
  6. #include <linux/irq.h>
  7. #include <linux/irqdomain.h>
  8. #include <linux/of.h>
  9. #include <linux/of_irq.h>
  10. #include <linux/of_address.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/pm_domain.h>
  13. #include <linux/reset.h>
  14. #include <linux/reset-controller.h>
  15. #include <linux/sched.h>
  16. #include <linux/slab.h>
  17. #include <linux/soc/dove/pmu.h>
  18. #include <linux/spinlock.h>
  19. #define NR_PMU_IRQS 7
  20. #define PMC_SW_RST 0x30
  21. #define PMC_IRQ_CAUSE 0x50
  22. #define PMC_IRQ_MASK 0x54
  23. #define PMU_PWR 0x10
  24. #define PMU_ISO 0x58
  25. struct pmu_data {
  26. spinlock_t lock;
  27. struct device_node *of_node;
  28. void __iomem *pmc_base;
  29. void __iomem *pmu_base;
  30. struct irq_chip_generic *irq_gc;
  31. struct irq_domain *irq_domain;
  32. #ifdef CONFIG_RESET_CONTROLLER
  33. struct reset_controller_dev reset;
  34. #endif
  35. };
  36. /*
  37. * The PMU contains a register to reset various subsystems within the
  38. * SoC. Export this as a reset controller.
  39. */
  40. #ifdef CONFIG_RESET_CONTROLLER
  41. #define rcdev_to_pmu(rcdev) container_of(rcdev, struct pmu_data, reset)
  42. static int pmu_reset_reset(struct reset_controller_dev *rc, unsigned long id)
  43. {
  44. struct pmu_data *pmu = rcdev_to_pmu(rc);
  45. unsigned long flags;
  46. u32 val;
  47. spin_lock_irqsave(&pmu->lock, flags);
  48. val = readl_relaxed(pmu->pmc_base + PMC_SW_RST);
  49. writel_relaxed(val & ~BIT(id), pmu->pmc_base + PMC_SW_RST);
  50. writel_relaxed(val | BIT(id), pmu->pmc_base + PMC_SW_RST);
  51. spin_unlock_irqrestore(&pmu->lock, flags);
  52. return 0;
  53. }
  54. static int pmu_reset_assert(struct reset_controller_dev *rc, unsigned long id)
  55. {
  56. struct pmu_data *pmu = rcdev_to_pmu(rc);
  57. unsigned long flags;
  58. u32 val = ~BIT(id);
  59. spin_lock_irqsave(&pmu->lock, flags);
  60. val &= readl_relaxed(pmu->pmc_base + PMC_SW_RST);
  61. writel_relaxed(val, pmu->pmc_base + PMC_SW_RST);
  62. spin_unlock_irqrestore(&pmu->lock, flags);
  63. return 0;
  64. }
  65. static int pmu_reset_deassert(struct reset_controller_dev *rc, unsigned long id)
  66. {
  67. struct pmu_data *pmu = rcdev_to_pmu(rc);
  68. unsigned long flags;
  69. u32 val = BIT(id);
  70. spin_lock_irqsave(&pmu->lock, flags);
  71. val |= readl_relaxed(pmu->pmc_base + PMC_SW_RST);
  72. writel_relaxed(val, pmu->pmc_base + PMC_SW_RST);
  73. spin_unlock_irqrestore(&pmu->lock, flags);
  74. return 0;
  75. }
  76. static const struct reset_control_ops pmu_reset_ops = {
  77. .reset = pmu_reset_reset,
  78. .assert = pmu_reset_assert,
  79. .deassert = pmu_reset_deassert,
  80. };
  81. static struct reset_controller_dev pmu_reset __initdata = {
  82. .ops = &pmu_reset_ops,
  83. .owner = THIS_MODULE,
  84. .nr_resets = 32,
  85. };
  86. static void __init pmu_reset_init(struct pmu_data *pmu)
  87. {
  88. int ret;
  89. pmu->reset = pmu_reset;
  90. pmu->reset.of_node = pmu->of_node;
  91. ret = reset_controller_register(&pmu->reset);
  92. if (ret)
  93. pr_err("pmu: %s failed: %d\n", "reset_controller_register", ret);
  94. }
  95. #else
  96. static void __init pmu_reset_init(struct pmu_data *pmu)
  97. {
  98. }
  99. #endif
  100. struct pmu_domain {
  101. struct pmu_data *pmu;
  102. u32 pwr_mask;
  103. u32 rst_mask;
  104. u32 iso_mask;
  105. struct generic_pm_domain base;
  106. };
  107. #define to_pmu_domain(dom) container_of(dom, struct pmu_domain, base)
  108. /*
  109. * This deals with the "old" Marvell sequence of bringing a power domain
  110. * down/up, which is: apply power, release reset, disable isolators.
  111. *
  112. * Later devices apparantly use a different sequence: power up, disable
  113. * isolators, assert repair signal, enable SRMA clock, enable AXI clock,
  114. * enable module clock, deassert reset.
  115. *
  116. * Note: reading the assembly, it seems that the IO accessors have an
  117. * unfortunate side-effect - they cause memory already read into registers
  118. * for the if () to be re-read for the bit-set or bit-clear operation.
  119. * The code is written to avoid this.
  120. */
  121. static int pmu_domain_power_off(struct generic_pm_domain *domain)
  122. {
  123. struct pmu_domain *pmu_dom = to_pmu_domain(domain);
  124. struct pmu_data *pmu = pmu_dom->pmu;
  125. unsigned long flags;
  126. unsigned int val;
  127. void __iomem *pmu_base = pmu->pmu_base;
  128. void __iomem *pmc_base = pmu->pmc_base;
  129. spin_lock_irqsave(&pmu->lock, flags);
  130. /* Enable isolators */
  131. if (pmu_dom->iso_mask) {
  132. val = ~pmu_dom->iso_mask;
  133. val &= readl_relaxed(pmu_base + PMU_ISO);
  134. writel_relaxed(val, pmu_base + PMU_ISO);
  135. }
  136. /* Reset unit */
  137. if (pmu_dom->rst_mask) {
  138. val = ~pmu_dom->rst_mask;
  139. val &= readl_relaxed(pmc_base + PMC_SW_RST);
  140. writel_relaxed(val, pmc_base + PMC_SW_RST);
  141. }
  142. /* Power down */
  143. val = readl_relaxed(pmu_base + PMU_PWR) | pmu_dom->pwr_mask;
  144. writel_relaxed(val, pmu_base + PMU_PWR);
  145. spin_unlock_irqrestore(&pmu->lock, flags);
  146. return 0;
  147. }
  148. static int pmu_domain_power_on(struct generic_pm_domain *domain)
  149. {
  150. struct pmu_domain *pmu_dom = to_pmu_domain(domain);
  151. struct pmu_data *pmu = pmu_dom->pmu;
  152. unsigned long flags;
  153. unsigned int val;
  154. void __iomem *pmu_base = pmu->pmu_base;
  155. void __iomem *pmc_base = pmu->pmc_base;
  156. spin_lock_irqsave(&pmu->lock, flags);
  157. /* Power on */
  158. val = ~pmu_dom->pwr_mask & readl_relaxed(pmu_base + PMU_PWR);
  159. writel_relaxed(val, pmu_base + PMU_PWR);
  160. /* Release reset */
  161. if (pmu_dom->rst_mask) {
  162. val = pmu_dom->rst_mask;
  163. val |= readl_relaxed(pmc_base + PMC_SW_RST);
  164. writel_relaxed(val, pmc_base + PMC_SW_RST);
  165. }
  166. /* Disable isolators */
  167. if (pmu_dom->iso_mask) {
  168. val = pmu_dom->iso_mask;
  169. val |= readl_relaxed(pmu_base + PMU_ISO);
  170. writel_relaxed(val, pmu_base + PMU_ISO);
  171. }
  172. spin_unlock_irqrestore(&pmu->lock, flags);
  173. return 0;
  174. }
  175. static void __pmu_domain_register(struct pmu_domain *domain,
  176. struct device_node *np)
  177. {
  178. unsigned int val = readl_relaxed(domain->pmu->pmu_base + PMU_PWR);
  179. domain->base.power_off = pmu_domain_power_off;
  180. domain->base.power_on = pmu_domain_power_on;
  181. pm_genpd_init(&domain->base, NULL, !(val & domain->pwr_mask));
  182. if (np)
  183. of_genpd_add_provider_simple(np, &domain->base);
  184. }
  185. /* PMU IRQ controller */
  186. static void pmu_irq_handler(struct irq_desc *desc)
  187. {
  188. struct pmu_data *pmu = irq_desc_get_handler_data(desc);
  189. struct irq_chip_generic *gc = pmu->irq_gc;
  190. struct irq_domain *domain = pmu->irq_domain;
  191. void __iomem *base = gc->reg_base;
  192. u32 stat = readl_relaxed(base + PMC_IRQ_CAUSE) & gc->mask_cache;
  193. u32 done = ~0;
  194. if (stat == 0) {
  195. handle_bad_irq(desc);
  196. return;
  197. }
  198. while (stat) {
  199. u32 hwirq = fls(stat) - 1;
  200. stat &= ~(1 << hwirq);
  201. done &= ~(1 << hwirq);
  202. generic_handle_irq(irq_find_mapping(domain, hwirq));
  203. }
  204. /*
  205. * The PMU mask register is not RW0C: it is RW. This means that
  206. * the bits take whatever value is written to them; if you write
  207. * a '1', you will set the interrupt.
  208. *
  209. * Unfortunately this means there is NO race free way to clear
  210. * these interrupts.
  211. *
  212. * So, let's structure the code so that the window is as small as
  213. * possible.
  214. */
  215. irq_gc_lock(gc);
  216. done &= readl_relaxed(base + PMC_IRQ_CAUSE);
  217. writel_relaxed(done, base + PMC_IRQ_CAUSE);
  218. irq_gc_unlock(gc);
  219. }
  220. static int __init dove_init_pmu_irq(struct pmu_data *pmu, int irq)
  221. {
  222. const char *name = "pmu_irq";
  223. struct irq_chip_generic *gc;
  224. struct irq_domain *domain;
  225. int ret;
  226. /* mask and clear all interrupts */
  227. writel(0, pmu->pmc_base + PMC_IRQ_MASK);
  228. writel(0, pmu->pmc_base + PMC_IRQ_CAUSE);
  229. domain = irq_domain_add_linear(pmu->of_node, NR_PMU_IRQS,
  230. &irq_generic_chip_ops, NULL);
  231. if (!domain) {
  232. pr_err("%s: unable to add irq domain\n", name);
  233. return -ENOMEM;
  234. }
  235. ret = irq_alloc_domain_generic_chips(domain, NR_PMU_IRQS, 1, name,
  236. handle_level_irq,
  237. IRQ_NOREQUEST | IRQ_NOPROBE, 0,
  238. IRQ_GC_INIT_MASK_CACHE);
  239. if (ret) {
  240. pr_err("%s: unable to alloc irq domain gc: %d\n", name, ret);
  241. irq_domain_remove(domain);
  242. return ret;
  243. }
  244. gc = irq_get_domain_generic_chip(domain, 0);
  245. gc->reg_base = pmu->pmc_base;
  246. gc->chip_types[0].regs.mask = PMC_IRQ_MASK;
  247. gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
  248. gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
  249. pmu->irq_domain = domain;
  250. pmu->irq_gc = gc;
  251. irq_set_handler_data(irq, pmu);
  252. irq_set_chained_handler(irq, pmu_irq_handler);
  253. return 0;
  254. }
  255. int __init dove_init_pmu_legacy(const struct dove_pmu_initdata *initdata)
  256. {
  257. const struct dove_pmu_domain_initdata *domain_initdata;
  258. struct pmu_data *pmu;
  259. int ret;
  260. pmu = kzalloc(sizeof(*pmu), GFP_KERNEL);
  261. if (!pmu)
  262. return -ENOMEM;
  263. spin_lock_init(&pmu->lock);
  264. pmu->pmc_base = initdata->pmc_base;
  265. pmu->pmu_base = initdata->pmu_base;
  266. pmu_reset_init(pmu);
  267. for (domain_initdata = initdata->domains; domain_initdata->name;
  268. domain_initdata++) {
  269. struct pmu_domain *domain;
  270. domain = kzalloc(sizeof(*domain), GFP_KERNEL);
  271. if (domain) {
  272. domain->pmu = pmu;
  273. domain->pwr_mask = domain_initdata->pwr_mask;
  274. domain->rst_mask = domain_initdata->rst_mask;
  275. domain->iso_mask = domain_initdata->iso_mask;
  276. domain->base.name = domain_initdata->name;
  277. __pmu_domain_register(domain, NULL);
  278. }
  279. }
  280. ret = dove_init_pmu_irq(pmu, initdata->irq);
  281. if (ret)
  282. pr_err("dove_init_pmu_irq() failed: %d\n", ret);
  283. if (pmu->irq_domain)
  284. irq_domain_associate_many(pmu->irq_domain,
  285. initdata->irq_domain_start,
  286. 0, NR_PMU_IRQS);
  287. return 0;
  288. }
  289. /*
  290. * pmu: power-manager@d0000 {
  291. * compatible = "marvell,dove-pmu";
  292. * reg = <0xd0000 0x8000> <0xd8000 0x8000>;
  293. * interrupts = <33>;
  294. * interrupt-controller;
  295. * #reset-cells = 1;
  296. * vpu_domain: vpu-domain {
  297. * #power-domain-cells = <0>;
  298. * marvell,pmu_pwr_mask = <0x00000008>;
  299. * marvell,pmu_iso_mask = <0x00000001>;
  300. * resets = <&pmu 16>;
  301. * };
  302. * gpu_domain: gpu-domain {
  303. * #power-domain-cells = <0>;
  304. * marvell,pmu_pwr_mask = <0x00000004>;
  305. * marvell,pmu_iso_mask = <0x00000002>;
  306. * resets = <&pmu 18>;
  307. * };
  308. * };
  309. */
  310. int __init dove_init_pmu(void)
  311. {
  312. struct device_node *np_pmu, *domains_node, *np;
  313. struct pmu_data *pmu;
  314. int ret, parent_irq;
  315. /* Lookup the PMU node */
  316. np_pmu = of_find_compatible_node(NULL, NULL, "marvell,dove-pmu");
  317. if (!np_pmu)
  318. return 0;
  319. domains_node = of_get_child_by_name(np_pmu, "domains");
  320. if (!domains_node) {
  321. pr_err("%pOFn: failed to find domains sub-node\n", np_pmu);
  322. return 0;
  323. }
  324. pmu = kzalloc(sizeof(*pmu), GFP_KERNEL);
  325. if (!pmu)
  326. return -ENOMEM;
  327. spin_lock_init(&pmu->lock);
  328. pmu->of_node = np_pmu;
  329. pmu->pmc_base = of_iomap(pmu->of_node, 0);
  330. pmu->pmu_base = of_iomap(pmu->of_node, 1);
  331. if (!pmu->pmc_base || !pmu->pmu_base) {
  332. pr_err("%pOFn: failed to map PMU\n", np_pmu);
  333. iounmap(pmu->pmu_base);
  334. iounmap(pmu->pmc_base);
  335. kfree(pmu);
  336. return -ENOMEM;
  337. }
  338. pmu_reset_init(pmu);
  339. for_each_available_child_of_node(domains_node, np) {
  340. struct of_phandle_args args;
  341. struct pmu_domain *domain;
  342. domain = kzalloc(sizeof(*domain), GFP_KERNEL);
  343. if (!domain)
  344. break;
  345. domain->pmu = pmu;
  346. domain->base.name = kasprintf(GFP_KERNEL, "%pOFn", np);
  347. if (!domain->base.name) {
  348. kfree(domain);
  349. break;
  350. }
  351. of_property_read_u32(np, "marvell,pmu_pwr_mask",
  352. &domain->pwr_mask);
  353. of_property_read_u32(np, "marvell,pmu_iso_mask",
  354. &domain->iso_mask);
  355. /*
  356. * We parse the reset controller property directly here
  357. * to ensure that we can operate when the reset controller
  358. * support is not configured into the kernel.
  359. */
  360. ret = of_parse_phandle_with_args(np, "resets", "#reset-cells",
  361. 0, &args);
  362. if (ret == 0) {
  363. if (args.np == pmu->of_node)
  364. domain->rst_mask = BIT(args.args[0]);
  365. of_node_put(args.np);
  366. }
  367. __pmu_domain_register(domain, np);
  368. }
  369. /* Loss of the interrupt controller is not a fatal error. */
  370. parent_irq = irq_of_parse_and_map(pmu->of_node, 0);
  371. if (!parent_irq) {
  372. pr_err("%pOFn: no interrupt specified\n", np_pmu);
  373. } else {
  374. ret = dove_init_pmu_irq(pmu, parent_irq);
  375. if (ret)
  376. pr_err("dove_init_pmu_irq() failed: %d\n", ret);
  377. }
  378. return 0;
  379. }