soc.c 8.7 KB

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  1. /*
  2. * Copyright (C) 2015 Atmel
  3. *
  4. * Alexandre Belloni <alexandre.belloni@free-electrons.com
  5. * Boris Brezillon <boris.brezillon@free-electrons.com
  6. *
  7. * This file is licensed under the terms of the GNU General Public
  8. * License version 2. This program is licensed "as is" without any
  9. * warranty of any kind, whether express or implied.
  10. *
  11. */
  12. #define pr_fmt(fmt) "AT91: " fmt
  13. #include <linux/io.h>
  14. #include <linux/of.h>
  15. #include <linux/of_address.h>
  16. #include <linux/of_platform.h>
  17. #include <linux/slab.h>
  18. #include <linux/sys_soc.h>
  19. #include "soc.h"
  20. #define AT91_DBGU_CIDR 0x40
  21. #define AT91_DBGU_EXID 0x44
  22. #define AT91_CHIPID_CIDR 0x00
  23. #define AT91_CHIPID_EXID 0x04
  24. #define AT91_CIDR_VERSION(x) ((x) & 0x1f)
  25. #define AT91_CIDR_EXT BIT(31)
  26. #define AT91_CIDR_MATCH_MASK 0x7fffffe0
  27. static const struct at91_soc __initconst socs[] = {
  28. #ifdef CONFIG_SOC_AT91RM9200
  29. AT91_SOC(AT91RM9200_CIDR_MATCH, 0, "at91rm9200 BGA", "at91rm9200"),
  30. #endif
  31. #ifdef CONFIG_SOC_AT91SAM9
  32. AT91_SOC(AT91SAM9260_CIDR_MATCH, 0, "at91sam9260", NULL),
  33. AT91_SOC(AT91SAM9261_CIDR_MATCH, 0, "at91sam9261", NULL),
  34. AT91_SOC(AT91SAM9263_CIDR_MATCH, 0, "at91sam9263", NULL),
  35. AT91_SOC(AT91SAM9G20_CIDR_MATCH, 0, "at91sam9g20", NULL),
  36. AT91_SOC(AT91SAM9RL64_CIDR_MATCH, 0, "at91sam9rl64", NULL),
  37. AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M11_EXID_MATCH,
  38. "at91sam9m11", "at91sam9g45"),
  39. AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M10_EXID_MATCH,
  40. "at91sam9m10", "at91sam9g45"),
  41. AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G46_EXID_MATCH,
  42. "at91sam9g46", "at91sam9g45"),
  43. AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G45_EXID_MATCH,
  44. "at91sam9g45", "at91sam9g45"),
  45. AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G15_EXID_MATCH,
  46. "at91sam9g15", "at91sam9x5"),
  47. AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G35_EXID_MATCH,
  48. "at91sam9g35", "at91sam9x5"),
  49. AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X35_EXID_MATCH,
  50. "at91sam9x35", "at91sam9x5"),
  51. AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G25_EXID_MATCH,
  52. "at91sam9g25", "at91sam9x5"),
  53. AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X25_EXID_MATCH,
  54. "at91sam9x25", "at91sam9x5"),
  55. AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN12_EXID_MATCH,
  56. "at91sam9cn12", "at91sam9n12"),
  57. AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9N12_EXID_MATCH,
  58. "at91sam9n12", "at91sam9n12"),
  59. AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN11_EXID_MATCH,
  60. "at91sam9cn11", "at91sam9n12"),
  61. AT91_SOC(AT91SAM9XE128_CIDR_MATCH, 0, "at91sam9xe128", "at91sam9xe128"),
  62. AT91_SOC(AT91SAM9XE256_CIDR_MATCH, 0, "at91sam9xe256", "at91sam9xe256"),
  63. AT91_SOC(AT91SAM9XE512_CIDR_MATCH, 0, "at91sam9xe512", "at91sam9xe512"),
  64. AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_EXID_MATCH,
  65. "sam9x60", "sam9x60"),
  66. #endif
  67. #ifdef CONFIG_SOC_SAMA5
  68. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D21CU_EXID_MATCH,
  69. "sama5d21", "sama5d2"),
  70. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D22CU_EXID_MATCH,
  71. "sama5d22", "sama5d2"),
  72. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D225C_D1M_EXID_MATCH,
  73. "sama5d225c 16MiB SiP", "sama5d2"),
  74. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D23CU_EXID_MATCH,
  75. "sama5d23", "sama5d2"),
  76. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D24CX_EXID_MATCH,
  77. "sama5d24", "sama5d2"),
  78. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D24CU_EXID_MATCH,
  79. "sama5d24", "sama5d2"),
  80. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D26CU_EXID_MATCH,
  81. "sama5d26", "sama5d2"),
  82. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27CU_EXID_MATCH,
  83. "sama5d27", "sama5d2"),
  84. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27CN_EXID_MATCH,
  85. "sama5d27", "sama5d2"),
  86. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_D1G_EXID_MATCH,
  87. "sama5d27c 128MiB SiP", "sama5d2"),
  88. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_D5M_EXID_MATCH,
  89. "sama5d27c 64MiB SiP", "sama5d2"),
  90. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_LD1G_EXID_MATCH,
  91. "sama5d27c 128MiB LPDDR2 SiP", "sama5d2"),
  92. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_LD2G_EXID_MATCH,
  93. "sama5d27c 256MiB LPDDR2 SiP", "sama5d2"),
  94. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28CU_EXID_MATCH,
  95. "sama5d28", "sama5d2"),
  96. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28CN_EXID_MATCH,
  97. "sama5d28", "sama5d2"),
  98. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_D1G_EXID_MATCH,
  99. "sama5d28c 128MiB SiP", "sama5d2"),
  100. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_LD1G_EXID_MATCH,
  101. "sama5d28c 128MiB LPDDR2 SiP", "sama5d2"),
  102. AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_LD2G_EXID_MATCH,
  103. "sama5d28c 256MiB LPDDR2 SiP", "sama5d2"),
  104. AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D31_EXID_MATCH,
  105. "sama5d31", "sama5d3"),
  106. AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D33_EXID_MATCH,
  107. "sama5d33", "sama5d3"),
  108. AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D34_EXID_MATCH,
  109. "sama5d34", "sama5d3"),
  110. AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D35_EXID_MATCH,
  111. "sama5d35", "sama5d3"),
  112. AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D36_EXID_MATCH,
  113. "sama5d36", "sama5d3"),
  114. AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D41_EXID_MATCH,
  115. "sama5d41", "sama5d4"),
  116. AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D42_EXID_MATCH,
  117. "sama5d42", "sama5d4"),
  118. AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D43_EXID_MATCH,
  119. "sama5d43", "sama5d4"),
  120. AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D44_EXID_MATCH,
  121. "sama5d44", "sama5d4"),
  122. #endif
  123. #ifdef CONFIG_SOC_SAMV7
  124. AT91_SOC(SAME70Q21_CIDR_MATCH, SAME70Q21_EXID_MATCH,
  125. "same70q21", "same7"),
  126. AT91_SOC(SAME70Q20_CIDR_MATCH, SAME70Q20_EXID_MATCH,
  127. "same70q20", "same7"),
  128. AT91_SOC(SAME70Q19_CIDR_MATCH, SAME70Q19_EXID_MATCH,
  129. "same70q19", "same7"),
  130. AT91_SOC(SAMS70Q21_CIDR_MATCH, SAMS70Q21_EXID_MATCH,
  131. "sams70q21", "sams7"),
  132. AT91_SOC(SAMS70Q20_CIDR_MATCH, SAMS70Q20_EXID_MATCH,
  133. "sams70q20", "sams7"),
  134. AT91_SOC(SAMS70Q19_CIDR_MATCH, SAMS70Q19_EXID_MATCH,
  135. "sams70q19", "sams7"),
  136. AT91_SOC(SAMV71Q21_CIDR_MATCH, SAMV71Q21_EXID_MATCH,
  137. "samv71q21", "samv7"),
  138. AT91_SOC(SAMV71Q20_CIDR_MATCH, SAMV71Q20_EXID_MATCH,
  139. "samv71q20", "samv7"),
  140. AT91_SOC(SAMV71Q19_CIDR_MATCH, SAMV71Q19_EXID_MATCH,
  141. "samv71q19", "samv7"),
  142. AT91_SOC(SAMV70Q20_CIDR_MATCH, SAMV70Q20_EXID_MATCH,
  143. "samv70q20", "samv7"),
  144. AT91_SOC(SAMV70Q19_CIDR_MATCH, SAMV70Q19_EXID_MATCH,
  145. "samv70q19", "samv7"),
  146. #endif
  147. { /* sentinel */ },
  148. };
  149. static int __init at91_get_cidr_exid_from_dbgu(u32 *cidr, u32 *exid)
  150. {
  151. struct device_node *np;
  152. void __iomem *regs;
  153. np = of_find_compatible_node(NULL, NULL, "atmel,at91rm9200-dbgu");
  154. if (!np)
  155. np = of_find_compatible_node(NULL, NULL,
  156. "atmel,at91sam9260-dbgu");
  157. if (!np)
  158. return -ENODEV;
  159. regs = of_iomap(np, 0);
  160. of_node_put(np);
  161. if (!regs) {
  162. pr_warn("Could not map DBGU iomem range");
  163. return -ENXIO;
  164. }
  165. *cidr = readl(regs + AT91_DBGU_CIDR);
  166. *exid = readl(regs + AT91_DBGU_EXID);
  167. iounmap(regs);
  168. return 0;
  169. }
  170. static int __init at91_get_cidr_exid_from_chipid(u32 *cidr, u32 *exid)
  171. {
  172. struct device_node *np;
  173. void __iomem *regs;
  174. np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-chipid");
  175. if (!np)
  176. return -ENODEV;
  177. regs = of_iomap(np, 0);
  178. of_node_put(np);
  179. if (!regs) {
  180. pr_warn("Could not map DBGU iomem range");
  181. return -ENXIO;
  182. }
  183. *cidr = readl(regs + AT91_CHIPID_CIDR);
  184. *exid = readl(regs + AT91_CHIPID_EXID);
  185. iounmap(regs);
  186. return 0;
  187. }
  188. struct soc_device * __init at91_soc_init(const struct at91_soc *socs)
  189. {
  190. struct soc_device_attribute *soc_dev_attr;
  191. const struct at91_soc *soc;
  192. struct soc_device *soc_dev;
  193. u32 cidr, exid;
  194. int ret;
  195. /*
  196. * With SAMA5D2 and later SoCs, CIDR and EXID registers are no more
  197. * in the dbgu device but in the chipid device whose purpose is only
  198. * to expose these two registers.
  199. */
  200. ret = at91_get_cidr_exid_from_dbgu(&cidr, &exid);
  201. if (ret)
  202. ret = at91_get_cidr_exid_from_chipid(&cidr, &exid);
  203. if (ret) {
  204. if (ret == -ENODEV)
  205. pr_warn("Could not find identification node");
  206. return NULL;
  207. }
  208. for (soc = socs; soc->name; soc++) {
  209. if (soc->cidr_match != (cidr & AT91_CIDR_MATCH_MASK))
  210. continue;
  211. if (!(cidr & AT91_CIDR_EXT) || soc->exid_match == exid)
  212. break;
  213. }
  214. if (!soc->name) {
  215. pr_warn("Could not find matching SoC description\n");
  216. return NULL;
  217. }
  218. soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
  219. if (!soc_dev_attr)
  220. return NULL;
  221. soc_dev_attr->family = soc->family;
  222. soc_dev_attr->soc_id = soc->name;
  223. soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%X",
  224. AT91_CIDR_VERSION(cidr));
  225. soc_dev = soc_device_register(soc_dev_attr);
  226. if (IS_ERR(soc_dev)) {
  227. kfree(soc_dev_attr->revision);
  228. kfree(soc_dev_attr);
  229. pr_warn("Could not register SoC device\n");
  230. return NULL;
  231. }
  232. if (soc->family)
  233. pr_info("Detected SoC family: %s\n", soc->family);
  234. pr_info("Detected SoC: %s, revision %X\n", soc->name,
  235. AT91_CIDR_VERSION(cidr));
  236. return soc_dev;
  237. }
  238. static const struct of_device_id at91_soc_allowed_list[] __initconst = {
  239. { .compatible = "atmel,at91rm9200", },
  240. { .compatible = "atmel,at91sam9", },
  241. { .compatible = "atmel,sama5", },
  242. { .compatible = "atmel,samv7", },
  243. { }
  244. };
  245. static int __init atmel_soc_device_init(void)
  246. {
  247. struct device_node *np = of_find_node_by_path("/");
  248. if (!of_match_node(at91_soc_allowed_list, np))
  249. return 0;
  250. at91_soc_init(socs);
  251. return 0;
  252. }
  253. subsys_initcall(atmel_soc_device_init);