islpci_dev.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2002 Intersil Americas Inc.
  4. * Copyright (C) 2003 Herbert Valerio Riedel <hvr@gnu.org>
  5. * Copyright (C) 2003 Luis R. Rodriguez <mcgrof@ruslug.rutgers.edu>
  6. */
  7. #include <linux/hardirq.h>
  8. #include <linux/module.h>
  9. #include <linux/slab.h>
  10. #include <linux/netdevice.h>
  11. #include <linux/ethtool.h>
  12. #include <linux/pci.h>
  13. #include <linux/sched.h>
  14. #include <linux/etherdevice.h>
  15. #include <linux/delay.h>
  16. #include <linux/if_arp.h>
  17. #include <asm/io.h>
  18. #include "prismcompat.h"
  19. #include "isl_38xx.h"
  20. #include "isl_ioctl.h"
  21. #include "islpci_dev.h"
  22. #include "islpci_mgt.h"
  23. #include "islpci_eth.h"
  24. #include "oid_mgt.h"
  25. #define ISL3877_IMAGE_FILE "isl3877"
  26. #define ISL3886_IMAGE_FILE "isl3886"
  27. #define ISL3890_IMAGE_FILE "isl3890"
  28. MODULE_FIRMWARE(ISL3877_IMAGE_FILE);
  29. MODULE_FIRMWARE(ISL3886_IMAGE_FILE);
  30. MODULE_FIRMWARE(ISL3890_IMAGE_FILE);
  31. static int prism54_bring_down(islpci_private *);
  32. static int islpci_alloc_memory(islpci_private *);
  33. /* Temporary dummy MAC address to use until firmware is loaded.
  34. * The idea there is that some tools (such as nameif) may query
  35. * the MAC address before the netdev is 'open'. By using a valid
  36. * OUI prefix, they can process the netdev properly.
  37. * Of course, this is not the final/real MAC address. It doesn't
  38. * matter, as you are suppose to be able to change it anytime via
  39. * ndev->set_mac_address. Jean II */
  40. static const unsigned char dummy_mac[6] = { 0x00, 0x30, 0xB4, 0x00, 0x00, 0x00 };
  41. static int
  42. isl_upload_firmware(islpci_private *priv)
  43. {
  44. u32 reg, rc;
  45. void __iomem *device_base = priv->device_base;
  46. /* clear the RAMBoot and the Reset bit */
  47. reg = readl(device_base + ISL38XX_CTRL_STAT_REG);
  48. reg &= ~ISL38XX_CTRL_STAT_RESET;
  49. reg &= ~ISL38XX_CTRL_STAT_RAMBOOT;
  50. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  51. wmb();
  52. udelay(ISL38XX_WRITEIO_DELAY);
  53. /* set the Reset bit without reading the register ! */
  54. reg |= ISL38XX_CTRL_STAT_RESET;
  55. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  56. wmb();
  57. udelay(ISL38XX_WRITEIO_DELAY);
  58. /* clear the Reset bit */
  59. reg &= ~ISL38XX_CTRL_STAT_RESET;
  60. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  61. wmb();
  62. /* wait a while for the device to reboot */
  63. mdelay(50);
  64. {
  65. const struct firmware *fw_entry = NULL;
  66. long fw_len;
  67. const u32 *fw_ptr;
  68. rc = request_firmware(&fw_entry, priv->firmware, PRISM_FW_PDEV);
  69. if (rc) {
  70. printk(KERN_ERR
  71. "%s: request_firmware() failed for '%s'\n",
  72. "prism54", priv->firmware);
  73. return rc;
  74. }
  75. /* prepare the Direct Memory Base register */
  76. reg = ISL38XX_DEV_FIRMWARE_ADDRES;
  77. fw_ptr = (u32 *) fw_entry->data;
  78. fw_len = fw_entry->size;
  79. if (fw_len % 4) {
  80. printk(KERN_ERR
  81. "%s: firmware '%s' size is not multiple of 32bit, aborting!\n",
  82. "prism54", priv->firmware);
  83. release_firmware(fw_entry);
  84. return -EILSEQ; /* Illegal byte sequence */;
  85. }
  86. while (fw_len > 0) {
  87. long _fw_len =
  88. (fw_len >
  89. ISL38XX_MEMORY_WINDOW_SIZE) ?
  90. ISL38XX_MEMORY_WINDOW_SIZE : fw_len;
  91. u32 __iomem *dev_fw_ptr = device_base + ISL38XX_DIRECT_MEM_WIN;
  92. /* set the card's base address for writing the data */
  93. isl38xx_w32_flush(device_base, reg,
  94. ISL38XX_DIR_MEM_BASE_REG);
  95. wmb(); /* be paranoid */
  96. /* increment the write address for next iteration */
  97. reg += _fw_len;
  98. fw_len -= _fw_len;
  99. /* write the data to the Direct Memory Window 32bit-wise */
  100. /* memcpy_toio() doesn't guarantee 32bit writes :-| */
  101. while (_fw_len > 0) {
  102. /* use non-swapping writel() */
  103. __raw_writel(*fw_ptr, dev_fw_ptr);
  104. fw_ptr++, dev_fw_ptr++;
  105. _fw_len -= 4;
  106. }
  107. /* flush PCI posting */
  108. (void) readl(device_base + ISL38XX_PCI_POSTING_FLUSH);
  109. wmb(); /* be paranoid again */
  110. BUG_ON(_fw_len != 0);
  111. }
  112. BUG_ON(fw_len != 0);
  113. /* Firmware version is at offset 40 (also for "newmac") */
  114. printk(KERN_DEBUG "%s: firmware version: %.8s\n",
  115. priv->ndev->name, fw_entry->data + 40);
  116. release_firmware(fw_entry);
  117. }
  118. /* now reset the device
  119. * clear the Reset & ClkRun bit, set the RAMBoot bit */
  120. reg = readl(device_base + ISL38XX_CTRL_STAT_REG);
  121. reg &= ~ISL38XX_CTRL_STAT_CLKRUN;
  122. reg &= ~ISL38XX_CTRL_STAT_RESET;
  123. reg |= ISL38XX_CTRL_STAT_RAMBOOT;
  124. isl38xx_w32_flush(device_base, reg, ISL38XX_CTRL_STAT_REG);
  125. wmb();
  126. udelay(ISL38XX_WRITEIO_DELAY);
  127. /* set the reset bit latches the host override and RAMBoot bits
  128. * into the device for operation when the reset bit is reset */
  129. reg |= ISL38XX_CTRL_STAT_RESET;
  130. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  131. /* don't do flush PCI posting here! */
  132. wmb();
  133. udelay(ISL38XX_WRITEIO_DELAY);
  134. /* clear the reset bit should start the whole circus */
  135. reg &= ~ISL38XX_CTRL_STAT_RESET;
  136. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  137. /* don't do flush PCI posting here! */
  138. wmb();
  139. udelay(ISL38XX_WRITEIO_DELAY);
  140. return 0;
  141. }
  142. /******************************************************************************
  143. Device Interrupt Handler
  144. ******************************************************************************/
  145. irqreturn_t
  146. islpci_interrupt(int irq, void *config)
  147. {
  148. u32 reg;
  149. islpci_private *priv = config;
  150. struct net_device *ndev = priv->ndev;
  151. void __iomem *device = priv->device_base;
  152. int powerstate = ISL38XX_PSM_POWERSAVE_STATE;
  153. /* lock the interrupt handler */
  154. spin_lock(&priv->slock);
  155. /* received an interrupt request on a shared IRQ line
  156. * first check whether the device is in sleep mode */
  157. reg = readl(device + ISL38XX_CTRL_STAT_REG);
  158. if (reg & ISL38XX_CTRL_STAT_SLEEPMODE)
  159. /* device is in sleep mode, IRQ was generated by someone else */
  160. {
  161. #if VERBOSE > SHOW_ERROR_MESSAGES
  162. DEBUG(SHOW_TRACING, "Assuming someone else called the IRQ\n");
  163. #endif
  164. spin_unlock(&priv->slock);
  165. return IRQ_NONE;
  166. }
  167. /* check whether there is any source of interrupt on the device */
  168. reg = readl(device + ISL38XX_INT_IDENT_REG);
  169. /* also check the contents of the Interrupt Enable Register, because this
  170. * will filter out interrupt sources from other devices on the same irq ! */
  171. reg &= readl(device + ISL38XX_INT_EN_REG);
  172. reg &= ISL38XX_INT_SOURCES;
  173. if (reg != 0) {
  174. if (islpci_get_state(priv) != PRV_STATE_SLEEP)
  175. powerstate = ISL38XX_PSM_ACTIVE_STATE;
  176. /* reset the request bits in the Identification register */
  177. isl38xx_w32_flush(device, reg, ISL38XX_INT_ACK_REG);
  178. #if VERBOSE > SHOW_ERROR_MESSAGES
  179. DEBUG(SHOW_FUNCTION_CALLS,
  180. "IRQ: Identification register 0x%p 0x%x\n", device, reg);
  181. #endif
  182. /* check for each bit in the register separately */
  183. if (reg & ISL38XX_INT_IDENT_UPDATE) {
  184. #if VERBOSE > SHOW_ERROR_MESSAGES
  185. /* Queue has been updated */
  186. DEBUG(SHOW_TRACING, "IRQ: Update flag\n");
  187. DEBUG(SHOW_QUEUE_INDEXES,
  188. "CB drv Qs: [%i][%i][%i][%i][%i][%i]\n",
  189. le32_to_cpu(priv->control_block->
  190. driver_curr_frag[0]),
  191. le32_to_cpu(priv->control_block->
  192. driver_curr_frag[1]),
  193. le32_to_cpu(priv->control_block->
  194. driver_curr_frag[2]),
  195. le32_to_cpu(priv->control_block->
  196. driver_curr_frag[3]),
  197. le32_to_cpu(priv->control_block->
  198. driver_curr_frag[4]),
  199. le32_to_cpu(priv->control_block->
  200. driver_curr_frag[5])
  201. );
  202. DEBUG(SHOW_QUEUE_INDEXES,
  203. "CB dev Qs: [%i][%i][%i][%i][%i][%i]\n",
  204. le32_to_cpu(priv->control_block->
  205. device_curr_frag[0]),
  206. le32_to_cpu(priv->control_block->
  207. device_curr_frag[1]),
  208. le32_to_cpu(priv->control_block->
  209. device_curr_frag[2]),
  210. le32_to_cpu(priv->control_block->
  211. device_curr_frag[3]),
  212. le32_to_cpu(priv->control_block->
  213. device_curr_frag[4]),
  214. le32_to_cpu(priv->control_block->
  215. device_curr_frag[5])
  216. );
  217. #endif
  218. /* cleanup the data low transmit queue */
  219. islpci_eth_cleanup_transmit(priv, priv->control_block);
  220. /* device is in active state, update the
  221. * powerstate flag if necessary */
  222. powerstate = ISL38XX_PSM_ACTIVE_STATE;
  223. /* check all three queues in priority order
  224. * call the PIMFOR receive function until the
  225. * queue is empty */
  226. if (isl38xx_in_queue(priv->control_block,
  227. ISL38XX_CB_RX_MGMTQ) != 0) {
  228. #if VERBOSE > SHOW_ERROR_MESSAGES
  229. DEBUG(SHOW_TRACING,
  230. "Received frame in Management Queue\n");
  231. #endif
  232. islpci_mgt_receive(ndev);
  233. islpci_mgt_cleanup_transmit(ndev);
  234. /* Refill slots in receive queue */
  235. islpci_mgmt_rx_fill(ndev);
  236. /* no need to trigger the device, next
  237. islpci_mgt_transaction does it */
  238. }
  239. while (isl38xx_in_queue(priv->control_block,
  240. ISL38XX_CB_RX_DATA_LQ) != 0) {
  241. #if VERBOSE > SHOW_ERROR_MESSAGES
  242. DEBUG(SHOW_TRACING,
  243. "Received frame in Data Low Queue\n");
  244. #endif
  245. islpci_eth_receive(priv);
  246. }
  247. /* check whether the data transmit queues were full */
  248. if (priv->data_low_tx_full) {
  249. /* check whether the transmit is not full anymore */
  250. if (ISL38XX_CB_TX_QSIZE -
  251. isl38xx_in_queue(priv->control_block,
  252. ISL38XX_CB_TX_DATA_LQ) >=
  253. ISL38XX_MIN_QTHRESHOLD) {
  254. /* nope, the driver is ready for more network frames */
  255. netif_wake_queue(priv->ndev);
  256. /* reset the full flag */
  257. priv->data_low_tx_full = 0;
  258. }
  259. }
  260. }
  261. if (reg & ISL38XX_INT_IDENT_INIT) {
  262. /* Device has been initialized */
  263. #if VERBOSE > SHOW_ERROR_MESSAGES
  264. DEBUG(SHOW_TRACING,
  265. "IRQ: Init flag, device initialized\n");
  266. #endif
  267. wake_up(&priv->reset_done);
  268. }
  269. if (reg & ISL38XX_INT_IDENT_SLEEP) {
  270. /* Device intends to move to powersave state */
  271. #if VERBOSE > SHOW_ERROR_MESSAGES
  272. DEBUG(SHOW_TRACING, "IRQ: Sleep flag\n");
  273. #endif
  274. isl38xx_handle_sleep_request(priv->control_block,
  275. &powerstate,
  276. priv->device_base);
  277. }
  278. if (reg & ISL38XX_INT_IDENT_WAKEUP) {
  279. /* Device has been woken up to active state */
  280. #if VERBOSE > SHOW_ERROR_MESSAGES
  281. DEBUG(SHOW_TRACING, "IRQ: Wakeup flag\n");
  282. #endif
  283. isl38xx_handle_wakeup(priv->control_block,
  284. &powerstate, priv->device_base);
  285. }
  286. } else {
  287. #if VERBOSE > SHOW_ERROR_MESSAGES
  288. DEBUG(SHOW_TRACING, "Assuming someone else called the IRQ\n");
  289. #endif
  290. spin_unlock(&priv->slock);
  291. return IRQ_NONE;
  292. }
  293. /* sleep -> ready */
  294. if (islpci_get_state(priv) == PRV_STATE_SLEEP
  295. && powerstate == ISL38XX_PSM_ACTIVE_STATE)
  296. islpci_set_state(priv, PRV_STATE_READY);
  297. /* !sleep -> sleep */
  298. if (islpci_get_state(priv) != PRV_STATE_SLEEP
  299. && powerstate == ISL38XX_PSM_POWERSAVE_STATE)
  300. islpci_set_state(priv, PRV_STATE_SLEEP);
  301. /* unlock the interrupt handler */
  302. spin_unlock(&priv->slock);
  303. return IRQ_HANDLED;
  304. }
  305. /******************************************************************************
  306. Network Interface Control & Statistical functions
  307. ******************************************************************************/
  308. static int
  309. islpci_open(struct net_device *ndev)
  310. {
  311. u32 rc;
  312. islpci_private *priv = netdev_priv(ndev);
  313. /* reset data structures, upload firmware and reset device */
  314. rc = islpci_reset(priv,1);
  315. if (rc) {
  316. prism54_bring_down(priv);
  317. return rc; /* Returns informative message */
  318. }
  319. netif_start_queue(ndev);
  320. /* Turn off carrier if in STA or Ad-hoc mode. It will be turned on
  321. * once the firmware receives a trap of being associated
  322. * (GEN_OID_LINKSTATE). In other modes (AP or WDS or monitor) we
  323. * should just leave the carrier on as its expected the firmware
  324. * won't send us a trigger. */
  325. if (priv->iw_mode == IW_MODE_INFRA || priv->iw_mode == IW_MODE_ADHOC)
  326. netif_carrier_off(ndev);
  327. else
  328. netif_carrier_on(ndev);
  329. return 0;
  330. }
  331. static int
  332. islpci_close(struct net_device *ndev)
  333. {
  334. islpci_private *priv = netdev_priv(ndev);
  335. printk(KERN_DEBUG "%s: islpci_close ()\n", ndev->name);
  336. netif_stop_queue(ndev);
  337. return prism54_bring_down(priv);
  338. }
  339. static int
  340. prism54_bring_down(islpci_private *priv)
  341. {
  342. void __iomem *device_base = priv->device_base;
  343. u32 reg;
  344. /* we are going to shutdown the device */
  345. islpci_set_state(priv, PRV_STATE_PREBOOT);
  346. /* disable all device interrupts in case they weren't */
  347. isl38xx_disable_interrupts(priv->device_base);
  348. /* For safety reasons, we may want to ensure that no DMA transfer is
  349. * currently in progress by emptying the TX and RX queues. */
  350. /* wait until interrupts have finished executing on other CPUs */
  351. synchronize_irq(priv->pdev->irq);
  352. reg = readl(device_base + ISL38XX_CTRL_STAT_REG);
  353. reg &= ~(ISL38XX_CTRL_STAT_RESET | ISL38XX_CTRL_STAT_RAMBOOT);
  354. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  355. wmb();
  356. udelay(ISL38XX_WRITEIO_DELAY);
  357. reg |= ISL38XX_CTRL_STAT_RESET;
  358. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  359. wmb();
  360. udelay(ISL38XX_WRITEIO_DELAY);
  361. /* clear the Reset bit */
  362. reg &= ~ISL38XX_CTRL_STAT_RESET;
  363. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  364. wmb();
  365. /* wait a while for the device to reset */
  366. schedule_timeout_uninterruptible(msecs_to_jiffies(50));
  367. return 0;
  368. }
  369. static int
  370. islpci_upload_fw(islpci_private *priv)
  371. {
  372. islpci_state_t old_state;
  373. u32 rc;
  374. old_state = islpci_set_state(priv, PRV_STATE_BOOT);
  375. printk(KERN_DEBUG "%s: uploading firmware...\n", priv->ndev->name);
  376. rc = isl_upload_firmware(priv);
  377. if (rc) {
  378. /* error uploading the firmware */
  379. printk(KERN_ERR "%s: could not upload firmware ('%s')\n",
  380. priv->ndev->name, priv->firmware);
  381. islpci_set_state(priv, old_state);
  382. return rc;
  383. }
  384. printk(KERN_DEBUG "%s: firmware upload complete\n",
  385. priv->ndev->name);
  386. islpci_set_state(priv, PRV_STATE_POSTBOOT);
  387. return 0;
  388. }
  389. static int
  390. islpci_reset_if(islpci_private *priv)
  391. {
  392. long remaining;
  393. int result = -ETIME;
  394. int count;
  395. DEFINE_WAIT(wait);
  396. prepare_to_wait(&priv->reset_done, &wait, TASK_UNINTERRUPTIBLE);
  397. /* now the last step is to reset the interface */
  398. isl38xx_interface_reset(priv->device_base, priv->device_host_address);
  399. islpci_set_state(priv, PRV_STATE_PREINIT);
  400. for(count = 0; count < 2 && result; count++) {
  401. /* The software reset acknowledge needs about 220 msec here.
  402. * Be conservative and wait for up to one second. */
  403. remaining = schedule_timeout_uninterruptible(HZ);
  404. if(remaining > 0) {
  405. result = 0;
  406. break;
  407. }
  408. /* If we're here it's because our IRQ hasn't yet gone through.
  409. * Retry a bit more...
  410. */
  411. printk(KERN_ERR "%s: no 'reset complete' IRQ seen - retrying\n",
  412. priv->ndev->name);
  413. }
  414. finish_wait(&priv->reset_done, &wait);
  415. if (result) {
  416. printk(KERN_ERR "%s: interface reset failure\n", priv->ndev->name);
  417. return result;
  418. }
  419. islpci_set_state(priv, PRV_STATE_INIT);
  420. /* Now that the device is 100% up, let's allow
  421. * for the other interrupts --
  422. * NOTE: this is not *yet* true since we've only allowed the
  423. * INIT interrupt on the IRQ line. We can perhaps poll
  424. * the IRQ line until we know for sure the reset went through */
  425. isl38xx_enable_common_interrupts(priv->device_base);
  426. down_write(&priv->mib_sem);
  427. result = mgt_commit(priv);
  428. if (result) {
  429. printk(KERN_ERR "%s: interface reset failure\n", priv->ndev->name);
  430. up_write(&priv->mib_sem);
  431. return result;
  432. }
  433. up_write(&priv->mib_sem);
  434. islpci_set_state(priv, PRV_STATE_READY);
  435. printk(KERN_DEBUG "%s: interface reset complete\n", priv->ndev->name);
  436. return 0;
  437. }
  438. int
  439. islpci_reset(islpci_private *priv, int reload_firmware)
  440. {
  441. isl38xx_control_block *cb = /* volatile not needed */
  442. (isl38xx_control_block *) priv->control_block;
  443. unsigned counter;
  444. int rc;
  445. if (reload_firmware)
  446. islpci_set_state(priv, PRV_STATE_PREBOOT);
  447. else
  448. islpci_set_state(priv, PRV_STATE_POSTBOOT);
  449. printk(KERN_DEBUG "%s: resetting device...\n", priv->ndev->name);
  450. /* disable all device interrupts in case they weren't */
  451. isl38xx_disable_interrupts(priv->device_base);
  452. /* flush all management queues */
  453. priv->index_mgmt_tx = 0;
  454. priv->index_mgmt_rx = 0;
  455. /* clear the indexes in the frame pointer */
  456. for (counter = 0; counter < ISL38XX_CB_QCOUNT; counter++) {
  457. cb->driver_curr_frag[counter] = cpu_to_le32(0);
  458. cb->device_curr_frag[counter] = cpu_to_le32(0);
  459. }
  460. /* reset the mgmt receive queue */
  461. for (counter = 0; counter < ISL38XX_CB_MGMT_QSIZE; counter++) {
  462. isl38xx_fragment *frag = &cb->rx_data_mgmt[counter];
  463. frag->size = cpu_to_le16(MGMT_FRAME_SIZE);
  464. frag->flags = 0;
  465. frag->address = cpu_to_le32(priv->mgmt_rx[counter].pci_addr);
  466. }
  467. for (counter = 0; counter < ISL38XX_CB_RX_QSIZE; counter++) {
  468. cb->rx_data_low[counter].address =
  469. cpu_to_le32((u32) priv->pci_map_rx_address[counter]);
  470. }
  471. /* since the receive queues are filled with empty fragments, now we can
  472. * set the corresponding indexes in the Control Block */
  473. priv->control_block->driver_curr_frag[ISL38XX_CB_RX_DATA_LQ] =
  474. cpu_to_le32(ISL38XX_CB_RX_QSIZE);
  475. priv->control_block->driver_curr_frag[ISL38XX_CB_RX_MGMTQ] =
  476. cpu_to_le32(ISL38XX_CB_MGMT_QSIZE);
  477. /* reset the remaining real index registers and full flags */
  478. priv->free_data_rx = 0;
  479. priv->free_data_tx = 0;
  480. priv->data_low_tx_full = 0;
  481. if (reload_firmware) { /* Should we load the firmware ? */
  482. /* now that the data structures are cleaned up, upload
  483. * firmware and reset interface */
  484. rc = islpci_upload_fw(priv);
  485. if (rc) {
  486. printk(KERN_ERR "%s: islpci_reset: failure\n",
  487. priv->ndev->name);
  488. return rc;
  489. }
  490. }
  491. /* finally reset interface */
  492. rc = islpci_reset_if(priv);
  493. if (rc)
  494. printk(KERN_ERR "prism54: Your card/socket may be faulty, or IRQ line too busy :(\n");
  495. return rc;
  496. }
  497. /******************************************************************************
  498. Network device configuration functions
  499. ******************************************************************************/
  500. static int
  501. islpci_alloc_memory(islpci_private *priv)
  502. {
  503. int counter;
  504. #if VERBOSE > SHOW_ERROR_MESSAGES
  505. printk(KERN_DEBUG "islpci_alloc_memory\n");
  506. #endif
  507. /* remap the PCI device base address to accessible */
  508. if (!(priv->device_base =
  509. ioremap(pci_resource_start(priv->pdev, 0),
  510. ISL38XX_PCI_MEM_SIZE))) {
  511. /* error in remapping the PCI device memory address range */
  512. printk(KERN_ERR "PCI memory remapping failed\n");
  513. return -1;
  514. }
  515. /* memory layout for consistent DMA region:
  516. *
  517. * Area 1: Control Block for the device interface
  518. * Area 2: Power Save Mode Buffer for temporary frame storage. Be aware that
  519. * the number of supported stations in the AP determines the minimal
  520. * size of the buffer !
  521. */
  522. /* perform the allocation */
  523. priv->driver_mem_address = pci_alloc_consistent(priv->pdev,
  524. HOST_MEM_BLOCK,
  525. &priv->
  526. device_host_address);
  527. if (!priv->driver_mem_address) {
  528. /* error allocating the block of PCI memory */
  529. printk(KERN_ERR "%s: could not allocate DMA memory, aborting!",
  530. "prism54");
  531. return -1;
  532. }
  533. /* assign the Control Block to the first address of the allocated area */
  534. priv->control_block =
  535. (isl38xx_control_block *) priv->driver_mem_address;
  536. /* set the Power Save Buffer pointer directly behind the CB */
  537. priv->device_psm_buffer =
  538. priv->device_host_address + CONTROL_BLOCK_SIZE;
  539. /* make sure all buffer pointers are initialized */
  540. for (counter = 0; counter < ISL38XX_CB_QCOUNT; counter++) {
  541. priv->control_block->driver_curr_frag[counter] = cpu_to_le32(0);
  542. priv->control_block->device_curr_frag[counter] = cpu_to_le32(0);
  543. }
  544. priv->index_mgmt_rx = 0;
  545. memset(priv->mgmt_rx, 0, sizeof(priv->mgmt_rx));
  546. memset(priv->mgmt_tx, 0, sizeof(priv->mgmt_tx));
  547. /* allocate rx queue for management frames */
  548. if (islpci_mgmt_rx_fill(priv->ndev) < 0)
  549. goto out_free;
  550. /* now get the data rx skb's */
  551. memset(priv->data_low_rx, 0, sizeof (priv->data_low_rx));
  552. memset(priv->pci_map_rx_address, 0, sizeof (priv->pci_map_rx_address));
  553. for (counter = 0; counter < ISL38XX_CB_RX_QSIZE; counter++) {
  554. struct sk_buff *skb;
  555. /* allocate an sk_buff for received data frames storage
  556. * each frame on receive size consists of 1 fragment
  557. * include any required allignment operations */
  558. if (!(skb = dev_alloc_skb(MAX_FRAGMENT_SIZE_RX + 2))) {
  559. /* error allocating an sk_buff structure elements */
  560. printk(KERN_ERR "Error allocating skb.\n");
  561. skb = NULL;
  562. goto out_free;
  563. }
  564. skb_reserve(skb, (4 - (long) skb->data) & 0x03);
  565. /* add the new allocated sk_buff to the buffer array */
  566. priv->data_low_rx[counter] = skb;
  567. /* map the allocated skb data area to pci */
  568. priv->pci_map_rx_address[counter] =
  569. pci_map_single(priv->pdev, (void *) skb->data,
  570. MAX_FRAGMENT_SIZE_RX + 2,
  571. PCI_DMA_FROMDEVICE);
  572. if (pci_dma_mapping_error(priv->pdev,
  573. priv->pci_map_rx_address[counter])) {
  574. priv->pci_map_rx_address[counter] = 0;
  575. /* error mapping the buffer to device
  576. accessible memory address */
  577. printk(KERN_ERR "failed to map skb DMA'able\n");
  578. goto out_free;
  579. }
  580. }
  581. prism54_acl_init(&priv->acl);
  582. prism54_wpa_bss_ie_init(priv);
  583. if (mgt_init(priv))
  584. goto out_free;
  585. return 0;
  586. out_free:
  587. islpci_free_memory(priv);
  588. return -1;
  589. }
  590. int
  591. islpci_free_memory(islpci_private *priv)
  592. {
  593. int counter;
  594. if (priv->device_base)
  595. iounmap(priv->device_base);
  596. priv->device_base = NULL;
  597. /* free consistent DMA area... */
  598. if (priv->driver_mem_address)
  599. pci_free_consistent(priv->pdev, HOST_MEM_BLOCK,
  600. priv->driver_mem_address,
  601. priv->device_host_address);
  602. /* clear some dangling pointers */
  603. priv->driver_mem_address = NULL;
  604. priv->device_host_address = 0;
  605. priv->device_psm_buffer = 0;
  606. priv->control_block = NULL;
  607. /* clean up mgmt rx buffers */
  608. for (counter = 0; counter < ISL38XX_CB_MGMT_QSIZE; counter++) {
  609. struct islpci_membuf *buf = &priv->mgmt_rx[counter];
  610. if (buf->pci_addr)
  611. pci_unmap_single(priv->pdev, buf->pci_addr,
  612. buf->size, PCI_DMA_FROMDEVICE);
  613. buf->pci_addr = 0;
  614. kfree(buf->mem);
  615. buf->size = 0;
  616. buf->mem = NULL;
  617. }
  618. /* clean up data rx buffers */
  619. for (counter = 0; counter < ISL38XX_CB_RX_QSIZE; counter++) {
  620. if (priv->pci_map_rx_address[counter])
  621. pci_unmap_single(priv->pdev,
  622. priv->pci_map_rx_address[counter],
  623. MAX_FRAGMENT_SIZE_RX + 2,
  624. PCI_DMA_FROMDEVICE);
  625. priv->pci_map_rx_address[counter] = 0;
  626. if (priv->data_low_rx[counter])
  627. dev_kfree_skb(priv->data_low_rx[counter]);
  628. priv->data_low_rx[counter] = NULL;
  629. }
  630. /* Free the access control list and the WPA list */
  631. prism54_acl_clean(&priv->acl);
  632. prism54_wpa_bss_ie_clean(priv);
  633. mgt_clean(priv);
  634. return 0;
  635. }
  636. #if 0
  637. static void
  638. islpci_set_multicast_list(struct net_device *dev)
  639. {
  640. /* put device into promisc mode and let network layer handle it */
  641. }
  642. #endif
  643. static void islpci_ethtool_get_drvinfo(struct net_device *dev,
  644. struct ethtool_drvinfo *info)
  645. {
  646. strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
  647. strlcpy(info->version, DRV_VERSION, sizeof(info->version));
  648. }
  649. static const struct ethtool_ops islpci_ethtool_ops = {
  650. .get_drvinfo = islpci_ethtool_get_drvinfo,
  651. };
  652. static const struct net_device_ops islpci_netdev_ops = {
  653. .ndo_open = islpci_open,
  654. .ndo_stop = islpci_close,
  655. .ndo_start_xmit = islpci_eth_transmit,
  656. .ndo_tx_timeout = islpci_eth_tx_timeout,
  657. .ndo_set_mac_address = prism54_set_mac_address,
  658. .ndo_validate_addr = eth_validate_addr,
  659. };
  660. static struct device_type wlan_type = {
  661. .name = "wlan",
  662. };
  663. struct net_device *
  664. islpci_setup(struct pci_dev *pdev)
  665. {
  666. islpci_private *priv;
  667. struct net_device *ndev = alloc_etherdev(sizeof (islpci_private));
  668. if (!ndev)
  669. return ndev;
  670. pci_set_drvdata(pdev, ndev);
  671. SET_NETDEV_DEV(ndev, &pdev->dev);
  672. SET_NETDEV_DEVTYPE(ndev, &wlan_type);
  673. /* setup the structure members */
  674. ndev->base_addr = pci_resource_start(pdev, 0);
  675. ndev->irq = pdev->irq;
  676. /* initialize the function pointers */
  677. ndev->netdev_ops = &islpci_netdev_ops;
  678. ndev->wireless_handlers = &prism54_handler_def;
  679. ndev->ethtool_ops = &islpci_ethtool_ops;
  680. /* ndev->set_multicast_list = &islpci_set_multicast_list; */
  681. ndev->addr_len = ETH_ALEN;
  682. /* Get a non-zero dummy MAC address for nameif. Jean II */
  683. memcpy(ndev->dev_addr, dummy_mac, ETH_ALEN);
  684. ndev->watchdog_timeo = ISLPCI_TX_TIMEOUT;
  685. /* allocate a private device structure to the network device */
  686. priv = netdev_priv(ndev);
  687. priv->ndev = ndev;
  688. priv->pdev = pdev;
  689. priv->monitor_type = ARPHRD_IEEE80211;
  690. priv->ndev->type = (priv->iw_mode == IW_MODE_MONITOR) ?
  691. priv->monitor_type : ARPHRD_ETHER;
  692. /* Add pointers to enable iwspy support. */
  693. priv->wireless_data.spy_data = &priv->spy_data;
  694. ndev->wireless_data = &priv->wireless_data;
  695. /* save the start and end address of the PCI memory area */
  696. ndev->mem_start = (unsigned long) priv->device_base;
  697. ndev->mem_end = ndev->mem_start + ISL38XX_PCI_MEM_SIZE;
  698. #if VERBOSE > SHOW_ERROR_MESSAGES
  699. DEBUG(SHOW_TRACING, "PCI Memory remapped to 0x%p\n", priv->device_base);
  700. #endif
  701. init_waitqueue_head(&priv->reset_done);
  702. /* init the queue read locks, process wait counter */
  703. mutex_init(&priv->mgmt_lock);
  704. priv->mgmt_received = NULL;
  705. init_waitqueue_head(&priv->mgmt_wqueue);
  706. mutex_init(&priv->stats_lock);
  707. spin_lock_init(&priv->slock);
  708. /* init state machine with off#1 state */
  709. priv->state = PRV_STATE_OFF;
  710. priv->state_off = 1;
  711. /* initialize workqueue's */
  712. INIT_WORK(&priv->stats_work, prism54_update_stats);
  713. priv->stats_timestamp = 0;
  714. INIT_WORK(&priv->reset_task, islpci_do_reset_and_wake);
  715. priv->reset_task_pending = 0;
  716. /* allocate various memory areas */
  717. if (islpci_alloc_memory(priv))
  718. goto do_free_netdev;
  719. /* select the firmware file depending on the device id */
  720. switch (pdev->device) {
  721. case 0x3877:
  722. strcpy(priv->firmware, ISL3877_IMAGE_FILE);
  723. break;
  724. case 0x3886:
  725. strcpy(priv->firmware, ISL3886_IMAGE_FILE);
  726. break;
  727. default:
  728. strcpy(priv->firmware, ISL3890_IMAGE_FILE);
  729. break;
  730. }
  731. if (register_netdev(ndev)) {
  732. DEBUG(SHOW_ERROR_MESSAGES,
  733. "ERROR: register_netdev() failed\n");
  734. goto do_islpci_free_memory;
  735. }
  736. return ndev;
  737. do_islpci_free_memory:
  738. islpci_free_memory(priv);
  739. do_free_netdev:
  740. free_netdev(ndev);
  741. priv = NULL;
  742. return NULL;
  743. }
  744. islpci_state_t
  745. islpci_set_state(islpci_private *priv, islpci_state_t new_state)
  746. {
  747. islpci_state_t old_state;
  748. /* lock */
  749. old_state = priv->state;
  750. /* this means either a race condition or some serious error in
  751. * the driver code */
  752. switch (new_state) {
  753. case PRV_STATE_OFF:
  754. priv->state_off++;
  755. /* fall through */
  756. default:
  757. priv->state = new_state;
  758. break;
  759. case PRV_STATE_PREBOOT:
  760. /* there are actually many off-states, enumerated by
  761. * state_off */
  762. if (old_state == PRV_STATE_OFF)
  763. priv->state_off--;
  764. /* only if hw_unavailable is zero now it means we either
  765. * were in off#1 state, or came here from
  766. * somewhere else */
  767. if (!priv->state_off)
  768. priv->state = new_state;
  769. break;
  770. }
  771. #if 0
  772. printk(KERN_DEBUG "%s: state transition %d -> %d (off#%d)\n",
  773. priv->ndev->name, old_state, new_state, priv->state_off);
  774. #endif
  775. /* invariants */
  776. BUG_ON(priv->state_off < 0);
  777. BUG_ON(priv->state_off && (priv->state != PRV_STATE_OFF));
  778. BUG_ON(!priv->state_off && (priv->state == PRV_STATE_OFF));
  779. /* unlock */
  780. return old_state;
  781. }